drivers/phy/cadence/phy-cadence-sierra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cadence Sierra PHY Driver
   4  *
   5  * Based on the linux driver provided by Cadence
   6  *
   7  * Copyright (c) 2018 Cadence Design Systems
   8  * Author: Alan Douglas <adouglas@cadence.com>
   9  *
  10  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  11  * Jean-Jacques Hiblot <jjhiblot@ti.com>
  12  *
  13  */
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <generic-phy.h>
  17 #include <reset.h>
  18 #include <dm/device.h>
  19 #include <dm/device-internal.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/lists.h>
  22 #include <dm/read.h>
  23 #include <dm/uclass.h>
  24 #include <dm/devres.h>
  25 #include <linux/io.h>
  26 #include <dt-bindings/phy/phy.h>
  27 #include <regmap.h>
  28
  29 /* PHY register offsets */
  30 #define SIERRA_COMMON_CDB_OFFSET                        0x0
  31 #define SIERRA_MACRO_ID_REG                             0x0
  32 #define SIERRA_CMN_PLLLC_MODE_PREG                      0x48
  33 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG            0x49
  34 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG            0x4A
  35 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG             0x4B
  36 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG               0x4F
  37 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG               0x50
  38 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG     0x62
  39
  40 #define SIERRA_LANE_CDB_OFFSET(ln, offset)      \
  41                                 (0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
  42
  43 #define SIERRA_DET_STANDEC_A_PREG                       0x000
  44 #define SIERRA_DET_STANDEC_B_PREG                       0x001
  45 #define SIERRA_DET_STANDEC_C_PREG                       0x002
  46 #define SIERRA_DET_STANDEC_D_PREG                       0x003
  47 #define SIERRA_DET_STANDEC_E_PREG                       0x004
  48 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG           0x008
  49 #define SIERRA_PSM_A0IN_TMR_PREG                        0x009
  50 #define SIERRA_PSM_DIAG_PREG                            0x015
  51 #define SIERRA_PSC_TX_A0_PREG                           0x028
  52 #define SIERRA_PSC_TX_A1_PREG                           0x029
  53 #define SIERRA_PSC_TX_A2_PREG                           0x02A
  54 #define SIERRA_PSC_TX_A3_PREG                           0x02B
  55 #define SIERRA_PSC_RX_A0_PREG                           0x030
  56 #define SIERRA_PSC_RX_A1_PREG                           0x031
  57 #define SIERRA_PSC_RX_A2_PREG                           0x032
  58 #define SIERRA_PSC_RX_A3_PREG                           0x033
  59 #define SIERRA_PLLCTRL_SUBRATE_PREG                     0x03A
  60 #define SIERRA_PLLCTRL_GEN_D_PREG                       0x03E
  61 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG                 0x03F
  62 #define SIERRA_PLLCTRL_STATUS_PREG                      0x044
  63 #define SIERRA_CLKPATH_BIASTRIM_PREG                    0x04B
  64 #define SIERRA_DFE_BIASTRIM_PREG                        0x04C
  65 #define SIERRA_DRVCTRL_ATTEN_PREG                       0x06A
  66 #define SIERRA_CLKPATHCTRL_TMR_PREG                     0x081
  67 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG                0x085
  68 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG                0x086
  69 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG                0x087
  70 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG                0x088
  71 #define SIERRA_CREQ_CCLKDET_MODE01_PREG                 0x08E
  72 #define SIERRA_RX_CTLE_MAINTENANCE_PREG                 0x091
  73 #define SIERRA_CREQ_FSMCLK_SEL_PREG                     0x092
  74 #define SIERRA_CREQ_EQ_CTRL_PREG                        0x093
  75 #define SIERRA_CREQ_SPARE_PREG                          0x096
  76 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG             0x097
  77 #define SIERRA_CTLELUT_CTRL_PREG                        0x098
  78 #define SIERRA_DFE_ECMP_RATESEL_PREG                    0x0C0
  79 #define SIERRA_DFE_SMP_RATESEL_PREG                     0x0C1
  80 #define SIERRA_DEQ_PHALIGN_CTRL                         0x0C4
  81 #define SIERRA_DEQ_CONCUR_CTRL1_PREG                    0x0C8
  82 #define SIERRA_DEQ_CONCUR_CTRL2_PREG                    0x0C9
  83 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG                    0x0CD
  84 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG               0x0CE
  85 #define SIERRA_DEQ_ERRCMP_CTRL_PREG                     0x0D0
  86 #define SIERRA_DEQ_OFFSET_CTRL_PREG                     0x0D8
  87 #define SIERRA_DEQ_GAIN_CTRL_PREG                       0x0E0
  88 #define SIERRA_DEQ_VGATUNE_CTRL_PREG                    0x0E1
  89 #define SIERRA_DEQ_GLUT0                                0x0E8
  90 #define SIERRA_DEQ_GLUT1                                0x0E9
  91 #define SIERRA_DEQ_GLUT2                                0x0EA
  92 #define SIERRA_DEQ_GLUT3                                0x0EB
  93 #define SIERRA_DEQ_GLUT4                                0x0EC
  94 #define SIERRA_DEQ_GLUT5                                0x0ED
  95 #define SIERRA_DEQ_GLUT6                                0x0EE
  96 #define SIERRA_DEQ_GLUT7                                0x0EF
  97 #define SIERRA_DEQ_GLUT8                                0x0F0
  98 #define SIERRA_DEQ_GLUT9                                0x0F1
  99 #define SIERRA_DEQ_GLUT10                               0x0F2
 100 #define SIERRA_DEQ_GLUT11                               0x0F3
 101 #define SIERRA_DEQ_GLUT12                               0x0F4
 102 #define SIERRA_DEQ_GLUT13                               0x0F5
 103 #define SIERRA_DEQ_GLUT14                               0x0F6
 104 #define SIERRA_DEQ_GLUT15                               0x0F7
 105 #define SIERRA_DEQ_GLUT16                               0x0F8
 106 #define SIERRA_DEQ_ALUT0                                0x108
 107 #define SIERRA_DEQ_ALUT1                                0x109
 108 #define SIERRA_DEQ_ALUT2                                0x10A
 109 #define SIERRA_DEQ_ALUT3                                0x10B
 110 #define SIERRA_DEQ_ALUT4                                0x10C
 111 #define SIERRA_DEQ_ALUT5                                0x10D
 112 #define SIERRA_DEQ_ALUT6                                0x10E
 113 #define SIERRA_DEQ_ALUT7                                0x10F
 114 #define SIERRA_DEQ_ALUT8                                0x110
 115 #define SIERRA_DEQ_ALUT9                                0x111
 116 #define SIERRA_DEQ_ALUT10                               0x112
 117 #define SIERRA_DEQ_ALUT11                               0x113
 118 #define SIERRA_DEQ_ALUT12                               0x114
 119 #define SIERRA_DEQ_ALUT13                               0x115
 120 #define SIERRA_DEQ_DFETAP_CTRL_PREG                     0x128
 121 #define SIERRA_DFE_EN_1010_IGNORE_PREG                  0x134
 122 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 123 #define SIERRA_DEQ_TAU_CTRL2_PREG                       0x151
 124 #define SIERRA_DEQ_PICTRL_PREG                          0x161
 125 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG                 0x170
 126 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG                 0x171
 127 #define SIERRA_CPICAL_PICNT_MODE1_PREG                  0x174
 128 #define SIERRA_CPI_OUTBUF_RATESEL_PREG                  0x17C
 129 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG         0x183
 130 #define SIERRA_LFPSDET_SUPPORT_PREG                     0x188
 131 #define SIERRA_LFPSFILT_NS_PREG                         0x18A
 132 #define SIERRA_LFPSFILT_RD_PREG                         0x18B
 133 #define SIERRA_LFPSFILT_MP_PREG                         0x18C
 134 #define SIERRA_SIGDET_SUPPORT_PREG                      0x190
 135 #define SIERRA_SDFILT_H2L_A_PREG                        0x191
 136 #define SIERRA_SDFILT_L2H_PREG                          0x193
 137 #define SIERRA_RXBUFFER_CTLECTRL_PREG                   0x19E
 138 #define SIERRA_RXBUFFER_RCDFECTRL_PREG                  0x19F
 139 #define SIERRA_RXBUFFER_DFECTRL_PREG                    0x1A0
 140 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG            0x14F
 141 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 142
 143 #define SIERRA_PHY_CONFIG_CTRL_OFFSET                   0xc000
 144 #define SIERRA_PHY_PLL_CFG                              0xe
 145
 146 #define SIERRA_MACRO_ID                                 0x00007364
 147 #define SIERRA_MAX_LANES                                16
 148 #define PLL_LOCK_TIME                                   100
 149
 150 #define CDNS_SIERRA_INPUT_CLOCKS                        3
 151 enum cdns_sierra_clock_input {
 152         PHY_CLK,
 153         CMN_REFCLK_DIG_DIV,
 154         CMN_REFCLK1_DIG_DIV,
 155 };
 156
 157 static const struct reg_field macro_id_type =
 158                                 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 159 static const struct reg_field phy_pll_cfg_1 =
 160                                 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 161 static const struct reg_field pllctrl_lock =
 162                                 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
 163
 164 #define reset_control_assert(rst) cdns_reset_assert(rst)
 165 #define reset_control_deassert(rst) cdns_reset_deassert(rst)
 166 #define reset_control reset_ctl
 167
 168 struct cdns_sierra_inst {
 169         u32 phy_type;
 170         u32 num_lanes;
 171         u32 mlane;
 172         struct reset_ctl_bulk *lnk_rst;
 173 };
 174
 175 struct cdns_reg_pairs {
 176         u16 val;
 177         u32 off;
 178 };
 179
 180 struct cdns_sierra_data {
 181                 u32 id_value;
 182                 u8 block_offset_shift;
 183                 u8 reg_offset_shift;
 184                 u32 pcie_cmn_regs;
 185                 u32 pcie_ln_regs;
 186                 u32 usb_cmn_regs;
 187                 u32 usb_ln_regs;
 188                 struct cdns_reg_pairs *pcie_cmn_vals;
 189                 struct cdns_reg_pairs *pcie_ln_vals;
 190                 struct cdns_reg_pairs *usb_cmn_vals;
 191                 struct cdns_reg_pairs *usb_ln_vals;
 192 };
 193
 194 struct cdns_regmap_cdb_context {
 195         struct udevice *dev;
 196         void __iomem *base;
 197         u8 reg_offset_shift;
 198 };
 199
 200 struct cdns_sierra_phy {
 201         struct udevice *dev;
 202         void *base;
 203         size_t size;
 204         struct regmap *regmap;
 205         struct cdns_sierra_data *init_data;
 206         struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
 207         struct reset_control *phy_rst;
 208         struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 209         struct regmap *regmap_phy_config_ctrl;
 210         struct regmap *regmap_common_cdb;
 211         struct regmap_field *macro_id_type;
 212         struct regmap_field *phy_pll_cfg_1;
 213         struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
 214         struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
 215         int nsubnodes;
 216         u32 num_lanes;
 217         bool autoconf;
 218 };
 219
 220 static inline int cdns_reset_assert(struct reset_control *rst)
 221 {
 222         if (rst)
 223                 return reset_assert(rst);
 224         else
 225                 return 0;
 226 }
 227
 228 static inline int cdns_reset_deassert(struct reset_control *rst)
 229 {
 230         if (rst)
 231                 return reset_deassert(rst);
 232         else
 233                 return 0;
 234 }
 235
 236 static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy)
 237 {
 238         struct cdns_sierra_phy *sp = dev_get_priv(phy->dev);
 239         int index;
 240
 241         if (phy->id >= SIERRA_MAX_LANES)
 242                 return NULL;
 243
 244         for (index = 0; index < sp->nsubnodes; index++) {
 245                 if (phy->id == sp->phys[index].mlane)
 246                         return &sp->phys[index];
 247         }
 248
 249         return NULL;
 250 }
 251
 252 static int cdns_sierra_phy_init(struct phy *gphy)
 253 {
 254         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 255         struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
 256         struct regmap *regmap = phy->regmap;
 257         int i, j;
 258         struct cdns_reg_pairs *cmn_vals, *ln_vals;
 259         u32 num_cmn_regs, num_ln_regs;
 260
 261         /* Initialise the PHY registers, unless auto configured */
 262         if (phy->autoconf)
 263                 return 0;
 264
 265         clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
 266         clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
 267
 268         if (ins->phy_type == PHY_TYPE_PCIE) {
 269                 num_cmn_regs = phy->init_data->pcie_cmn_regs;
 270                 num_ln_regs = phy->init_data->pcie_ln_regs;
 271                 cmn_vals = phy->init_data->pcie_cmn_vals;
 272                 ln_vals = phy->init_data->pcie_ln_vals;
 273         } else if (ins->phy_type == PHY_TYPE_USB3) {
 274                 num_cmn_regs = phy->init_data->usb_cmn_regs;
 275                 num_ln_regs = phy->init_data->usb_ln_regs;
 276                 cmn_vals = phy->init_data->usb_cmn_vals;
 277                 ln_vals = phy->init_data->usb_ln_vals;
 278         } else {
 279                 return -EINVAL;
 280         }
 281
 282         regmap = phy->regmap_common_cdb;
 283         for (j = 0; j < num_cmn_regs ; j++)
 284                 regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
 285
 286         for (i = 0; i < ins->num_lanes; i++) {
 287                 for (j = 0; j < num_ln_regs ; j++) {
 288                         regmap = phy->regmap_lane_cdb[i + ins->mlane];
 289                         regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
 290                 }
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int cdns_sierra_phy_on(struct phy *gphy)
 297 {
 298         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 299         struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
 300         struct udevice *dev = gphy->dev;
 301         u32 val;
 302         int ret;
 303
 304         ret = reset_control_deassert(sp->phy_rst);
 305         if (ret) {
 306                 dev_err(dev, "Failed to take the PHY out of reset\n");
 307                 return ret;
 308         }
 309
 310         /* Take the PHY lane group out of reset */
 311         ret = reset_deassert_bulk(ins->lnk_rst);
 312         if (ret) {
 313                 dev_err(dev, "Failed to take the PHY lane out of reset\n");
 314                 return ret;
 315         }
 316
 317         ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
 318                                              val, val, 1000, PLL_LOCK_TIME);
 319         if (ret < 0)
 320                 dev_err(dev, "PLL lock of lane failed\n");
 321
 322         reset_control_assert(sp->phy_rst);
 323         reset_control_deassert(sp->phy_rst);
 324
 325         return ret;
 326 }
 327
 328 static int cdns_sierra_phy_off(struct phy *gphy)
 329 {
 330         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 331
 332         return reset_assert_bulk(ins->lnk_rst);
 333 }
 334
 335 static int cdns_sierra_phy_reset(struct phy *gphy)
 336 {
 337         struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
 338
 339         reset_control_assert(sp->phy_rst);
 340         reset_control_deassert(sp->phy_rst);
 341         return 0;
 342 };
 343
 344 static const struct phy_ops ops = {
 345         .init           = cdns_sierra_phy_init,
 346         .power_on       = cdns_sierra_phy_on,
 347         .power_off      = cdns_sierra_phy_off,
 348         .reset          = cdns_sierra_phy_reset,
 349 };
 350
 351 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
 352                                     ofnode child)
 353 {
 354         if (ofnode_read_u32(child, "reg", &inst->mlane))
 355                 return -EINVAL;
 356
 357         if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
 358                 return -EINVAL;
 359
 360         if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type))
 361                 return -EINVAL;
 362
 363         return 0;
 364 }
 365
 366 static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base,
 367                                        u32 block_offset, u8 block_offset_shift,
 368                                        u8 reg_offset_shift)
 369 {
 370         struct cdns_sierra_phy *sp = dev_get_priv(dev);
 371         struct regmap_config config;
 372
 373         config.r_start = (ulong)(base + (block_offset << block_offset_shift));
 374         config.r_size = sp->size - (block_offset << block_offset_shift);
 375         config.reg_offset_shift = reg_offset_shift;
 376         config.width = REGMAP_SIZE_16;
 377
 378         return devm_regmap_init(dev, NULL, NULL, &config);
 379 }
 380
 381 static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 382 {
 383         struct udevice *dev = sp->dev;
 384         struct regmap_field *field;
 385         struct regmap *regmap;
 386         int i;
 387
 388         regmap = sp->regmap_common_cdb;
 389         field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
 390         if (IS_ERR(field)) {
 391                 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
 392                 return PTR_ERR(field);
 393         }
 394         sp->macro_id_type = field;
 395
 396         regmap = sp->regmap_phy_config_ctrl;
 397         field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
 398         if (IS_ERR(field)) {
 399                 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
 400                 return PTR_ERR(field);
 401         }
 402         sp->phy_pll_cfg_1 = field;
 403
 404         for (i = 0; i < SIERRA_MAX_LANES; i++) {
 405                 regmap = sp->regmap_lane_cdb[i];
 406                 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
 407                 if (IS_ERR(field)) {
 408                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 409                         return PTR_ERR(field);
 410                 }
 411                 sp->pllctrl_lock[i] =  field;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
 418                                    void __iomem *base, u8 block_offset_shift,
 419                                    u8 reg_offset_shift)
 420 {
 421         struct udevice *dev = sp->dev;
 422         struct regmap *regmap;
 423         u32 block_offset;
 424         int i;
 425
 426         for (i = 0; i < SIERRA_MAX_LANES; i++) {
 427                 block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift);
 428                 regmap = cdns_regmap_init(dev, base, block_offset,
 429                                           block_offset_shift, reg_offset_shift);
 430                 if (IS_ERR(regmap)) {
 431                         dev_err(dev, "Failed to init lane CDB regmap\n");
 432                         return PTR_ERR(regmap);
 433                 }
 434                 sp->regmap_lane_cdb[i] = regmap;
 435         }
 436
 437         regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
 438                                   block_offset_shift, reg_offset_shift);
 439         if (IS_ERR(regmap)) {
 440                 dev_err(dev, "Failed to init common CDB regmap\n");
 441                 return PTR_ERR(regmap);
 442         }
 443         sp->regmap_common_cdb = regmap;
 444
 445         regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET,
 446                                   block_offset_shift, reg_offset_shift);
 447         if (IS_ERR(regmap)) {
 448                 dev_err(dev, "Failed to init PHY config and control regmap\n");
 449                 return PTR_ERR(regmap);
 450         }
 451         sp->regmap_phy_config_ctrl = regmap;
 452
 453         return 0;
 454 }
 455
 456 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
 457                                       struct udevice *dev)
 458 {
 459         struct clk *clk;
 460         int ret;
 461
 462         clk = devm_clk_get_optional(dev, "phy_clk");
 463         if (IS_ERR(clk)) {
 464                 dev_err(dev, "failed to get clock phy_clk\n");
 465                 return PTR_ERR(clk);
 466         }
 467         sp->input_clks[PHY_CLK] = clk;
 468
 469         clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
 470         if (IS_ERR(clk)) {
 471                 dev_err(dev, "cmn_refclk_dig_div clock not found\n");
 472                 ret = PTR_ERR(clk);
 473                 return ret;
 474         }
 475         sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
 476
 477         clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
 478         if (IS_ERR(clk)) {
 479                 dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
 480                 ret = PTR_ERR(clk);
 481                 return ret;
 482         }
 483         sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
 484
 485         return 0;
 486 }
 487
 488 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
 489                                       struct udevice *dev)
 490 {
 491         struct reset_control *rst;
 492
 493         rst = devm_reset_control_get(dev, "sierra_reset");
 494         if (IS_ERR(rst)) {
 495                 dev_err(dev, "failed to get reset\n");
 496                 return PTR_ERR(rst);
 497         }
 498         sp->phy_rst = rst;
 499
 500         return 0;
 501 }
 502
 503 static int cdns_sierra_phy_probe(struct udevice *dev)
 504 {
 505         struct cdns_sierra_phy *sp = dev_get_priv(dev);
 506         struct cdns_sierra_data *data;
 507         unsigned int id_value;
 508         int ret, node = 0;
 509         ofnode child;
 510
 511         sp->dev = dev;
 512
 513         sp->base =  devfdt_remap_addr_index(dev, 0);
 514         if (!sp->base) {
 515                 dev_err(dev, "unable to map regs\n");
 516                 return -ENOMEM;
 517         }
 518         devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size);
 519
 520         /* Get init data for this PHY */
 521         data = (struct cdns_sierra_data *)dev_get_driver_data(dev);
 522         sp->init_data = data;
 523
 524         ret = cdns_regmap_init_blocks(sp, sp->base, data->block_offset_shift,
 525                                       data->reg_offset_shift);
 526         if (ret)
 527                 return ret;
 528
 529         ret = cdns_regfield_init(sp);
 530         if (ret)
 531                 return ret;
 532
 533         ret = cdns_sierra_phy_get_clocks(sp, dev);
 534         if (ret)
 535                 return ret;
 536
 537         sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
 538         if (IS_ERR(sp->phy_rst)) {
 539                 dev_err(dev, "failed to get reset\n");
 540                 return PTR_ERR(sp->phy_rst);
 541         }
 542
 543         ret = cdns_sierra_phy_get_resets(sp, dev);
 544         if (ret)
 545                 return ret;
 546
 547         ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
 548         if (ret)
 549                 return ret;
 550
 551         /* Check that PHY is present */
 552         regmap_field_read(sp->macro_id_type, &id_value);
 553         if  (sp->init_data->id_value != id_value) {
 554                 dev_err(dev, "PHY not found 0x%x vs 0x%x\n",
 555                         sp->init_data->id_value, id_value);
 556                 ret = -EINVAL;
 557                 goto clk_disable;
 558         }
 559
 560         sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
 561
 562         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
 563                 if (!(ofnode_name_eq(child, "phy") ||
 564                       ofnode_name_eq(child, "link")))
 565                         continue;
 566
 567                 sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
 568                                                                      child);
 569                 if (IS_ERR(sp->phys[node].lnk_rst)) {
 570                         ret = PTR_ERR(sp->phys[node].lnk_rst);
 571                         dev_err(dev, "failed to get reset %s\n",
 572                                 ofnode_get_name(child));
 573                         goto put_child2;
 574                 }
 575
 576                 if (!sp->autoconf) {
 577                         ret = cdns_sierra_get_optional(&sp->phys[node], child);
 578                         if (ret) {
 579                                 dev_err(dev, "missing property in node %s\n",
 580                                         ofnode_get_name(child));
 581                                 goto put_child;
 582                         }
 583                 }
 584                 sp->num_lanes += sp->phys[node].num_lanes;
 585
 586                 node++;
 587         }
 588         sp->nsubnodes = node;
 589
 590         /* If more than one subnode, configure the PHY as multilink */
 591         if (!sp->autoconf && sp->nsubnodes > 1)
 592                 regmap_field_write(sp->phy_pll_cfg_1, 0x1);
 593
 594         dev_info(dev, "sierra probed\n");
 595         return 0;
 596
 597 put_child:
 598         node++;
 599 put_child2:
 600
 601 clk_disable:
 602         clk_disable_unprepare(sp->input_clks[PHY_CLK]);
 603         return ret;
 604 }
 605
 606 static int cdns_sierra_phy_remove(struct udevice *dev)
 607 {
 608         struct cdns_sierra_phy *phy = dev_get_priv(dev);
 609         int i;
 610
 611         reset_control_assert(phy->phy_rst);
 612
 613         /*
 614          * The device level resets will be put automatically.
 615          * Need to put the subnode resets here though.
 616          */
 617         for (i = 0; i < phy->nsubnodes; i++)
 618                 reset_assert_bulk(phy->phys[i].lnk_rst);
 619
 620         return 0;
 621 }
 622
 623 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
 624 static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
 625         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 626         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 627         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
 628         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
 629         {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
 630 };
 631
 632 /* refclk100MHz_32b_PCIe_ln_ext_ssc */
 633 static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
 634         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
 635         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
 636         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
 637         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
 638         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 639         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
 640         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
 641 };
 642
 643 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
 644 static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
 645         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 646         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 647         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
 648         {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
 649 };
 650
 651 /* refclk100MHz_20b_USB_ln_ext_ssc */
 652 static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
 653         {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
 654         {0x000F, SIERRA_DET_STANDEC_B_PREG},
 655         {0x55A5, SIERRA_DET_STANDEC_C_PREG},
 656         {0x69ad, SIERRA_DET_STANDEC_D_PREG},
 657         {0x0241, SIERRA_DET_STANDEC_E_PREG},
 658         {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
 659         {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
 660         {0xCF00, SIERRA_PSM_DIAG_PREG},
 661         {0x001F, SIERRA_PSC_TX_A0_PREG},
 662         {0x0007, SIERRA_PSC_TX_A1_PREG},
 663         {0x0003, SIERRA_PSC_TX_A2_PREG},
 664         {0x0003, SIERRA_PSC_TX_A3_PREG},
 665         {0x0FFF, SIERRA_PSC_RX_A0_PREG},
 666         {0x0003, SIERRA_PSC_RX_A1_PREG},
 667         {0x0003, SIERRA_PSC_RX_A2_PREG},
 668         {0x0001, SIERRA_PSC_RX_A3_PREG},
 669         {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
 670         {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
 671         {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
 672         {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
 673         {0x2512, SIERRA_DFE_BIASTRIM_PREG},
 674         {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
 675         {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
 676         {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
 677         {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 678         {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
 679         {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
 680         {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
 681         {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
 682         {0x0000, SIERRA_CREQ_SPARE_PREG},
 683         {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
 684         {0x8452, SIERRA_CTLELUT_CTRL_PREG},
 685         {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
 686         {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
 687         {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
 688         {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
 689         {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
 690         {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
 691         {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
 692         {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
 693         {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
 694         {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
 695         {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
 696         {0x0014, SIERRA_DEQ_GLUT0},
 697         {0x0014, SIERRA_DEQ_GLUT1},
 698         {0x0014, SIERRA_DEQ_GLUT2},
 699         {0x0014, SIERRA_DEQ_GLUT3},
 700         {0x0014, SIERRA_DEQ_GLUT4},
 701         {0x0014, SIERRA_DEQ_GLUT5},
 702         {0x0014, SIERRA_DEQ_GLUT6},
 703         {0x0014, SIERRA_DEQ_GLUT7},
 704         {0x0014, SIERRA_DEQ_GLUT8},
 705         {0x0014, SIERRA_DEQ_GLUT9},
 706         {0x0014, SIERRA_DEQ_GLUT10},
 707         {0x0014, SIERRA_DEQ_GLUT11},
 708         {0x0014, SIERRA_DEQ_GLUT12},
 709         {0x0014, SIERRA_DEQ_GLUT13},
 710         {0x0014, SIERRA_DEQ_GLUT14},
 711         {0x0014, SIERRA_DEQ_GLUT15},
 712         {0x0014, SIERRA_DEQ_GLUT16},
 713         {0x0BAE, SIERRA_DEQ_ALUT0},
 714         {0x0AEB, SIERRA_DEQ_ALUT1},
 715         {0x0A28, SIERRA_DEQ_ALUT2},
 716         {0x0965, SIERRA_DEQ_ALUT3},
 717         {0x08A2, SIERRA_DEQ_ALUT4},
 718         {0x07DF, SIERRA_DEQ_ALUT5},
 719         {0x071C, SIERRA_DEQ_ALUT6},
 720         {0x0659, SIERRA_DEQ_ALUT7},
 721         {0x0596, SIERRA_DEQ_ALUT8},
 722         {0x0514, SIERRA_DEQ_ALUT9},
 723         {0x0492, SIERRA_DEQ_ALUT10},
 724         {0x0410, SIERRA_DEQ_ALUT11},
 725         {0x038E, SIERRA_DEQ_ALUT12},
 726         {0x030C, SIERRA_DEQ_ALUT13},
 727         {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
 728         {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
 729         {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
 730         {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
 731         {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
 732         {0x0033, SIERRA_DEQ_PICTRL_PREG},
 733         {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
 734         {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
 735         {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
 736         {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
 737         {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
 738         {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
 739         {0x000F, SIERRA_LFPSFILT_NS_PREG},
 740         {0x0009, SIERRA_LFPSFILT_RD_PREG},
 741         {0x0001, SIERRA_LFPSFILT_MP_PREG},
 742         {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
 743         {0x8013, SIERRA_SDFILT_H2L_A_PREG},
 744         {0x8009, SIERRA_SDFILT_L2H_PREG},
 745         {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
 746         {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
 747         {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
 748 };
 749
 750 static const struct cdns_sierra_data cdns_map_sierra = {
 751         SIERRA_MACRO_ID,
 752         0x2,
 753         0x2,
 754         ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
 755         ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
 756         ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
 757         ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
 758         cdns_pcie_cmn_regs_ext_ssc,
 759         cdns_pcie_ln_regs_ext_ssc,
 760         cdns_usb_cmn_regs_ext_ssc,
 761         cdns_usb_ln_regs_ext_ssc,
 762 };
 763
 764 static const struct cdns_sierra_data cdns_ti_map_sierra = {
 765         SIERRA_MACRO_ID,
 766         0x0,
 767         0x1,
 768         ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
 769         ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
 770         ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
 771         ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
 772         cdns_pcie_cmn_regs_ext_ssc,
 773         cdns_pcie_ln_regs_ext_ssc,
 774         cdns_usb_cmn_regs_ext_ssc,
 775         cdns_usb_ln_regs_ext_ssc,
 776 };
 777
 778 static const struct udevice_id cdns_sierra_id_table[] = {
 779         {
 780                 .compatible = "cdns,sierra-phy-t0",
 781                 .data = (ulong)&cdns_map_sierra,
 782         },
 783         {
 784                 .compatible = "ti,sierra-phy-t0",
 785                 .data = (ulong)&cdns_ti_map_sierra,
 786         },
 787         {}
 788 };
 789
 790 U_BOOT_DRIVER(sierra_phy_provider) = {
 791         .name           = "cdns,sierra",
 792         .id             = UCLASS_PHY,
 793         .of_match       = cdns_sierra_id_table,
 794         .probe          = cdns_sierra_phy_probe,
 795         .remove         = cdns_sierra_phy_remove,
 796         .ops            = &ops,
 797         .priv_auto      = sizeof(struct cdns_sierra_phy),
 798 };