2 * Copyright (C) 2018 Ã
\81lvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/bcm63xx/usb-common.c:
5 * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
6 * Copyright 2013 Florian Fainelli <florian@openwrt.org>
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <generic-phy.h>
15 #include <power-domain.h>
18 #include <dm/device.h>
20 /* USBH PLL Control register */
21 #define USBH_PLL_REG 0x18
22 #define USBH_PLL_IDDQ_PWRDN BIT(9)
23 #define USBH_PLL_PWRDN_DELAY BIT(10)
25 /* USBH Swap Control register */
26 #define USBH_SWAP_REG 0x1c
27 #define USBH_SWAP_OHCI_DATA BIT(0)
28 #define USBH_SWAP_OHCI_ENDIAN BIT(1)
29 #define USBH_SWAP_EHCI_DATA BIT(3)
30 #define USBH_SWAP_EHCI_ENDIAN BIT(4)
32 /* USBH Setup register */
33 #define USBH_SETUP_REG 0x28
34 #define USBH_SETUP_IOC BIT(4)
35 #define USBH_SETUP_IPP BIT(5)
37 struct bcm6368_usbh_hw {
42 struct bcm6368_usbh_priv {
43 const struct bcm6368_usbh_hw *hw;
47 static int bcm6368_usbh_init(struct phy *phy)
49 struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
50 const struct bcm6368_usbh_hw *hw = priv->hw;
52 /* configure to work in native cpu endian */
53 clrsetbits_be32(priv->regs + USBH_SWAP_REG,
54 USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
55 USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
59 clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
61 setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
63 /* enable pll control */
65 clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
70 static struct phy_ops bcm6368_usbh_ops = {
71 .init = bcm6368_usbh_init,
74 static const struct bcm6368_usbh_hw bcm6328_hw = {
75 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
79 static const struct bcm6368_usbh_hw bcm6362_hw = {
84 static const struct bcm6368_usbh_hw bcm6368_hw = {
89 static const struct bcm6368_usbh_hw bcm63268_hw = {
90 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
91 .setup_clr = USBH_SETUP_IPP,
94 static const struct udevice_id bcm6368_usbh_ids[] = {
96 .compatible = "brcm,bcm6328-usbh",
97 .data = (ulong)&bcm6328_hw,
99 .compatible = "brcm,bcm6362-usbh",
100 .data = (ulong)&bcm6362_hw,
102 .compatible = "brcm,bcm6368-usbh",
103 .data = (ulong)&bcm6368_hw,
105 .compatible = "brcm,bcm63268-usbh",
106 .data = (ulong)&bcm63268_hw,
107 }, { /* sentinel */ }
110 static int bcm6368_usbh_probe(struct udevice *dev)
112 struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
113 const struct bcm6368_usbh_hw *hw =
114 (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
115 #if defined(CONFIG_POWER_DOMAIN)
116 struct power_domain pwr_dom;
118 struct reset_ctl rst_ctl;
124 addr = devfdt_get_addr_size_index(dev, 0, &size);
125 if (addr == FDT_ADDR_T_NONE)
128 priv->regs = ioremap(addr, size);
131 /* enable usbh clock */
132 ret = clk_get_by_name(dev, "usbh", &clk);
136 ret = clk_enable(&clk);
140 ret = clk_free(&clk);
144 #if defined(CONFIG_POWER_DOMAIN)
145 /* enable power domain */
146 ret = power_domain_get(dev, &pwr_dom);
150 ret = power_domain_on(&pwr_dom);
154 ret = power_domain_free(&pwr_dom);
160 ret = reset_get_by_index(dev, 0, &rst_ctl);
164 ret = reset_deassert(&rst_ctl);
168 ret = reset_free(&rst_ctl);
172 /* enable usb_ref clock */
173 ret = clk_get_by_name(dev, "usb_ref", &clk);
175 ret = clk_enable(&clk);
179 ret = clk_free(&clk);
189 U_BOOT_DRIVER(bcm6368_usbh) = {
190 .name = "bcm6368-usbh",
192 .of_match = bcm6368_usbh_ids,
193 .ops = &bcm6368_usbh_ops,
194 .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
195 .probe = bcm6368_usbh_probe,