1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
5 * Derived from linux/arch/mips/bcm63xx/usb-common.c:
6 * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright 2013 Florian Fainelli <florian@openwrt.org>
13 #include <generic-phy.h>
16 #include <power-domain.h>
19 #include <dm/device.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
23 /* USBH PLL Control register */
24 #define USBH_PLL_REG 0x18
25 #define USBH_PLL_IDDQ_PWRDN BIT(9)
26 #define USBH_PLL_PWRDN_DELAY BIT(10)
28 /* USBH Swap Control register */
29 #define USBH_SWAP_REG 0x1c
30 #define USBH_SWAP_OHCI_DATA BIT(0)
31 #define USBH_SWAP_OHCI_ENDIAN BIT(1)
32 #define USBH_SWAP_EHCI_DATA BIT(3)
33 #define USBH_SWAP_EHCI_ENDIAN BIT(4)
35 /* USBH Setup register */
36 #define USBH_SETUP_REG 0x28
37 #define USBH_SETUP_IOC BIT(4)
38 #define USBH_SETUP_IPP BIT(5)
40 struct bcm6368_usbh_hw {
45 struct bcm6368_usbh_priv {
46 const struct bcm6368_usbh_hw *hw;
50 static int bcm6368_usbh_init(struct phy *phy)
52 struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
53 const struct bcm6368_usbh_hw *hw = priv->hw;
55 /* configure to work in native cpu endian */
56 clrsetbits_be32(priv->regs + USBH_SWAP_REG,
57 USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
58 USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
62 clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
64 setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
66 /* enable pll control */
68 clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
73 static struct phy_ops bcm6368_usbh_ops = {
74 .init = bcm6368_usbh_init,
77 static const struct bcm6368_usbh_hw bcm6328_hw = {
78 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
82 static const struct bcm6368_usbh_hw bcm6362_hw = {
87 static const struct bcm6368_usbh_hw bcm6368_hw = {
92 static const struct bcm6368_usbh_hw bcm63268_hw = {
93 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
94 .setup_clr = USBH_SETUP_IPP,
97 static const struct udevice_id bcm6368_usbh_ids[] = {
99 .compatible = "brcm,bcm6328-usbh",
100 .data = (ulong)&bcm6328_hw,
102 .compatible = "brcm,bcm6362-usbh",
103 .data = (ulong)&bcm6362_hw,
105 .compatible = "brcm,bcm6368-usbh",
106 .data = (ulong)&bcm6368_hw,
108 .compatible = "brcm,bcm63268-usbh",
109 .data = (ulong)&bcm63268_hw,
110 }, { /* sentinel */ }
113 static int bcm6368_usbh_probe(struct udevice *dev)
115 struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
116 const struct bcm6368_usbh_hw *hw =
117 (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
118 #if defined(CONFIG_POWER_DOMAIN)
119 struct power_domain pwr_dom;
121 struct reset_ctl rst_ctl;
125 priv->regs = dev_remap_addr(dev);
131 /* enable usbh clock */
132 ret = clk_get_by_name(dev, "usbh", &clk);
136 ret = clk_enable(&clk);
140 ret = clk_free(&clk);
144 #if defined(CONFIG_POWER_DOMAIN)
145 /* enable power domain */
146 ret = power_domain_get(dev, &pwr_dom);
150 ret = power_domain_on(&pwr_dom);
154 ret = power_domain_free(&pwr_dom);
160 ret = reset_get_by_index(dev, 0, &rst_ctl);
164 ret = reset_deassert(&rst_ctl);
168 ret = reset_free(&rst_ctl);
172 /* enable usb_ref clock */
173 ret = clk_get_by_name(dev, "usb_ref", &clk);
175 ret = clk_enable(&clk);
179 ret = clk_free(&clk);
189 U_BOOT_DRIVER(bcm6368_usbh) = {
190 .name = "bcm6368-usbh",
192 .of_match = bcm6368_usbh_ids,
193 .ops = &bcm6368_usbh_ops,
194 .priv_auto = sizeof(struct bcm6368_usbh_priv),
195 .probe = bcm6368_usbh_probe,