drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <log.h>
  17 #include <dm/device.h>
  18 #include <generic-phy.h>
  19 #include <phy-sun4i-usb.h>
  20 #include <reset.h>
  21 #include <asm/gpio.h>
  22 #include <asm/io.h>
  23 #include <dm/device_compat.h>
  24 #include <linux/bitops.h>
  25 #include <linux/delay.h>
  26 #include <linux/err.h>
  27 #include <power/regulator.h>
  28
  29 #define REG_ISCR                        0x00
  30 #define REG_PHYCTL_A10                  0x04
  31 #define REG_PHYBIST                     0x08
  32 #define REG_PHYTUNE                     0x0c
  33 #define REG_PHYCTL_A33                  0x10
  34 #define REG_PHY_OTGCTL                  0x20
  35
  36 #define REG_HCI_PHY_CTL                 0x10
  37
  38 /* Common Control Bits for Both PHYs */
  39 #define PHY_PLL_BW                      0x03
  40 #define PHY_RES45_CAL_EN                0x0c
  41
  42 /* Private Control Bits for Each PHY */
  43 #define PHY_TX_AMPLITUDE_TUNE           0x20
  44 #define PHY_TX_SLEWRATE_TUNE            0x22
  45 #define PHY_DISCON_TH_SEL               0x2a
  46 #define PHY_SQUELCH_DETECT              0x3c
  47
  48 #define PHYCTL_DATA                     BIT(7)
  49 #define OTGCTL_ROUTE_MUSB               BIT(0)
  50
  51 #define PHY_TX_RATE                     BIT(4)
  52 #define PHY_TX_MAGNITUDE                BIT(2)
  53 #define PHY_TX_AMPLITUDE_LEN            5
  54
  55 #define PHY_RES45_CAL_DATA              BIT(0)
  56 #define PHY_RES45_CAL_LEN               1
  57 #define PHY_DISCON_TH_LEN               2
  58
  59 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  60 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  61 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  62 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  63
  64 /* A83T specific control bits for PHY0 */
  65 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  66 #define PHY_CTL_SIDDQ                   BIT(3)
  67 #define PHY_CTL_H3_SIDDQ                BIT(1)
  68
  69 /* A83T specific control bits for PHY2 HSIC */
  70 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  71 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  72 #define SUNXI_HSIC                      BIT(1)
  73
  74 #define MAX_PHYS                        4
  75
  76 enum sun4i_usb_phy_type {
  77         sun4i_a10_phy,
  78         sun6i_a31_phy,
  79         sun8i_a33_phy,
  80         sun8i_a83t_phy,
  81         sun8i_h3_phy,
  82         sun8i_r40_phy,
  83         sun8i_v3s_phy,
  84         sun50i_a64_phy,
  85         sun50i_h6_phy,
  86 };
  87
  88 struct sun4i_usb_phy_cfg {
  89         int num_phys;
  90         enum sun4i_usb_phy_type type;
  91         u32 disc_thresh;
  92         u32 hci_phy_ctl_clear;
  93         u8 phyctl_offset;
  94         bool dedicated_clocks;
  95         bool phy0_dual_route;
  96         int missing_phys;
  97 };
  98
  99 struct sun4i_usb_phy_info {
 100         const char *gpio_vbus;
 101         const char *gpio_vbus_det;
 102         const char *gpio_id_det;
 103 } phy_info[] = {
 104         {
 105                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
 106                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 107                 .gpio_id_det = CONFIG_USB0_ID_DET,
 108         },
 109         {
 110                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
 111                 .gpio_vbus_det = NULL,
 112                 .gpio_id_det = NULL,
 113         },
 114         {
 115                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 116                 .gpio_vbus_det = NULL,
 117                 .gpio_id_det = NULL,
 118         },
 119         {
 120                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 121                 .gpio_vbus_det = NULL,
 122                 .gpio_id_det = NULL,
 123         },
 124 };
 125
 126 struct sun4i_usb_phy_plat {
 127         void __iomem *pmu;
 128         struct gpio_desc gpio_vbus;
 129         struct gpio_desc gpio_vbus_det;
 130         struct gpio_desc gpio_id_det;
 131         struct clk clocks;
 132         struct reset_ctl resets;
 133         int id;
 134 };
 135
 136 struct sun4i_usb_phy_data {
 137         void __iomem *base;
 138         const struct sun4i_usb_phy_cfg *cfg;
 139         struct sun4i_usb_phy_plat *usb_phy;
 140         struct udevice *vbus_power_supply;
 141 };
 142
 143 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 144
 145 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 146 {
 147         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 148         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 149         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 150         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 151         int i;
 152
 153         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 154                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 155                 writel(0, phyctl);
 156         }
 157
 158         for (i = 0; i < len; i++) {
 159                 temp = readl(phyctl);
 160
 161                 /* clear the address portion */
 162                 temp &= ~(0xff << 8);
 163
 164                 /* set the address */
 165                 temp |= ((addr + i) << 8);
 166                 writel(temp, phyctl);
 167
 168                 /* set the data bit and clear usbc bit*/
 169                 temp = readb(phyctl);
 170                 if (data & 0x1)
 171                         temp |= PHYCTL_DATA;
 172                 else
 173                         temp &= ~PHYCTL_DATA;
 174                 temp &= ~usbc_bit;
 175                 writeb(temp, phyctl);
 176
 177                 /* pulse usbc_bit */
 178                 temp = readb(phyctl);
 179                 temp |= usbc_bit;
 180                 writeb(temp, phyctl);
 181
 182                 temp = readb(phyctl);
 183                 temp &= ~usbc_bit;
 184                 writeb(temp, phyctl);
 185
 186                 data >>= 1;
 187         }
 188 }
 189
 190 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 191 {
 192         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 193         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 194         u32 bits, reg_value;
 195
 196         if (!usb_phy->pmu)
 197                 return;
 198
 199         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 200                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 201
 202         /* A83T USB2 is HSIC */
 203         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 204                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 205                         SUNXI_HSIC;
 206
 207         reg_value = readl(usb_phy->pmu);
 208
 209         if (enable)
 210                 reg_value |= bits;
 211         else
 212                 reg_value &= ~bits;
 213
 214         writel(reg_value, usb_phy->pmu);
 215 }
 216
 217 static int sun4i_usb_phy_power_on(struct phy *phy)
 218 {
 219         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 220         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 221
 222         if (initial_usb_scan_delay) {
 223                 mdelay(initial_usb_scan_delay);
 224                 initial_usb_scan_delay = 0;
 225         }
 226
 227         /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
 228         if (phy->id == 0 && sun4i_usb_phy_vbus_detect(phy)) {
 229                 dev_warn(phy->dev, "External vbus detected, not enabling our own vbus\n");
 230                 return 0;
 231         }
 232
 233         if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
 234                 dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
 235
 236         return 0;
 237 }
 238
 239 static int sun4i_usb_phy_power_off(struct phy *phy)
 240 {
 241         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 242         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 243
 244         if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
 245                 dm_gpio_set_value(&usb_phy->gpio_vbus, 0);
 246
 247         return 0;
 248 }
 249
 250 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 251 {
 252         u32 regval;
 253
 254         regval = readl(data->base + REG_PHY_OTGCTL);
 255         if (!id_det) {
 256                 /* Host mode. Route phy0 to EHCI/OHCI */
 257                 regval &= ~OTGCTL_ROUTE_MUSB;
 258         } else {
 259                 /* Peripheral mode. Route phy0 to MUSB */
 260                 regval |= OTGCTL_ROUTE_MUSB;
 261         }
 262         writel(regval, data->base + REG_PHY_OTGCTL);
 263 }
 264
 265 static int sun4i_usb_phy_init(struct phy *phy)
 266 {
 267         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 268         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 269         u32 val;
 270         int ret;
 271
 272         ret = clk_enable(&usb_phy->clocks);
 273         if (ret) {
 274                 dev_err(phy->dev, "failed to enable usb_%ldphy clock\n",
 275                         phy->id);
 276                 return ret;
 277         }
 278
 279         ret = reset_deassert(&usb_phy->resets);
 280         if (ret) {
 281                 dev_err(phy->dev, "failed to deassert usb_%ldreset reset\n",
 282                         phy->id);
 283                 return ret;
 284         }
 285
 286         if (usb_phy->pmu && data->cfg->hci_phy_ctl_clear) {
 287                 val = readl(usb_phy->pmu + REG_HCI_PHY_CTL);
 288                 val &= ~data->cfg->hci_phy_ctl_clear;
 289                 writel(val, usb_phy->pmu + REG_HCI_PHY_CTL);
 290         }
 291
 292         if (data->cfg->type == sun8i_a83t_phy ||
 293             data->cfg->type == sun50i_h6_phy) {
 294                 if (phy->id == 0) {
 295                         val = readl(data->base + data->cfg->phyctl_offset);
 296                         val |= PHY_CTL_VBUSVLDEXT;
 297                         val &= ~PHY_CTL_SIDDQ;
 298                         writel(val, data->base + data->cfg->phyctl_offset);
 299                 }
 300         } else {
 301                 if (usb_phy->id == 0)
 302                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 303                                             PHY_RES45_CAL_DATA,
 304                                             PHY_RES45_CAL_LEN);
 305
 306                 /* Adjust PHY's magnitude and rate */
 307                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 308                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 309                                     PHY_TX_AMPLITUDE_LEN);
 310
 311                 /* Disconnect threshold adjustment */
 312                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 313                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 314         }
 315
 316 #ifdef CONFIG_USB_MUSB_SUNXI
 317         /* Needed for HCI and conflicts with MUSB, keep PHY0 on MUSB */
 318         if (usb_phy->id != 0)
 319                 sun4i_usb_phy_passby(phy, true);
 320
 321         /* Route PHY0 to MUSB to allow USB gadget */
 322         if (data->cfg->phy0_dual_route)
 323                 sun4i_usb_phy0_reroute(data, true);
 324 #else
 325         sun4i_usb_phy_passby(phy, true);
 326
 327         /* Route PHY0 to HCI to allow USB host */
 328         if (data->cfg->phy0_dual_route)
 329                 sun4i_usb_phy0_reroute(data, false);
 330 #endif
 331
 332         return 0;
 333 }
 334
 335 static int sun4i_usb_phy_exit(struct phy *phy)
 336 {
 337         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 338         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 339         int ret;
 340
 341         if (phy->id == 0) {
 342                 if (data->cfg->type == sun8i_a83t_phy ||
 343                     data->cfg->type == sun50i_h6_phy) {
 344                         void __iomem *phyctl = data->base +
 345                                 data->cfg->phyctl_offset;
 346
 347                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 348                 }
 349         }
 350
 351         sun4i_usb_phy_passby(phy, false);
 352
 353         ret = clk_disable(&usb_phy->clocks);
 354         if (ret) {
 355                 dev_err(phy->dev, "failed to disable usb_%ldphy clock\n",
 356                         phy->id);
 357                 return ret;
 358         }
 359
 360         ret = reset_assert(&usb_phy->resets);
 361         if (ret) {
 362                 dev_err(phy->dev, "failed to assert usb_%ldreset reset\n",
 363                         phy->id);
 364                 return ret;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int sun4i_usb_phy_xlate(struct phy *phy,
 371                                struct ofnode_phandle_args *args)
 372 {
 373         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 374
 375         if (args->args_count >= data->cfg->num_phys)
 376                 return -EINVAL;
 377
 378         if (data->cfg->missing_phys & BIT(args->args[0]))
 379                 return -ENODEV;
 380
 381         if (args->args_count)
 382                 phy->id = args->args[0];
 383         else
 384                 phy->id = 0;
 385
 386         debug("%s: phy_id = %ld\n", __func__, phy->id);
 387         return 0;
 388 }
 389
 390 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 391 {
 392         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 393         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 394         int err = 1, retries = 3;
 395
 396         if (dm_gpio_is_valid(&usb_phy->gpio_vbus_det)) {
 397                 err = dm_gpio_get_value(&usb_phy->gpio_vbus_det);
 398                 /*
 399                  * Vbus may have been provided by the board and just turned off
 400                  * some milliseconds ago on reset. What we're measuring then is
 401                  * a residual charge on Vbus. Sleep a bit and try again.
 402                  */
 403                 while (err > 0 && retries--) {
 404                         mdelay(100);
 405                         err = dm_gpio_get_value(&usb_phy->gpio_vbus_det);
 406                 }
 407         } else if (data->vbus_power_supply) {
 408                 err = regulator_get_enable(data->vbus_power_supply);
 409         }
 410
 411         return err;
 412 }
 413
 414 int sun4i_usb_phy_id_detect(struct phy *phy)
 415 {
 416         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 417         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 418
 419         if (!dm_gpio_is_valid(&usb_phy->gpio_id_det))
 420                 return -1;
 421
 422         return dm_gpio_get_value(&usb_phy->gpio_id_det);
 423 }
 424
 425 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
 426 {
 427         sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
 428 }
 429
 430 static struct phy_ops sun4i_usb_phy_ops = {
 431         .of_xlate = sun4i_usb_phy_xlate,
 432         .init = sun4i_usb_phy_init,
 433         .power_on = sun4i_usb_phy_power_on,
 434         .power_off = sun4i_usb_phy_power_off,
 435         .exit = sun4i_usb_phy_exit,
 436 };
 437
 438 static int sun4i_usb_phy_probe(struct udevice *dev)
 439 {
 440         struct sun4i_usb_phy_plat *plat = dev_get_plat(dev);
 441         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 442         int i, ret;
 443
 444         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 445         if (!data->cfg)
 446                 return -EINVAL;
 447
 448         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 449         if (IS_ERR(data->base))
 450                 return PTR_ERR(data->base);
 451
 452         device_get_supply_regulator(dev, "usb0_vbus_power-supply",
 453                                     &data->vbus_power_supply);
 454
 455         data->usb_phy = plat;
 456         for (i = 0; i < data->cfg->num_phys; i++) {
 457                 struct sun4i_usb_phy_plat *phy = &plat[i];
 458                 struct sun4i_usb_phy_info *info = &phy_info[i];
 459                 char name[16];
 460
 461                 if (data->cfg->missing_phys & BIT(i))
 462                         continue;
 463
 464                 ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus);
 465                 if (ret == 0) {
 466                         ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus");
 467                         if (ret)
 468                                 return ret;
 469                         ret = dm_gpio_set_dir_flags(&phy->gpio_vbus,
 470                                                     GPIOD_IS_OUT);
 471                         if (ret)
 472                                 return ret;
 473                         ret = dm_gpio_set_value(&phy->gpio_vbus, 0);
 474                         if (ret)
 475                                 return ret;
 476                 }
 477
 478                 ret = dm_gpio_lookup_name(info->gpio_vbus_det,
 479                                           &phy->gpio_vbus_det);
 480                 if (ret == 0) {
 481                         ret = dm_gpio_request(&phy->gpio_vbus_det,
 482                                               "usb_vbus_det");
 483                         if (ret)
 484                                 return ret;
 485                         ret = dm_gpio_set_dir_flags(&phy->gpio_vbus_det,
 486                                                     GPIOD_IS_IN);
 487                         if (ret)
 488                                 return ret;
 489                 }
 490
 491                 ret = dm_gpio_lookup_name(info->gpio_id_det, &phy->gpio_id_det);
 492                 if (ret == 0) {
 493                         ret = dm_gpio_request(&phy->gpio_id_det, "usb_id_det");
 494                         if (ret)
 495                                 return ret;
 496                         ret = dm_gpio_set_dir_flags(&phy->gpio_id_det,
 497                                                 GPIOD_IS_IN | GPIOD_PULL_UP);
 498                         if (ret)
 499                                 return ret;
 500                 }
 501
 502                 if (data->cfg->dedicated_clocks)
 503                         snprintf(name, sizeof(name), "usb%d_phy", i);
 504                 else
 505                         strlcpy(name, "usb_phy", sizeof(name));
 506
 507                 ret = clk_get_by_name(dev, name, &phy->clocks);
 508                 if (ret) {
 509                         dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
 510                         return ret;
 511                 }
 512
 513                 snprintf(name, sizeof(name), "usb%d_reset", i);
 514                 ret = reset_get_by_name(dev, name, &phy->resets);
 515                 if (ret) {
 516                         dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
 517                         return ret;
 518                 }
 519
 520                 if (i || data->cfg->phy0_dual_route) {
 521                         snprintf(name, sizeof(name), "pmu%d", i);
 522                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 523                         if (IS_ERR(phy->pmu))
 524                                 return PTR_ERR(phy->pmu);
 525                 }
 526
 527                 phy->id = i;
 528         };
 529
 530         debug("Allwinner Sun4I USB PHY driver loaded\n");
 531         return 0;
 532 }
 533
 534 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 535         .num_phys = 3,
 536         .type = sun4i_a10_phy,
 537         .disc_thresh = 3,
 538         .phyctl_offset = REG_PHYCTL_A10,
 539         .dedicated_clocks = false,
 540 };
 541
 542 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 543         .num_phys = 2,
 544         .type = sun4i_a10_phy,
 545         .disc_thresh = 2,
 546         .phyctl_offset = REG_PHYCTL_A10,
 547         .dedicated_clocks = false,
 548 };
 549
 550 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 551         .num_phys = 3,
 552         .type = sun6i_a31_phy,
 553         .disc_thresh = 3,
 554         .phyctl_offset = REG_PHYCTL_A10,
 555         .dedicated_clocks = true,
 556 };
 557
 558 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 559         .num_phys = 3,
 560         .type = sun4i_a10_phy,
 561         .disc_thresh = 2,
 562         .phyctl_offset = REG_PHYCTL_A10,
 563         .dedicated_clocks = false,
 564 };
 565
 566 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 567         .num_phys = 2,
 568         .type = sun4i_a10_phy,
 569         .disc_thresh = 3,
 570         .phyctl_offset = REG_PHYCTL_A10,
 571         .dedicated_clocks = true,
 572 };
 573
 574 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 575         .num_phys = 2,
 576         .type = sun8i_a33_phy,
 577         .disc_thresh = 3,
 578         .phyctl_offset = REG_PHYCTL_A33,
 579         .dedicated_clocks = true,
 580 };
 581
 582 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 583         .num_phys = 3,
 584         .type = sun8i_a83t_phy,
 585         .phyctl_offset = REG_PHYCTL_A33,
 586         .dedicated_clocks = true,
 587 };
 588
 589 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 590         .num_phys = 4,
 591         .type = sun8i_h3_phy,
 592         .disc_thresh = 3,
 593         .phyctl_offset = REG_PHYCTL_A33,
 594         .dedicated_clocks = true,
 595         .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 596         .phy0_dual_route = true,
 597 };
 598
 599 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 600         .num_phys = 3,
 601         .type = sun8i_r40_phy,
 602         .disc_thresh = 3,
 603         .phyctl_offset = REG_PHYCTL_A33,
 604         .dedicated_clocks = true,
 605         .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 606         .phy0_dual_route = true,
 607 };
 608
 609 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 610         .num_phys = 1,
 611         .type = sun8i_v3s_phy,
 612         .disc_thresh = 3,
 613         .phyctl_offset = REG_PHYCTL_A33,
 614         .dedicated_clocks = true,
 615         .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 616         .phy0_dual_route = true,
 617 };
 618
 619 static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
 620         .num_phys = 2,
 621         .type = sun50i_h6_phy,
 622         .phyctl_offset = REG_PHYCTL_A33,
 623         .dedicated_clocks = true,
 624         .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
 625         .phy0_dual_route = true,
 626 };
 627
 628 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 629         .num_phys = 2,
 630         .type = sun50i_a64_phy,
 631         .disc_thresh = 3,
 632         .phyctl_offset = REG_PHYCTL_A33,
 633         .dedicated_clocks = true,
 634         .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 635         .phy0_dual_route = true,
 636 };
 637
 638 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 639         .num_phys = 4,
 640         .type = sun50i_h6_phy,
 641         .disc_thresh = 3,
 642         .phyctl_offset = REG_PHYCTL_A33,
 643         .dedicated_clocks = true,
 644         .phy0_dual_route = true,
 645         .missing_phys = BIT(1) | BIT(2),
 646 };
 647
 648 static const struct udevice_id sun4i_usb_phy_ids[] = {
 649         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 650         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 651         { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 652         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 653         { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
 654         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 655         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 656         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 657         { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
 658         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 659         { .compatible = "allwinner,sun20i-d1-usb-phy", .data = (ulong)&sun20i_d1_cfg },
 660         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 661         { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
 662         { }
 663 };
 664
 665 U_BOOT_DRIVER(sun4i_usb_phy) = {
 666         .name   = "sun4i_usb_phy",
 667         .id     = UCLASS_PHY,
 668         .of_match = sun4i_usb_phy_ids,
 669         .ops = &sun4i_usb_phy_ops,
 670         .probe = sun4i_usb_phy_probe,
 671         .plat_auto      = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 672         .priv_auto      = sizeof(struct sun4i_usb_phy_data),
 673 };