drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <dm/device.h>
  16 #include <generic-phy.h>
  17 #include <phy-sun4i-usb.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/cpu.h>
  22
  23 #define REG_ISCR                        0x00
  24 #define REG_PHYCTL_A10                  0x04
  25 #define REG_PHYBIST                     0x08
  26 #define REG_PHYTUNE                     0x0c
  27 #define REG_PHYCTL_A33                  0x10
  28 #define REG_PHY_OTGCTL                  0x20
  29 #define REG_PMU_UNK1                    0x10
  30
  31 /* Common Control Bits for Both PHYs */
  32 #define PHY_PLL_BW                      0x03
  33 #define PHY_RES45_CAL_EN                0x0c
  34
  35 /* Private Control Bits for Each PHY */
  36 #define PHY_TX_AMPLITUDE_TUNE           0x20
  37 #define PHY_TX_SLEWRATE_TUNE            0x22
  38 #define PHY_DISCON_TH_SEL               0x2a
  39
  40 #define PHYCTL_DATA                     BIT(7)
  41 #define OTGCTL_ROUTE_MUSB               BIT(0)
  42
  43 #define PHY_TX_RATE                     BIT(4)
  44 #define PHY_TX_MAGNITUDE                BIT(2)
  45 #define PHY_TX_AMPLITUDE_LEN            5
  46
  47 #define PHY_RES45_CAL_DATA              BIT(0)
  48 #define PHY_RES45_CAL_LEN               1
  49 #define PHY_DISCON_TH_LEN               2
  50
  51 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  52 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  53 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  54 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  55
  56 /* A83T specific control bits for PHY0 */
  57 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  58 #define PHY_CTL_SIDDQ                   BIT(3)
  59
  60 /* A83T specific control bits for PHY2 HSIC */
  61 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  62 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  63 #define SUNXI_HSIC                      BIT(1)
  64
  65 #define MAX_PHYS                        4
  66
  67 enum sun4i_usb_phy_type {
  68         sun8i_a83t_phy,
  69         sun8i_h3_phy,
  70         sun8i_v3s_phy,
  71         sun50i_a64_phy,
  72 };
  73
  74 struct sun4i_usb_phy_cfg {
  75         int num_phys;
  76         enum sun4i_usb_phy_type type;
  77         u32 disc_thresh;
  78         u8 phyctl_offset;
  79         bool enable_pmu_unk1;
  80         bool phy0_dual_route;
  81 };
  82
  83 struct sun4i_usb_phy_info {
  84         const char *gpio_vbus;
  85         const char *gpio_vbus_det;
  86         const char *gpio_id_det;
  87         int rst_mask;
  88 } phy_info[] = {
  89         {
  90                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
  91                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
  92                 .gpio_id_det = CONFIG_USB0_ID_DET,
  93                 .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
  94         },
  95         {
  96                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
  97                 .gpio_vbus_det = NULL,
  98                 .gpio_id_det = NULL,
  99                 .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 100         },
 101         {
 102                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 103                 .gpio_vbus_det = NULL,
 104                 .gpio_id_det = NULL,
 105 #ifdef CONFIG_MACH_SUN8I_A83T
 106                 .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
 107                              CCM_USB_CTRL_12M_CLK),
 108 #else
 109                 .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
 110 #endif
 111         },
 112         {
 113                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 114                 .gpio_vbus_det = NULL,
 115                 .gpio_id_det = NULL,
 116 #ifdef CONFIG_MACH_SUN6I
 117                 .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
 118 #endif
 119         },
 120 };
 121
 122 struct sun4i_usb_phy_plat {
 123         void __iomem *pmu;
 124         int power_on_count;
 125         int gpio_vbus;
 126         int gpio_vbus_det;
 127         int gpio_id_det;
 128         int rst_mask;
 129         int id;
 130 };
 131
 132 struct sun4i_usb_phy_data {
 133         void __iomem *base;
 134         struct sunxi_ccm_reg *ccm;
 135         const struct sun4i_usb_phy_cfg *cfg;
 136         struct sun4i_usb_phy_plat *usb_phy;
 137 };
 138
 139 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 140
 141 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 142 {
 143         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 144         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 145         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 146         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 147         int i;
 148
 149         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 150                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 151                 writel(0, phyctl);
 152         }
 153
 154         for (i = 0; i < len; i++) {
 155                 temp = readl(phyctl);
 156
 157                 /* clear the address portion */
 158                 temp &= ~(0xff << 8);
 159
 160                 /* set the address */
 161                 temp |= ((addr + i) << 8);
 162                 writel(temp, phyctl);
 163
 164                 /* set the data bit and clear usbc bit*/
 165                 temp = readb(phyctl);
 166                 if (data & 0x1)
 167                         temp |= PHYCTL_DATA;
 168                 else
 169                         temp &= ~PHYCTL_DATA;
 170                 temp &= ~usbc_bit;
 171                 writeb(temp, phyctl);
 172
 173                 /* pulse usbc_bit */
 174                 temp = readb(phyctl);
 175                 temp |= usbc_bit;
 176                 writeb(temp, phyctl);
 177
 178                 temp = readb(phyctl);
 179                 temp &= ~usbc_bit;
 180                 writeb(temp, phyctl);
 181
 182                 data >>= 1;
 183         }
 184 }
 185
 186 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 187 {
 188         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 189         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 190         u32 bits, reg_value;
 191
 192         if (!usb_phy->pmu)
 193                 return;
 194
 195         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 196                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 197
 198         /* A83T USB2 is HSIC */
 199         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 200                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 201                         SUNXI_HSIC;
 202
 203         reg_value = readl(usb_phy->pmu);
 204
 205         if (enable)
 206                 reg_value |= bits;
 207         else
 208                 reg_value &= ~bits;
 209
 210         writel(reg_value, usb_phy->pmu);
 211 }
 212
 213 static int sun4i_usb_phy_power_on(struct phy *phy)
 214 {
 215         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 216         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 217
 218         if (initial_usb_scan_delay) {
 219                 mdelay(initial_usb_scan_delay);
 220                 initial_usb_scan_delay = 0;
 221         }
 222
 223         usb_phy->power_on_count++;
 224         if (usb_phy->power_on_count != 1)
 225                 return 0;
 226
 227         if (usb_phy->gpio_vbus >= 0)
 228                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 229
 230         return 0;
 231 }
 232
 233 static int sun4i_usb_phy_power_off(struct phy *phy)
 234 {
 235         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 236         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 237
 238         usb_phy->power_on_count--;
 239         if (usb_phy->power_on_count != 0)
 240                 return 0;
 241
 242         if (usb_phy->gpio_vbus >= 0)
 243                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 244
 245         return 0;
 246 }
 247
 248 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 249 {
 250         u32 regval;
 251
 252         regval = readl(data->base + REG_PHY_OTGCTL);
 253         if (!id_det) {
 254                 /* Host mode. Route phy0 to EHCI/OHCI */
 255                 regval &= ~OTGCTL_ROUTE_MUSB;
 256         } else {
 257                 /* Peripheral mode. Route phy0 to MUSB */
 258                 regval |= OTGCTL_ROUTE_MUSB;
 259         }
 260         writel(regval, data->base + REG_PHY_OTGCTL);
 261 }
 262
 263 static int sun4i_usb_phy_init(struct phy *phy)
 264 {
 265         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 266         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 267         u32 val;
 268
 269         setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 270
 271         if (data->cfg->type == sun8i_a83t_phy) {
 272                 if (phy->id == 0) {
 273                         val = readl(data->base + data->cfg->phyctl_offset);
 274                         val |= PHY_CTL_VBUSVLDEXT;
 275                         val &= ~PHY_CTL_SIDDQ;
 276                         writel(val, data->base + data->cfg->phyctl_offset);
 277                 }
 278         } else {
 279                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 280                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 281                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 282                 }
 283
 284                 if (usb_phy->id == 0)
 285                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 286                                             PHY_RES45_CAL_DATA,
 287                                             PHY_RES45_CAL_LEN);
 288
 289                 /* Adjust PHY's magnitude and rate */
 290                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 291                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 292                                     PHY_TX_AMPLITUDE_LEN);
 293
 294                 /* Disconnect threshold adjustment */
 295                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 296                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 297         }
 298
 299         if (usb_phy->id != 0)
 300                 sun4i_usb_phy_passby(phy, true);
 301
 302         sun4i_usb_phy0_reroute(data, true);
 303
 304         return 0;
 305 }
 306
 307 static int sun4i_usb_phy_exit(struct phy *phy)
 308 {
 309         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 310         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 311
 312         if (phy->id == 0) {
 313                 if (data->cfg->type == sun8i_a83t_phy) {
 314                         void __iomem *phyctl = data->base +
 315                                 data->cfg->phyctl_offset;
 316
 317                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 318                 }
 319         }
 320
 321         sun4i_usb_phy_passby(phy, false);
 322
 323         clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 324
 325         return 0;
 326 }
 327
 328 static int sun4i_usb_phy_xlate(struct phy *phy,
 329                                struct ofnode_phandle_args *args)
 330 {
 331         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 332
 333         if (args->args_count >= data->cfg->num_phys)
 334                 return -EINVAL;
 335
 336         if (args->args_count)
 337                 phy->id = args->args[0];
 338         else
 339                 phy->id = 0;
 340
 341         debug("%s: phy_id = %ld\n", __func__, phy->id);
 342         return 0;
 343 }
 344
 345 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 346 {
 347         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 348         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 349         int err, retries = 3;
 350
 351         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 352
 353         if (usb_phy->gpio_vbus_det < 0)
 354                 return usb_phy->gpio_vbus_det;
 355
 356         err = gpio_get_value(usb_phy->gpio_vbus_det);
 357         /*
 358          * Vbus may have been provided by the board and just been turned of
 359          * some milliseconds ago on reset, what we're measuring then is a
 360          * residual charge on Vbus, sleep a bit and try again.
 361          */
 362         while (err > 0 && retries--) {
 363                 mdelay(100);
 364                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 365         }
 366
 367         return err;
 368 }
 369
 370 int sun4i_usb_phy_id_detect(struct phy *phy)
 371 {
 372         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 373         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 374
 375         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 376
 377         if (usb_phy->gpio_id_det < 0)
 378                 return usb_phy->gpio_id_det;
 379
 380         return gpio_get_value(usb_phy->gpio_id_det);
 381 }
 382
 383 static struct phy_ops sun4i_usb_phy_ops = {
 384         .of_xlate = sun4i_usb_phy_xlate,
 385         .init = sun4i_usb_phy_init,
 386         .power_on = sun4i_usb_phy_power_on,
 387         .power_off = sun4i_usb_phy_power_off,
 388         .exit = sun4i_usb_phy_exit,
 389 };
 390
 391 static int sun4i_usb_phy_probe(struct udevice *dev)
 392 {
 393         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 394         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 395         int i, ret;
 396
 397         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 398         if (!data->cfg)
 399                 return -EINVAL;
 400
 401         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 402         if (IS_ERR(data->base))
 403                 return PTR_ERR(data->base);
 404
 405         data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 406         if (IS_ERR(data->ccm))
 407                 return PTR_ERR(data->ccm);
 408
 409         data->usb_phy = plat;
 410         for (i = 0; i < data->cfg->num_phys; i++) {
 411                 struct sun4i_usb_phy_plat *phy = &plat[i];
 412                 struct sun4i_usb_phy_info *info = &phy_info[i];
 413                 char name[16];
 414
 415                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 416                 if (phy->gpio_vbus >= 0) {
 417                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 418                         if (ret)
 419                                 return ret;
 420                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 421                         if (ret)
 422                                 return ret;
 423                 }
 424
 425                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 426                 if (phy->gpio_vbus_det >= 0) {
 427                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 428                         if (ret)
 429                                 return ret;
 430                         ret = gpio_direction_input(phy->gpio_vbus_det);
 431                         if (ret)
 432                                 return ret;
 433                 }
 434
 435                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 436                 if (phy->gpio_id_det >= 0) {
 437                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 438                         if (ret)
 439                                 return ret;
 440                         ret = gpio_direction_input(phy->gpio_id_det);
 441                         if (ret)
 442                                 return ret;
 443                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 444                 }
 445
 446                 if (i || data->cfg->phy0_dual_route) {
 447                         snprintf(name, sizeof(name), "pmu%d", i);
 448                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 449                         if (IS_ERR(phy->pmu))
 450                                 return PTR_ERR(phy->pmu);
 451                 }
 452
 453                 phy->id = i;
 454                 phy->rst_mask = info->rst_mask;
 455         };
 456
 457         setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 458
 459         debug("Allwinner Sun4I USB PHY driver loaded\n");
 460         return 0;
 461 }
 462
 463 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 464         .num_phys = 3,
 465         .type = sun8i_a83t_phy,
 466         .phyctl_offset = REG_PHYCTL_A33,
 467 };
 468
 469 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 470         .num_phys = 4,
 471         .type = sun8i_h3_phy,
 472         .disc_thresh = 3,
 473         .phyctl_offset = REG_PHYCTL_A33,
 474         .enable_pmu_unk1 = true,
 475         .phy0_dual_route = true,
 476 };
 477
 478 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 479         .num_phys = 1,
 480         .type = sun8i_v3s_phy,
 481         .disc_thresh = 3,
 482         .phyctl_offset = REG_PHYCTL_A33,
 483         .enable_pmu_unk1 = true,
 484         .phy0_dual_route = true,
 485 };
 486
 487 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 488         .num_phys = 2,
 489         .type = sun50i_a64_phy,
 490         .disc_thresh = 3,
 491         .phyctl_offset = REG_PHYCTL_A33,
 492         .enable_pmu_unk1 = true,
 493         .phy0_dual_route = true,
 494 };
 495
 496 static const struct udevice_id sun4i_usb_phy_ids[] = {
 497         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 498         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 499         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 500         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 501         { }
 502 };
 503
 504 U_BOOT_DRIVER(sun4i_usb_phy) = {
 505         .name   = "sun4i_usb_phy",
 506         .id     = UCLASS_PHY,
 507         .of_match = sun4i_usb_phy_ids,
 508         .ops = &sun4i_usb_phy_ops,
 509         .probe = sun4i_usb_phy_probe,
 510         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 511         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 512 };