drivers/perf/xgene_pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * APM X-Gene SoC PMU (Performance Monitor Unit)
   4  *
   5  * Copyright (c) 2016, Applied Micro Circuits Corporation
   6  * Author: Hoan Tran <hotran@apm.com>
   7  *         Tai Nguyen <ttnguyen@apm.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/clk.h>
  12 #include <linux/cpuhotplug.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_fdt.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/perf_event.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26
  27 #define CSW_CSWCR                       0x0000
  28 #define  CSW_CSWCR_DUALMCB_MASK         BIT(0)
  29 #define  CSW_CSWCR_MCB0_ROUTING(x)      (((x) & 0x0C) >> 2)
  30 #define  CSW_CSWCR_MCB1_ROUTING(x)      (((x) & 0x30) >> 4)
  31 #define MCBADDRMR                       0x0000
  32 #define  MCBADDRMR_DUALMCU_MODE_MASK    BIT(2)
  33
  34 #define PCPPMU_INTSTATUS_REG    0x000
  35 #define PCPPMU_INTMASK_REG      0x004
  36 #define  PCPPMU_INTMASK         0x0000000F
  37 #define  PCPPMU_INTENMASK       0xFFFFFFFF
  38 #define  PCPPMU_INTCLRMASK      0xFFFFFFF0
  39 #define  PCPPMU_INT_MCU         BIT(0)
  40 #define  PCPPMU_INT_MCB         BIT(1)
  41 #define  PCPPMU_INT_L3C         BIT(2)
  42 #define  PCPPMU_INT_IOB         BIT(3)
  43
  44 #define  PCPPMU_V3_INTMASK      0x00FF33FF
  45 #define  PCPPMU_V3_INTENMASK    0xFFFFFFFF
  46 #define  PCPPMU_V3_INTCLRMASK   0xFF00CC00
  47 #define  PCPPMU_V3_INT_MCU      0x000000FF
  48 #define  PCPPMU_V3_INT_MCB      0x00000300
  49 #define  PCPPMU_V3_INT_L3C      0x00FF0000
  50 #define  PCPPMU_V3_INT_IOB      0x00003000
  51
  52 #define PMU_MAX_COUNTERS        4
  53 #define PMU_CNT_MAX_PERIOD      0xFFFFFFFFULL
  54 #define PMU_V3_CNT_MAX_PERIOD   0xFFFFFFFFFFFFFFFFULL
  55 #define PMU_OVERFLOW_MASK       0xF
  56 #define PMU_PMCR_E              BIT(0)
  57 #define PMU_PMCR_P              BIT(1)
  58
  59 #define PMU_PMEVCNTR0           0x000
  60 #define PMU_PMEVCNTR1           0x004
  61 #define PMU_PMEVCNTR2           0x008
  62 #define PMU_PMEVCNTR3           0x00C
  63 #define PMU_PMEVTYPER0          0x400
  64 #define PMU_PMEVTYPER1          0x404
  65 #define PMU_PMEVTYPER2          0x408
  66 #define PMU_PMEVTYPER3          0x40C
  67 #define PMU_PMAMR0              0xA00
  68 #define PMU_PMAMR1              0xA04
  69 #define PMU_PMCNTENSET          0xC00
  70 #define PMU_PMCNTENCLR          0xC20
  71 #define PMU_PMINTENSET          0xC40
  72 #define PMU_PMINTENCLR          0xC60
  73 #define PMU_PMOVSR              0xC80
  74 #define PMU_PMCR                0xE04
  75
  76 /* PMU registers for V3 */
  77 #define PMU_PMOVSCLR            0xC80
  78 #define PMU_PMOVSSET            0xCC0
  79
  80 #define to_pmu_dev(p)     container_of(p, struct xgene_pmu_dev, pmu)
  81 #define GET_CNTR(ev)      (ev->hw.idx)
  82 #define GET_EVENTID(ev)   (ev->hw.config & 0xFFULL)
  83 #define GET_AGENTID(ev)   (ev->hw.config_base & 0xFFFFFFFFUL)
  84 #define GET_AGENT1ID(ev)  ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
  85
  86 struct hw_pmu_info {
  87         u32 type;
  88         u32 enable_mask;
  89         void __iomem *csr;
  90 };
  91
  92 struct xgene_pmu_dev {
  93         struct hw_pmu_info *inf;
  94         struct xgene_pmu *parent;
  95         struct pmu pmu;
  96         u8 max_counters;
  97         DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS);
  98         u64 max_period;
  99         const struct attribute_group **attr_groups;
 100         struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];
 101 };
 102
 103 struct xgene_pmu_ops {
 104         void (*mask_int)(struct xgene_pmu *pmu);
 105         void (*unmask_int)(struct xgene_pmu *pmu);
 106         u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
 107         void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
 108         void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
 109         void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
 110         void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
 111         void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
 112         void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
 113         void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
 114         void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
 115         void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
 116         void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
 117         void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
 118 };
 119
 120 struct xgene_pmu {
 121         struct device *dev;
 122         struct hlist_node node;
 123         int version;
 124         void __iomem *pcppmu_csr;
 125         u32 mcb_active_mask;
 126         u32 mc_active_mask;
 127         u32 l3c_active_mask;
 128         cpumask_t cpu;
 129         int irq;
 130         raw_spinlock_t lock;
 131         const struct xgene_pmu_ops *ops;
 132         struct list_head l3cpmus;
 133         struct list_head iobpmus;
 134         struct list_head mcbpmus;
 135         struct list_head mcpmus;
 136 };
 137
 138 struct xgene_pmu_dev_ctx {
 139         char *name;
 140         struct list_head next;
 141         struct xgene_pmu_dev *pmu_dev;
 142         struct hw_pmu_info inf;
 143 };
 144
 145 struct xgene_pmu_data {
 146         int id;
 147         u32 data;
 148 };
 149
 150 enum xgene_pmu_version {
 151         PCP_PMU_V1 = 1,
 152         PCP_PMU_V2,
 153         PCP_PMU_V3,
 154 };
 155
 156 enum xgene_pmu_dev_type {
 157         PMU_TYPE_L3C = 0,
 158         PMU_TYPE_IOB,
 159         PMU_TYPE_IOB_SLOW,
 160         PMU_TYPE_MCB,
 161         PMU_TYPE_MC,
 162 };
 163
 164 /*
 165  * sysfs format attributes
 166  */
 167 static ssize_t xgene_pmu_format_show(struct device *dev,
 168                                      struct device_attribute *attr, char *buf)
 169 {
 170         struct dev_ext_attribute *eattr;
 171
 172         eattr = container_of(attr, struct dev_ext_attribute, attr);
 173         return sysfs_emit(buf, "%s\n", (char *) eattr->var);
 174 }
 175
 176 #define XGENE_PMU_FORMAT_ATTR(_name, _config)           \
 177         (&((struct dev_ext_attribute[]) {               \
 178                 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \
 179                   .var = (void *) _config, }            \
 180         })[0].attr.attr)
 181
 182 static struct attribute *l3c_pmu_format_attrs[] = {
 183         XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
 184         XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
 185         NULL,
 186 };
 187
 188 static struct attribute *iob_pmu_format_attrs[] = {
 189         XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
 190         XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
 191         NULL,
 192 };
 193
 194 static struct attribute *mcb_pmu_format_attrs[] = {
 195         XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
 196         XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
 197         NULL,
 198 };
 199
 200 static struct attribute *mc_pmu_format_attrs[] = {
 201         XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
 202         NULL,
 203 };
 204
 205 static const struct attribute_group l3c_pmu_format_attr_group = {
 206         .name = "format",
 207         .attrs = l3c_pmu_format_attrs,
 208 };
 209
 210 static const struct attribute_group iob_pmu_format_attr_group = {
 211         .name = "format",
 212         .attrs = iob_pmu_format_attrs,
 213 };
 214
 215 static const struct attribute_group mcb_pmu_format_attr_group = {
 216         .name = "format",
 217         .attrs = mcb_pmu_format_attrs,
 218 };
 219
 220 static const struct attribute_group mc_pmu_format_attr_group = {
 221         .name = "format",
 222         .attrs = mc_pmu_format_attrs,
 223 };
 224
 225 static struct attribute *l3c_pmu_v3_format_attrs[] = {
 226         XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
 227         NULL,
 228 };
 229
 230 static struct attribute *iob_pmu_v3_format_attrs[] = {
 231         XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
 232         NULL,
 233 };
 234
 235 static struct attribute *iob_slow_pmu_v3_format_attrs[] = {
 236         XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
 237         NULL,
 238 };
 239
 240 static struct attribute *mcb_pmu_v3_format_attrs[] = {
 241         XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
 242         NULL,
 243 };
 244
 245 static struct attribute *mc_pmu_v3_format_attrs[] = {
 246         XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
 247         NULL,
 248 };
 249
 250 static const struct attribute_group l3c_pmu_v3_format_attr_group = {
 251         .name = "format",
 252         .attrs = l3c_pmu_v3_format_attrs,
 253 };
 254
 255 static const struct attribute_group iob_pmu_v3_format_attr_group = {
 256         .name = "format",
 257         .attrs = iob_pmu_v3_format_attrs,
 258 };
 259
 260 static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {
 261         .name = "format",
 262         .attrs = iob_slow_pmu_v3_format_attrs,
 263 };
 264
 265 static const struct attribute_group mcb_pmu_v3_format_attr_group = {
 266         .name = "format",
 267         .attrs = mcb_pmu_v3_format_attrs,
 268 };
 269
 270 static const struct attribute_group mc_pmu_v3_format_attr_group = {
 271         .name = "format",
 272         .attrs = mc_pmu_v3_format_attrs,
 273 };
 274
 275 /*
 276  * sysfs event attributes
 277  */
 278 static ssize_t xgene_pmu_event_show(struct device *dev,
 279                                     struct device_attribute *attr, char *buf)
 280 {
 281         struct perf_pmu_events_attr *pmu_attr =
 282                 container_of(attr, struct perf_pmu_events_attr, attr);
 283
 284         return sysfs_emit(buf, "config=0x%llx\n", pmu_attr->id);
 285 }
 286
 287 #define XGENE_PMU_EVENT_ATTR(_name, _config)            \
 288         PMU_EVENT_ATTR_ID(_name, xgene_pmu_event_show, _config)
 289
 290 static struct attribute *l3c_pmu_events_attrs[] = {
 291         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 292         XGENE_PMU_EVENT_ATTR(cycle-count-div-64,                0x01),
 293         XGENE_PMU_EVENT_ATTR(read-hit,                          0x02),
 294         XGENE_PMU_EVENT_ATTR(read-miss,                         0x03),
 295         XGENE_PMU_EVENT_ATTR(write-need-replacement,            0x06),
 296         XGENE_PMU_EVENT_ATTR(write-not-need-replacement,        0x07),
 297         XGENE_PMU_EVENT_ATTR(tq-full,                           0x08),
 298         XGENE_PMU_EVENT_ATTR(ackq-full,                         0x09),
 299         XGENE_PMU_EVENT_ATTR(wdb-full,                          0x0a),
 300         XGENE_PMU_EVENT_ATTR(bank-fifo-full,                    0x0b),
 301         XGENE_PMU_EVENT_ATTR(odb-full,                          0x0c),
 302         XGENE_PMU_EVENT_ATTR(wbq-full,                          0x0d),
 303         XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue,          0x0e),
 304         XGENE_PMU_EVENT_ATTR(bank-fifo-issue,                   0x0f),
 305         NULL,
 306 };
 307
 308 static struct attribute *iob_pmu_events_attrs[] = {
 309         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 310         XGENE_PMU_EVENT_ATTR(cycle-count-div-64,                0x01),
 311         XGENE_PMU_EVENT_ATTR(axi0-read,                         0x02),
 312         XGENE_PMU_EVENT_ATTR(axi0-read-partial,                 0x03),
 313         XGENE_PMU_EVENT_ATTR(axi1-read,                         0x04),
 314         XGENE_PMU_EVENT_ATTR(axi1-read-partial,                 0x05),
 315         XGENE_PMU_EVENT_ATTR(csw-read-block,                    0x06),
 316         XGENE_PMU_EVENT_ATTR(csw-read-partial,                  0x07),
 317         XGENE_PMU_EVENT_ATTR(axi0-write,                        0x10),
 318         XGENE_PMU_EVENT_ATTR(axi0-write-partial,                0x11),
 319         XGENE_PMU_EVENT_ATTR(axi1-write,                        0x13),
 320         XGENE_PMU_EVENT_ATTR(axi1-write-partial,                0x14),
 321         XGENE_PMU_EVENT_ATTR(csw-inbound-dirty,                 0x16),
 322         NULL,
 323 };
 324
 325 static struct attribute *mcb_pmu_events_attrs[] = {
 326         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 327         XGENE_PMU_EVENT_ATTR(cycle-count-div-64,                0x01),
 328         XGENE_PMU_EVENT_ATTR(csw-read,                          0x02),
 329         XGENE_PMU_EVENT_ATTR(csw-write-request,                 0x03),
 330         XGENE_PMU_EVENT_ATTR(mcb-csw-stall,                     0x04),
 331         XGENE_PMU_EVENT_ATTR(cancel-read-gack,                  0x05),
 332         NULL,
 333 };
 334
 335 static struct attribute *mc_pmu_events_attrs[] = {
 336         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 337         XGENE_PMU_EVENT_ATTR(cycle-count-div-64,                0x01),
 338         XGENE_PMU_EVENT_ATTR(act-cmd-sent,                      0x02),
 339         XGENE_PMU_EVENT_ATTR(pre-cmd-sent,                      0x03),
 340         XGENE_PMU_EVENT_ATTR(rd-cmd-sent,                       0x04),
 341         XGENE_PMU_EVENT_ATTR(rda-cmd-sent,                      0x05),
 342         XGENE_PMU_EVENT_ATTR(wr-cmd-sent,                       0x06),
 343         XGENE_PMU_EVENT_ATTR(wra-cmd-sent,                      0x07),
 344         XGENE_PMU_EVENT_ATTR(pde-cmd-sent,                      0x08),
 345         XGENE_PMU_EVENT_ATTR(sre-cmd-sent,                      0x09),
 346         XGENE_PMU_EVENT_ATTR(prea-cmd-sent,                     0x0a),
 347         XGENE_PMU_EVENT_ATTR(ref-cmd-sent,                      0x0b),
 348         XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent,                   0x0c),
 349         XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent,                   0x0d),
 350         XGENE_PMU_EVENT_ATTR(in-rd-collision,                   0x0e),
 351         XGENE_PMU_EVENT_ATTR(in-wr-collision,                   0x0f),
 352         XGENE_PMU_EVENT_ATTR(collision-queue-not-empty,         0x10),
 353         XGENE_PMU_EVENT_ATTR(collision-queue-full,              0x11),
 354         XGENE_PMU_EVENT_ATTR(mcu-request,                       0x12),
 355         XGENE_PMU_EVENT_ATTR(mcu-rd-request,                    0x13),
 356         XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request,                 0x14),
 357         XGENE_PMU_EVENT_ATTR(mcu-wr-request,                    0x15),
 358         XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all,                0x16),
 359         XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel,             0x17),
 360         XGENE_PMU_EVENT_ATTR(mcu-rd-response,                   0x18),
 361         XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all,    0x19),
 362         XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
 363         XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all,                0x1b),
 364         XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel,             0x1c),
 365         NULL,
 366 };
 367
 368 static const struct attribute_group l3c_pmu_events_attr_group = {
 369         .name = "events",
 370         .attrs = l3c_pmu_events_attrs,
 371 };
 372
 373 static const struct attribute_group iob_pmu_events_attr_group = {
 374         .name = "events",
 375         .attrs = iob_pmu_events_attrs,
 376 };
 377
 378 static const struct attribute_group mcb_pmu_events_attr_group = {
 379         .name = "events",
 380         .attrs = mcb_pmu_events_attrs,
 381 };
 382
 383 static const struct attribute_group mc_pmu_events_attr_group = {
 384         .name = "events",
 385         .attrs = mc_pmu_events_attrs,
 386 };
 387
 388 static struct attribute *l3c_pmu_v3_events_attrs[] = {
 389         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 390         XGENE_PMU_EVENT_ATTR(read-hit,                          0x01),
 391         XGENE_PMU_EVENT_ATTR(read-miss,                         0x02),
 392         XGENE_PMU_EVENT_ATTR(index-flush-eviction,              0x03),
 393         XGENE_PMU_EVENT_ATTR(write-caused-replacement,          0x04),
 394         XGENE_PMU_EVENT_ATTR(write-not-caused-replacement,      0x05),
 395         XGENE_PMU_EVENT_ATTR(clean-eviction,                    0x06),
 396         XGENE_PMU_EVENT_ATTR(dirty-eviction,                    0x07),
 397         XGENE_PMU_EVENT_ATTR(read,                              0x08),
 398         XGENE_PMU_EVENT_ATTR(write,                             0x09),
 399         XGENE_PMU_EVENT_ATTR(request,                           0x0a),
 400         XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall,      0x0b),
 401         XGENE_PMU_EVENT_ATTR(tq-full,                           0x0c),
 402         XGENE_PMU_EVENT_ATTR(ackq-full,                         0x0d),
 403         XGENE_PMU_EVENT_ATTR(wdb-full,                          0x0e),
 404         XGENE_PMU_EVENT_ATTR(odb-full,                          0x10),
 405         XGENE_PMU_EVENT_ATTR(wbq-full,                          0x11),
 406         XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall,        0x12),
 407         XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall,       0x13),
 408         XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall,      0x14),
 409         XGENE_PMU_EVENT_ATTR(total-insertion,                   0x15),
 410         XGENE_PMU_EVENT_ATTR(sip-insertions-r-set,              0x16),
 411         XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear,            0x17),
 412         XGENE_PMU_EVENT_ATTR(dip-insertions-r-set,              0x18),
 413         XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear,            0x19),
 414         XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set,        0x1a),
 415         XGENE_PMU_EVENT_ATTR(egression,                         0x1b),
 416         XGENE_PMU_EVENT_ATTR(replacement,                       0x1c),
 417         XGENE_PMU_EVENT_ATTR(old-replacement,                   0x1d),
 418         XGENE_PMU_EVENT_ATTR(young-replacement,                 0x1e),
 419         XGENE_PMU_EVENT_ATTR(r-set-replacement,                 0x1f),
 420         XGENE_PMU_EVENT_ATTR(r-clear-replacement,               0x20),
 421         XGENE_PMU_EVENT_ATTR(old-r-replacement,                 0x21),
 422         XGENE_PMU_EVENT_ATTR(old-nr-replacement,                0x22),
 423         XGENE_PMU_EVENT_ATTR(young-r-replacement,               0x23),
 424         XGENE_PMU_EVENT_ATTR(young-nr-replacement,              0x24),
 425         XGENE_PMU_EVENT_ATTR(bloomfilter-clearing,              0x25),
 426         XGENE_PMU_EVENT_ATTR(generation-flip,                   0x26),
 427         XGENE_PMU_EVENT_ATTR(vcc-droop-detected,                0x27),
 428         NULL,
 429 };
 430
 431 static struct attribute *iob_fast_pmu_v3_events_attrs[] = {
 432         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 433         XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all,              0x01),
 434         XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd,               0x02),
 435         XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr,               0x03),
 436         XGENE_PMU_EVENT_ATTR(pa-all-cp-req,                     0x04),
 437         XGENE_PMU_EVENT_ATTR(pa-cp-blk-req,                     0x05),
 438         XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req,                     0x06),
 439         XGENE_PMU_EVENT_ATTR(pa-cp-rd-req,                      0x07),
 440         XGENE_PMU_EVENT_ATTR(pa-cp-wr-req,                      0x08),
 441         XGENE_PMU_EVENT_ATTR(ba-all-req,                        0x09),
 442         XGENE_PMU_EVENT_ATTR(ba-rd-req,                         0x0a),
 443         XGENE_PMU_EVENT_ATTR(ba-wr-req,                         0x0b),
 444         XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued,           0x10),
 445         XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued,        0x11),
 446         XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
 447         XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
 448         XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable,   0x14),
 449         XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
 450         XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req,                     0x16),
 451         XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req,                     0x17),
 452         XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data,             0x18),
 453         XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS,        0x1b),
 454         XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence,             0x1c),
 455         XGENE_PMU_EVENT_ATTR(pa-barrier-cycles,                 0x1d),
 456         XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops,                0x20),
 457         XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop,                0x21),
 458         XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit,            0x22),
 459         XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop,             0x23),
 460         XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit,         0x24),
 461         XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop,            0x25),
 462         XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit,        0x26),
 463         XGENE_PMU_EVENT_ATTR(pa-req-buffer-full,                0x28),
 464         XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full,      0x29),
 465         XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
 466         XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full,     0x2b),
 467         XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
 468         XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full,     0x2d),
 469         XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
 470         XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure,    0x2f),
 471         NULL,
 472 };
 473
 474 static struct attribute *iob_slow_pmu_v3_events_attrs[] = {
 475         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 476         XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req,                    0x01),
 477         XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req,                    0x02),
 478         XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req,                    0x03),
 479         XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req,                    0x04),
 480         XGENE_PMU_EVENT_ATTR(ba-all-axi-req,                    0x07),
 481         XGENE_PMU_EVENT_ATTR(ba-axi-rd-req,                     0x08),
 482         XGENE_PMU_EVENT_ATTR(ba-axi-wr-req,                     0x09),
 483         XGENE_PMU_EVENT_ATTR(ba-free-list-empty,                0x10),
 484         NULL,
 485 };
 486
 487 static struct attribute *mcb_pmu_v3_events_attrs[] = {
 488         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 489         XGENE_PMU_EVENT_ATTR(req-receive,                       0x01),
 490         XGENE_PMU_EVENT_ATTR(rd-req-recv,                       0x02),
 491         XGENE_PMU_EVENT_ATTR(rd-req-recv-2,                     0x03),
 492         XGENE_PMU_EVENT_ATTR(wr-req-recv,                       0x04),
 493         XGENE_PMU_EVENT_ATTR(wr-req-recv-2,                     0x05),
 494         XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu,                0x06),
 495         XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2,              0x07),
 496         XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu,           0x08),
 497         XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2,         0x09),
 498         XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
 499         XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
 500         XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
 501         XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req,       0x0d),
 502         XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2,     0x0e),
 503         XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu,                0x0f),
 504         XGENE_PMU_EVENT_ATTR(gack-recv,                         0x10),
 505         XGENE_PMU_EVENT_ATTR(rd-gack-recv,                      0x11),
 506         XGENE_PMU_EVENT_ATTR(wr-gack-recv,                      0x12),
 507         XGENE_PMU_EVENT_ATTR(cancel-rd-gack,                    0x13),
 508         XGENE_PMU_EVENT_ATTR(cancel-wr-gack,                    0x14),
 509         XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall,                 0x15),
 510         XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked,              0x16),
 511         XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall,             0x17),
 512         XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked,               0x18),
 513         XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked,        0x19),
 514         XGENE_PMU_EVENT_ATTR(mcu-req-table-full,                0x1a),
 515         XGENE_PMU_EVENT_ATTR(mcu-stat-table-full,               0x1b),
 516         XGENE_PMU_EVENT_ATTR(mcu-wr-table-full,                 0x1c),
 517         XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp,                0x1d),
 518         XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp,               0x1e),
 519         XGENE_PMU_EVENT_ATTR(mcu-retryack-resp,                 0x1f),
 520         XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp,                0x20),
 521         XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload,             0x21),
 522         XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass,               0x22),
 523         XGENE_PMU_EVENT_ATTR(volt-droop-detect,                 0x23),
 524         NULL,
 525 };
 526
 527 static struct attribute *mc_pmu_v3_events_attrs[] = {
 528         XGENE_PMU_EVENT_ATTR(cycle-count,                       0x00),
 529         XGENE_PMU_EVENT_ATTR(act-sent,                          0x01),
 530         XGENE_PMU_EVENT_ATTR(pre-sent,                          0x02),
 531         XGENE_PMU_EVENT_ATTR(rd-sent,                           0x03),
 532         XGENE_PMU_EVENT_ATTR(rda-sent,                          0x04),
 533         XGENE_PMU_EVENT_ATTR(wr-sent,                           0x05),
 534         XGENE_PMU_EVENT_ATTR(wra-sent,                          0x06),
 535         XGENE_PMU_EVENT_ATTR(pd-entry-vld,                      0x07),
 536         XGENE_PMU_EVENT_ATTR(sref-entry-vld,                    0x08),
 537         XGENE_PMU_EVENT_ATTR(prea-sent,                         0x09),
 538         XGENE_PMU_EVENT_ATTR(ref-sent,                          0x0a),
 539         XGENE_PMU_EVENT_ATTR(rd-rda-sent,                       0x0b),
 540         XGENE_PMU_EVENT_ATTR(wr-wra-sent,                       0x0c),
 541         XGENE_PMU_EVENT_ATTR(raw-hazard,                        0x0d),
 542         XGENE_PMU_EVENT_ATTR(war-hazard,                        0x0e),
 543         XGENE_PMU_EVENT_ATTR(waw-hazard,                        0x0f),
 544         XGENE_PMU_EVENT_ATTR(rar-hazard,                        0x10),
 545         XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard,                0x11),
 546         XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld,              0x12),
 547         XGENE_PMU_EVENT_ATTR(lprd-req-vld,                      0x13),
 548         XGENE_PMU_EVENT_ATTR(hprd-req-vld,                      0x14),
 549         XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld,                 0x15),
 550         XGENE_PMU_EVENT_ATTR(wr-req-vld,                        0x16),
 551         XGENE_PMU_EVENT_ATTR(partial-wr-req-vld,                0x17),
 552         XGENE_PMU_EVENT_ATTR(rd-retry,                          0x18),
 553         XGENE_PMU_EVENT_ATTR(wr-retry,                          0x19),
 554         XGENE_PMU_EVENT_ATTR(retry-gnt,                         0x1a),
 555         XGENE_PMU_EVENT_ATTR(rank-change,                       0x1b),
 556         XGENE_PMU_EVENT_ATTR(dir-change,                        0x1c),
 557         XGENE_PMU_EVENT_ATTR(rank-dir-change,                   0x1d),
 558         XGENE_PMU_EVENT_ATTR(rank-active,                       0x1e),
 559         XGENE_PMU_EVENT_ATTR(rank-idle,                         0x1f),
 560         XGENE_PMU_EVENT_ATTR(rank-pd,                           0x20),
 561         XGENE_PMU_EVENT_ATTR(rank-sref,                         0x21),
 562         XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh,              0x22),
 563         XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh,               0x23),
 564         XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh,               0x24),
 565         XGENE_PMU_EVENT_ATTR(phy-updt-complt,                   0x25),
 566         XGENE_PMU_EVENT_ATTR(tz-fail,                           0x26),
 567         XGENE_PMU_EVENT_ATTR(dram-errc,                         0x27),
 568         XGENE_PMU_EVENT_ATTR(dram-errd,                         0x28),
 569         XGENE_PMU_EVENT_ATTR(rd-enq,                            0x29),
 570         XGENE_PMU_EVENT_ATTR(wr-enq,                            0x2a),
 571         XGENE_PMU_EVENT_ATTR(tmac-limit-reached,                0x2b),
 572         XGENE_PMU_EVENT_ATTR(tmaw-tracker-full,                 0x2c),
 573         NULL,
 574 };
 575
 576 static const struct attribute_group l3c_pmu_v3_events_attr_group = {
 577         .name = "events",
 578         .attrs = l3c_pmu_v3_events_attrs,
 579 };
 580
 581 static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {
 582         .name = "events",
 583         .attrs = iob_fast_pmu_v3_events_attrs,
 584 };
 585
 586 static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {
 587         .name = "events",
 588         .attrs = iob_slow_pmu_v3_events_attrs,
 589 };
 590
 591 static const struct attribute_group mcb_pmu_v3_events_attr_group = {
 592         .name = "events",
 593         .attrs = mcb_pmu_v3_events_attrs,
 594 };
 595
 596 static const struct attribute_group mc_pmu_v3_events_attr_group = {
 597         .name = "events",
 598         .attrs = mc_pmu_v3_events_attrs,
 599 };
 600
 601 /*
 602  * sysfs cpumask attributes
 603  */
 604 static ssize_t cpumask_show(struct device *dev,
 605                             struct device_attribute *attr, char *buf)
 606 {
 607         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
 608
 609         return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
 610 }
 611
 612 static DEVICE_ATTR_RO(cpumask);
 613
 614 static struct attribute *xgene_pmu_cpumask_attrs[] = {
 615         &dev_attr_cpumask.attr,
 616         NULL,
 617 };
 618
 619 static const struct attribute_group pmu_cpumask_attr_group = {
 620         .attrs = xgene_pmu_cpumask_attrs,
 621 };
 622
 623 /*
 624  * Per PMU device attribute groups of PMU v1 and v2
 625  */
 626 static const struct attribute_group *l3c_pmu_attr_groups[] = {
 627         &l3c_pmu_format_attr_group,
 628         &pmu_cpumask_attr_group,
 629         &l3c_pmu_events_attr_group,
 630         NULL
 631 };
 632
 633 static const struct attribute_group *iob_pmu_attr_groups[] = {
 634         &iob_pmu_format_attr_group,
 635         &pmu_cpumask_attr_group,
 636         &iob_pmu_events_attr_group,
 637         NULL
 638 };
 639
 640 static const struct attribute_group *mcb_pmu_attr_groups[] = {
 641         &mcb_pmu_format_attr_group,
 642         &pmu_cpumask_attr_group,
 643         &mcb_pmu_events_attr_group,
 644         NULL
 645 };
 646
 647 static const struct attribute_group *mc_pmu_attr_groups[] = {
 648         &mc_pmu_format_attr_group,
 649         &pmu_cpumask_attr_group,
 650         &mc_pmu_events_attr_group,
 651         NULL
 652 };
 653
 654 /*
 655  * Per PMU device attribute groups of PMU v3
 656  */
 657 static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {
 658         &l3c_pmu_v3_format_attr_group,
 659         &pmu_cpumask_attr_group,
 660         &l3c_pmu_v3_events_attr_group,
 661         NULL
 662 };
 663
 664 static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {
 665         &iob_pmu_v3_format_attr_group,
 666         &pmu_cpumask_attr_group,
 667         &iob_fast_pmu_v3_events_attr_group,
 668         NULL
 669 };
 670
 671 static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {
 672         &iob_slow_pmu_v3_format_attr_group,
 673         &pmu_cpumask_attr_group,
 674         &iob_slow_pmu_v3_events_attr_group,
 675         NULL
 676 };
 677
 678 static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {
 679         &mcb_pmu_v3_format_attr_group,
 680         &pmu_cpumask_attr_group,
 681         &mcb_pmu_v3_events_attr_group,
 682         NULL
 683 };
 684
 685 static const struct attribute_group *mc_pmu_v3_attr_groups[] = {
 686         &mc_pmu_v3_format_attr_group,
 687         &pmu_cpumask_attr_group,
 688         &mc_pmu_v3_events_attr_group,
 689         NULL
 690 };
 691
 692 static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
 693 {
 694         int cntr;
 695
 696         cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
 697                                 pmu_dev->max_counters);
 698         if (cntr == pmu_dev->max_counters)
 699                 return -ENOSPC;
 700         set_bit(cntr, pmu_dev->cntr_assign_mask);
 701
 702         return cntr;
 703 }
 704
 705 static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
 706 {
 707         clear_bit(cntr, pmu_dev->cntr_assign_mask);
 708 }
 709
 710 static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)
 711 {
 712         writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
 713 }
 714
 715 static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)
 716 {
 717         writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
 718 }
 719
 720 static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)
 721 {
 722         writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
 723 }
 724
 725 static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)
 726 {
 727         writel(PCPPMU_V3_INTCLRMASK,
 728                xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
 729 }
 730
 731 static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
 732                                            int idx)
 733 {
 734         return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
 735 }
 736
 737 static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
 738                                            int idx)
 739 {
 740         u32 lo, hi;
 741
 742         /*
 743          * v3 has 64-bit counter registers composed by 2 32-bit registers
 744          * This can be a problem if the counter increases and carries
 745          * out of bit [31] between 2 reads. The extra reads would help
 746          * to prevent this issue.
 747          */
 748         do {
 749                 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
 750                 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
 751         } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
 752
 753         return (((u64)hi << 32) | lo);
 754 }
 755
 756 static inline void
 757 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
 758 {
 759         writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
 760 }
 761
 762 static inline void
 763 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
 764 {
 765         u32 cnt_lo, cnt_hi;
 766
 767         cnt_hi = upper_32_bits(val);
 768         cnt_lo = lower_32_bits(val);
 769
 770         /* v3 has 64-bit counter registers composed by 2 32-bit registers */
 771         xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
 772         xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
 773 }
 774
 775 static inline void
 776 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
 777 {
 778         writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
 779 }
 780
 781 static inline void
 782 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
 783 {
 784         writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
 785 }
 786
 787 static inline void
 788 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
 789
 790 static inline void
 791 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
 792 {
 793         writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
 794 }
 795
 796 static inline void
 797 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
 798
 799 static inline void
 800 xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
 801 {
 802         u32 val;
 803
 804         val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
 805         val |= 1 << idx;
 806         writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
 807 }
 808
 809 static inline void
 810 xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
 811 {
 812         u32 val;
 813
 814         val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
 815         val |= 1 << idx;
 816         writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
 817 }
 818
 819 static inline void
 820 xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
 821 {
 822         u32 val;
 823
 824         val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
 825         val |= 1 << idx;
 826         writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
 827 }
 828
 829 static inline void
 830 xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
 831 {
 832         u32 val;
 833
 834         val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
 835         val |= 1 << idx;
 836         writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
 837 }
 838
 839 static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
 840 {
 841         u32 val;
 842
 843         val = readl(pmu_dev->inf->csr + PMU_PMCR);
 844         val |= PMU_PMCR_P;
 845         writel(val, pmu_dev->inf->csr + PMU_PMCR);
 846 }
 847
 848 static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
 849 {
 850         u32 val;
 851
 852         val = readl(pmu_dev->inf->csr + PMU_PMCR);
 853         val |= PMU_PMCR_E;
 854         writel(val, pmu_dev->inf->csr + PMU_PMCR);
 855 }
 856
 857 static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
 858 {
 859         u32 val;
 860
 861         val = readl(pmu_dev->inf->csr + PMU_PMCR);
 862         val &= ~PMU_PMCR_E;
 863         writel(val, pmu_dev->inf->csr + PMU_PMCR);
 864 }
 865
 866 static void xgene_perf_pmu_enable(struct pmu *pmu)
 867 {
 868         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
 869         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
 870         bool enabled = !bitmap_empty(pmu_dev->cntr_assign_mask,
 871                         pmu_dev->max_counters);
 872
 873         if (!enabled)
 874                 return;
 875
 876         xgene_pmu->ops->start_counters(pmu_dev);
 877 }
 878
 879 static void xgene_perf_pmu_disable(struct pmu *pmu)
 880 {
 881         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
 882         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
 883
 884         xgene_pmu->ops->stop_counters(pmu_dev);
 885 }
 886
 887 static int xgene_perf_event_init(struct perf_event *event)
 888 {
 889         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
 890         struct hw_perf_event *hw = &event->hw;
 891         struct perf_event *sibling;
 892
 893         /* Test the event attr type check for PMU enumeration */
 894         if (event->attr.type != event->pmu->type)
 895                 return -ENOENT;
 896
 897         /*
 898          * SOC PMU counters are shared across all cores.
 899          * Therefore, it does not support per-process mode.
 900          * Also, it does not support event sampling mode.
 901          */
 902         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
 903                 return -EINVAL;
 904
 905         if (event->cpu < 0)
 906                 return -EINVAL;
 907         /*
 908          * Many perf core operations (eg. events rotation) operate on a
 909          * single CPU context. This is obvious for CPU PMUs, where one
 910          * expects the same sets of events being observed on all CPUs,
 911          * but can lead to issues for off-core PMUs, where each
 912          * event could be theoretically assigned to a different CPU. To
 913          * mitigate this, we enforce CPU assignment to one, selected
 914          * processor (the one described in the "cpumask" attribute).
 915          */
 916         event->cpu = cpumask_first(&pmu_dev->parent->cpu);
 917
 918         hw->config = event->attr.config;
 919         /*
 920          * Each bit of the config1 field represents an agent from which the
 921          * request of the event come. The event is counted only if it's caused
 922          * by a request of an agent has the bit cleared.
 923          * By default, the event is counted for all agents.
 924          */
 925         hw->config_base = event->attr.config1;
 926
 927         /*
 928          * We must NOT create groups containing mixed PMUs, although software
 929          * events are acceptable
 930          */
 931         if (event->group_leader->pmu != event->pmu &&
 932                         !is_software_event(event->group_leader))
 933                 return -EINVAL;
 934
 935         for_each_sibling_event(sibling, event->group_leader) {
 936                 if (sibling->pmu != event->pmu &&
 937                                 !is_software_event(sibling))
 938                         return -EINVAL;
 939         }
 940
 941         return 0;
 942 }
 943
 944 static void xgene_perf_enable_event(struct perf_event *event)
 945 {
 946         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
 947         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
 948
 949         xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
 950                                       GET_EVENTID(event));
 951         xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
 952         if (pmu_dev->inf->type == PMU_TYPE_IOB)
 953                 xgene_pmu->ops->write_agent1msk(pmu_dev,
 954                                                 ~((u32)GET_AGENT1ID(event)));
 955
 956         xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
 957         xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
 958 }
 959
 960 static void xgene_perf_disable_event(struct perf_event *event)
 961 {
 962         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
 963         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
 964
 965         xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
 966         xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
 967 }
 968
 969 static void xgene_perf_event_set_period(struct perf_event *event)
 970 {
 971         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
 972         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
 973         struct hw_perf_event *hw = &event->hw;
 974         /*
 975          * For 32 bit counter, it has a period of 2^32. To account for the
 976          * possibility of extreme interrupt latency we program for a period of
 977          * half that. Hopefully, we can handle the interrupt before another 2^31
 978          * events occur and the counter overtakes its previous value.
 979          * For 64 bit counter, we don't expect it overflow.
 980          */
 981         u64 val = 1ULL << 31;
 982
 983         local64_set(&hw->prev_count, val);
 984         xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
 985 }
 986
 987 static void xgene_perf_event_update(struct perf_event *event)
 988 {
 989         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
 990         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
 991         struct hw_perf_event *hw = &event->hw;
 992         u64 delta, prev_raw_count, new_raw_count;
 993
 994 again:
 995         prev_raw_count = local64_read(&hw->prev_count);
 996         new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
 997
 998         if (local64_cmpxchg(&hw->prev_count, prev_raw_count,
 999                             new_raw_count) != prev_raw_count)
1000                 goto again;
1001
1002         delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
1003
1004         local64_add(delta, &event->count);
1005 }
1006
1007 static void xgene_perf_read(struct perf_event *event)
1008 {
1009         xgene_perf_event_update(event);
1010 }
1011
1012 static void xgene_perf_start(struct perf_event *event, int flags)
1013 {
1014         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1015         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1016         struct hw_perf_event *hw = &event->hw;
1017
1018         if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))
1019                 return;
1020
1021         WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
1022         hw->state = 0;
1023
1024         xgene_perf_event_set_period(event);
1025
1026         if (flags & PERF_EF_RELOAD) {
1027                 u64 prev_raw_count =  local64_read(&hw->prev_count);
1028
1029                 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1030                                               prev_raw_count);
1031         }
1032
1033         xgene_perf_enable_event(event);
1034         perf_event_update_userpage(event);
1035 }
1036
1037 static void xgene_perf_stop(struct perf_event *event, int flags)
1038 {
1039         struct hw_perf_event *hw = &event->hw;
1040
1041         if (hw->state & PERF_HES_UPTODATE)
1042                 return;
1043
1044         xgene_perf_disable_event(event);
1045         WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);
1046         hw->state |= PERF_HES_STOPPED;
1047
1048         if (hw->state & PERF_HES_UPTODATE)
1049                 return;
1050
1051         xgene_perf_read(event);
1052         hw->state |= PERF_HES_UPTODATE;
1053 }
1054
1055 static int xgene_perf_add(struct perf_event *event, int flags)
1056 {
1057         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1058         struct hw_perf_event *hw = &event->hw;
1059
1060         hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1061
1062         /* Allocate an event counter */
1063         hw->idx = get_next_avail_cntr(pmu_dev);
1064         if (hw->idx < 0)
1065                 return -EAGAIN;
1066
1067         /* Update counter event pointer for Interrupt handler */
1068         pmu_dev->pmu_counter_event[hw->idx] = event;
1069
1070         if (flags & PERF_EF_START)
1071                 xgene_perf_start(event, PERF_EF_RELOAD);
1072
1073         return 0;
1074 }
1075
1076 static void xgene_perf_del(struct perf_event *event, int flags)
1077 {
1078         struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1079         struct hw_perf_event *hw = &event->hw;
1080
1081         xgene_perf_stop(event, PERF_EF_UPDATE);
1082
1083         /* clear the assigned counter */
1084         clear_avail_cntr(pmu_dev, GET_CNTR(event));
1085
1086         perf_event_update_userpage(event);
1087         pmu_dev->pmu_counter_event[hw->idx] = NULL;
1088 }
1089
1090 static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1091 {
1092         struct xgene_pmu *xgene_pmu;
1093
1094         if (pmu_dev->parent->version == PCP_PMU_V3)
1095                 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1096         else
1097                 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
1098         /* First version PMU supports only single event counter */
1099         xgene_pmu = pmu_dev->parent;
1100         if (xgene_pmu->version == PCP_PMU_V1)
1101                 pmu_dev->max_counters = 1;
1102         else
1103                 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1104
1105         /* Perf driver registration */
1106         pmu_dev->pmu = (struct pmu) {
1107                 .attr_groups    = pmu_dev->attr_groups,
1108                 .task_ctx_nr    = perf_invalid_context,
1109                 .pmu_enable     = xgene_perf_pmu_enable,
1110                 .pmu_disable    = xgene_perf_pmu_disable,
1111                 .event_init     = xgene_perf_event_init,
1112                 .add            = xgene_perf_add,
1113                 .del            = xgene_perf_del,
1114                 .start          = xgene_perf_start,
1115                 .stop           = xgene_perf_stop,
1116                 .read           = xgene_perf_read,
1117                 .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
1118         };
1119
1120         /* Hardware counter init */
1121         xgene_pmu->ops->stop_counters(pmu_dev);
1122         xgene_pmu->ops->reset_counters(pmu_dev);
1123
1124         return perf_pmu_register(&pmu_dev->pmu, name, -1);
1125 }
1126
1127 static int
1128 xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)
1129 {
1130         struct device *dev = xgene_pmu->dev;
1131         struct xgene_pmu_dev *pmu;
1132
1133         pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
1134         if (!pmu)
1135                 return -ENOMEM;
1136         pmu->parent = xgene_pmu;
1137         pmu->inf = &ctx->inf;
1138         ctx->pmu_dev = pmu;
1139
1140         switch (pmu->inf->type) {
1141         case PMU_TYPE_L3C:
1142                 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
1143                         return -ENODEV;
1144                 if (xgene_pmu->version == PCP_PMU_V3)
1145                         pmu->attr_groups = l3c_pmu_v3_attr_groups;
1146                 else
1147                         pmu->attr_groups = l3c_pmu_attr_groups;
1148                 break;
1149         case PMU_TYPE_IOB:
1150                 if (xgene_pmu->version == PCP_PMU_V3)
1151                         pmu->attr_groups = iob_fast_pmu_v3_attr_groups;
1152                 else
1153                         pmu->attr_groups = iob_pmu_attr_groups;
1154                 break;
1155         case PMU_TYPE_IOB_SLOW:
1156                 if (xgene_pmu->version == PCP_PMU_V3)
1157                         pmu->attr_groups = iob_slow_pmu_v3_attr_groups;
1158                 break;
1159         case PMU_TYPE_MCB:
1160                 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
1161                         return -ENODEV;
1162                 if (xgene_pmu->version == PCP_PMU_V3)
1163                         pmu->attr_groups = mcb_pmu_v3_attr_groups;
1164                 else
1165                         pmu->attr_groups = mcb_pmu_attr_groups;
1166                 break;
1167         case PMU_TYPE_MC:
1168                 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
1169                         return -ENODEV;
1170                 if (xgene_pmu->version == PCP_PMU_V3)
1171                         pmu->attr_groups = mc_pmu_v3_attr_groups;
1172                 else
1173                         pmu->attr_groups = mc_pmu_attr_groups;
1174                 break;
1175         default:
1176                 return -EINVAL;
1177         }
1178
1179         if (xgene_init_perf(pmu, ctx->name)) {
1180                 dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);
1181                 return -ENODEV;
1182         }
1183
1184         dev_info(dev, "%s PMU registered\n", ctx->name);
1185
1186         return 0;
1187 }
1188
1189 static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1190 {
1191         struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1192         void __iomem *csr = pmu_dev->inf->csr;
1193         u32 pmovsr;
1194         int idx;
1195
1196         xgene_pmu->ops->stop_counters(pmu_dev);
1197
1198         if (xgene_pmu->version == PCP_PMU_V3)
1199                 pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;
1200         else
1201                 pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;
1202
1203         if (!pmovsr)
1204                 goto out;
1205
1206         /* Clear interrupt flag */
1207         if (xgene_pmu->version == PCP_PMU_V1)
1208                 writel(0x0, csr + PMU_PMOVSR);
1209         else if (xgene_pmu->version == PCP_PMU_V2)
1210                 writel(pmovsr, csr + PMU_PMOVSR);
1211         else
1212                 writel(pmovsr, csr + PMU_PMOVSCLR);
1213
1214         for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) {
1215                 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1216                 int overflowed = pmovsr & BIT(idx);
1217
1218                 /* Ignore if we don't have an event. */
1219                 if (!event || !overflowed)
1220                         continue;
1221                 xgene_perf_event_update(event);
1222                 xgene_perf_event_set_period(event);
1223         }
1224
1225 out:
1226         xgene_pmu->ops->start_counters(pmu_dev);
1227 }
1228
1229 static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)
1230 {
1231         u32 intr_mcu, intr_mcb, intr_l3c, intr_iob;
1232         struct xgene_pmu_dev_ctx *ctx;
1233         struct xgene_pmu *xgene_pmu = dev_id;
1234         u32 val;
1235
1236         raw_spin_lock(&xgene_pmu->lock);
1237
1238         /* Get Interrupt PMU source */
1239         val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);
1240         if (xgene_pmu->version == PCP_PMU_V3) {
1241                 intr_mcu = PCPPMU_V3_INT_MCU;
1242                 intr_mcb = PCPPMU_V3_INT_MCB;
1243                 intr_l3c = PCPPMU_V3_INT_L3C;
1244                 intr_iob = PCPPMU_V3_INT_IOB;
1245         } else {
1246                 intr_mcu = PCPPMU_INT_MCU;
1247                 intr_mcb = PCPPMU_INT_MCB;
1248                 intr_l3c = PCPPMU_INT_L3C;
1249                 intr_iob = PCPPMU_INT_IOB;
1250         }
1251         if (val & intr_mcu) {
1252                 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1253                         _xgene_pmu_isr(irq, ctx->pmu_dev);
1254                 }
1255         }
1256         if (val & intr_mcb) {
1257                 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1258                         _xgene_pmu_isr(irq, ctx->pmu_dev);
1259                 }
1260         }
1261         if (val & intr_l3c) {
1262                 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1263                         _xgene_pmu_isr(irq, ctx->pmu_dev);
1264                 }
1265         }
1266         if (val & intr_iob) {
1267                 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1268                         _xgene_pmu_isr(irq, ctx->pmu_dev);
1269                 }
1270         }
1271
1272         raw_spin_unlock(&xgene_pmu->lock);
1273
1274         return IRQ_HANDLED;
1275 }
1276
1277 static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1278                                              struct platform_device *pdev)
1279 {
1280         void __iomem *csw_csr, *mcba_csr, *mcbb_csr;
1281         unsigned int reg;
1282
1283         csw_csr = devm_platform_ioremap_resource(pdev, 1);
1284         if (IS_ERR(csw_csr)) {
1285                 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1286                 return PTR_ERR(csw_csr);
1287         }
1288
1289         mcba_csr = devm_platform_ioremap_resource(pdev, 2);
1290         if (IS_ERR(mcba_csr)) {
1291                 dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");
1292                 return PTR_ERR(mcba_csr);
1293         }
1294
1295         mcbb_csr = devm_platform_ioremap_resource(pdev, 3);
1296         if (IS_ERR(mcbb_csr)) {
1297                 dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");
1298                 return PTR_ERR(mcbb_csr);
1299         }
1300
1301         xgene_pmu->l3c_active_mask = 0x1;
1302
1303         reg = readl(csw_csr + CSW_CSWCR);
1304         if (reg & CSW_CSWCR_DUALMCB_MASK) {
1305                 /* Dual MCB active */
1306                 xgene_pmu->mcb_active_mask = 0x3;
1307                 /* Probe all active MC(s) */
1308                 reg = readl(mcbb_csr + CSW_CSWCR);
1309                 xgene_pmu->mc_active_mask =
1310                         (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1311         } else {
1312                 /* Single MCB active */
1313                 xgene_pmu->mcb_active_mask = 0x1;
1314                 /* Probe all active MC(s) */
1315                 reg = readl(mcba_csr + CSW_CSWCR);
1316                 xgene_pmu->mc_active_mask =
1317                         (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1318         }
1319
1320         return 0;
1321 }
1322
1323 static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1324                                                 struct platform_device *pdev)
1325 {
1326         void __iomem *csw_csr;
1327         unsigned int reg;
1328         u32 mcb0routing;
1329         u32 mcb1routing;
1330
1331         csw_csr = devm_platform_ioremap_resource(pdev, 1);
1332         if (IS_ERR(csw_csr)) {
1333                 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1334                 return PTR_ERR(csw_csr);
1335         }
1336
1337         reg = readl(csw_csr + CSW_CSWCR);
1338         mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg);
1339         mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg);
1340         if (reg & CSW_CSWCR_DUALMCB_MASK) {
1341                 /* Dual MCB active */
1342                 xgene_pmu->mcb_active_mask = 0x3;
1343                 /* Probe all active L3C(s), maximum is 8 */
1344                 xgene_pmu->l3c_active_mask = 0xFF;
1345                 /* Probe all active MC(s), maximum is 8 */
1346                 if ((mcb0routing == 0x2) && (mcb1routing == 0x2))
1347                         xgene_pmu->mc_active_mask = 0xFF;
1348                 else if ((mcb0routing == 0x1) && (mcb1routing == 0x1))
1349                         xgene_pmu->mc_active_mask =  0x33;
1350                 else
1351                         xgene_pmu->mc_active_mask =  0x11;
1352         } else {
1353                 /* Single MCB active */
1354                 xgene_pmu->mcb_active_mask = 0x1;
1355                 /* Probe all active L3C(s), maximum is 4 */
1356                 xgene_pmu->l3c_active_mask = 0x0F;
1357                 /* Probe all active MC(s), maximum is 4 */
1358                 if (mcb0routing == 0x2)
1359                         xgene_pmu->mc_active_mask = 0x0F;
1360                 else if (mcb0routing == 0x1)
1361                         xgene_pmu->mc_active_mask =  0x03;
1362                 else
1363                         xgene_pmu->mc_active_mask =  0x01;
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1370                                             struct platform_device *pdev)
1371 {
1372         struct regmap *csw_map, *mcba_map, *mcbb_map;
1373         struct device_node *np = pdev->dev.of_node;
1374         unsigned int reg;
1375
1376         csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");
1377         if (IS_ERR(csw_map)) {
1378                 dev_err(&pdev->dev, "unable to get syscon regmap csw\n");
1379                 return PTR_ERR(csw_map);
1380         }
1381
1382         mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");
1383         if (IS_ERR(mcba_map)) {
1384                 dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");
1385                 return PTR_ERR(mcba_map);
1386         }
1387
1388         mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");
1389         if (IS_ERR(mcbb_map)) {
1390                 dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");
1391                 return PTR_ERR(mcbb_map);
1392         }
1393
1394         xgene_pmu->l3c_active_mask = 0x1;
1395         if (regmap_read(csw_map, CSW_CSWCR, &reg))
1396                 return -EINVAL;
1397
1398         if (reg & CSW_CSWCR_DUALMCB_MASK) {
1399                 /* Dual MCB active */
1400                 xgene_pmu->mcb_active_mask = 0x3;
1401                 /* Probe all active MC(s) */
1402                 if (regmap_read(mcbb_map, MCBADDRMR, &reg))
1403                         return 0;
1404                 xgene_pmu->mc_active_mask =
1405                         (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1406         } else {
1407                 /* Single MCB active */
1408                 xgene_pmu->mcb_active_mask = 0x1;
1409                 /* Probe all active MC(s) */
1410                 if (regmap_read(mcba_map, MCBADDRMR, &reg))
1411                         return 0;
1412                 xgene_pmu->mc_active_mask =
1413                         (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1414         }
1415
1416         return 0;
1417 }
1418
1419 static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1420                                               struct platform_device *pdev)
1421 {
1422         if (has_acpi_companion(&pdev->dev)) {
1423                 if (xgene_pmu->version == PCP_PMU_V3)
1424                         return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,
1425                                                                     pdev);
1426                 else
1427                         return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,
1428                                                                  pdev);
1429         }
1430         return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
1431 }
1432
1433 static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)
1434 {
1435         switch (type) {
1436         case PMU_TYPE_L3C:
1437                 return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id);
1438         case PMU_TYPE_IOB:
1439                 return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id);
1440         case PMU_TYPE_IOB_SLOW:
1441                 return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id);
1442         case PMU_TYPE_MCB:
1443                 return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id);
1444         case PMU_TYPE_MC:
1445                 return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id);
1446         default:
1447                 return devm_kasprintf(dev, GFP_KERNEL, "unknown");
1448         }
1449 }
1450
1451 #if defined(CONFIG_ACPI)
1452 static struct
1453 xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1454                                        struct acpi_device *adev, u32 type)
1455 {
1456         struct device *dev = xgene_pmu->dev;
1457         struct list_head resource_list;
1458         struct xgene_pmu_dev_ctx *ctx;
1459         const union acpi_object *obj;
1460         struct hw_pmu_info *inf;
1461         void __iomem *dev_csr;
1462         struct resource res;
1463         struct resource_entry *rentry;
1464         int enable_bit;
1465         int rc;
1466
1467         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1468         if (!ctx)
1469                 return NULL;
1470
1471         INIT_LIST_HEAD(&resource_list);
1472         rc = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
1473         if (rc <= 0) {
1474                 dev_err(dev, "PMU type %d: No resources found\n", type);
1475                 return NULL;
1476         }
1477
1478         list_for_each_entry(rentry, &resource_list, node) {
1479                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
1480                         res = *rentry->res;
1481                         rentry = NULL;
1482                         break;
1483                 }
1484         }
1485         acpi_dev_free_resource_list(&resource_list);
1486
1487         if (rentry) {
1488                 dev_err(dev, "PMU type %d: No memory resource found\n", type);
1489                 return NULL;
1490         }
1491
1492         dev_csr = devm_ioremap_resource(dev, &res);
1493         if (IS_ERR(dev_csr)) {
1494                 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
1495                 return NULL;
1496         }
1497
1498         /* A PMU device node without enable-bit-index is always enabled */
1499         rc = acpi_dev_get_property(adev, "enable-bit-index",
1500                                    ACPI_TYPE_INTEGER, &obj);
1501         if (rc < 0)
1502                 enable_bit = 0;
1503         else
1504                 enable_bit = (int) obj->integer.value;
1505
1506         ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1507         if (!ctx->name) {
1508                 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
1509                 return NULL;
1510         }
1511         inf = &ctx->inf;
1512         inf->type = type;
1513         inf->csr = dev_csr;
1514         inf->enable_mask = 1 << enable_bit;
1515
1516         return ctx;
1517 }
1518
1519 static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {
1520         {"APMC0D5D", PMU_TYPE_L3C},
1521         {"APMC0D5E", PMU_TYPE_IOB},
1522         {"APMC0D5F", PMU_TYPE_MCB},
1523         {"APMC0D60", PMU_TYPE_MC},
1524         {"APMC0D84", PMU_TYPE_L3C},
1525         {"APMC0D85", PMU_TYPE_IOB},
1526         {"APMC0D86", PMU_TYPE_IOB_SLOW},
1527         {"APMC0D87", PMU_TYPE_MCB},
1528         {"APMC0D88", PMU_TYPE_MC},
1529         {},
1530 };
1531
1532 static const struct acpi_device_id *xgene_pmu_acpi_match_type(
1533                                         const struct acpi_device_id *ids,
1534                                         struct acpi_device *adev)
1535 {
1536         const struct acpi_device_id *match_id = NULL;
1537         const struct acpi_device_id *id;
1538
1539         for (id = ids; id->id[0] || id->cls; id++) {
1540                 if (!acpi_match_device_ids(adev, id))
1541                         match_id = id;
1542                 else if (match_id)
1543                         break;
1544         }
1545
1546         return match_id;
1547 }
1548
1549 static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
1550                                     void *data, void **return_value)
1551 {
1552         struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
1553         const struct acpi_device_id *acpi_id;
1554         struct xgene_pmu *xgene_pmu = data;
1555         struct xgene_pmu_dev_ctx *ctx;
1556
1557         if (!adev || acpi_bus_get_status(adev) || !adev->status.present)
1558                 return AE_OK;
1559
1560         acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
1561         if (!acpi_id)
1562                 return AE_OK;
1563
1564         ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);
1565         if (!ctx)
1566                 return AE_OK;
1567
1568         if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1569                 /* Can't add the PMU device, skip it */
1570                 devm_kfree(xgene_pmu->dev, ctx);
1571                 return AE_OK;
1572         }
1573
1574         switch (ctx->inf.type) {
1575         case PMU_TYPE_L3C:
1576                 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1577                 break;
1578         case PMU_TYPE_IOB:
1579                 list_add(&ctx->next, &xgene_pmu->iobpmus);
1580                 break;
1581         case PMU_TYPE_IOB_SLOW:
1582                 list_add(&ctx->next, &xgene_pmu->iobpmus);
1583                 break;
1584         case PMU_TYPE_MCB:
1585                 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1586                 break;
1587         case PMU_TYPE_MC:
1588                 list_add(&ctx->next, &xgene_pmu->mcpmus);
1589                 break;
1590         }
1591         return AE_OK;
1592 }
1593
1594 static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1595                                   struct platform_device *pdev)
1596 {
1597         struct device *dev = xgene_pmu->dev;
1598         acpi_handle handle;
1599         acpi_status status;
1600
1601         handle = ACPI_HANDLE(dev);
1602         if (!handle)
1603                 return -EINVAL;
1604
1605         status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1606                                      acpi_pmu_dev_add, NULL, xgene_pmu, NULL);
1607         if (ACPI_FAILURE(status)) {
1608                 dev_err(dev, "failed to probe PMU devices\n");
1609                 return -ENODEV;
1610         }
1611
1612         return 0;
1613 }
1614 #else
1615 static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1616                                   struct platform_device *pdev)
1617 {
1618         return 0;
1619 }
1620 #endif
1621
1622 static struct
1623 xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1624                                       struct device_node *np, u32 type)
1625 {
1626         struct device *dev = xgene_pmu->dev;
1627         struct xgene_pmu_dev_ctx *ctx;
1628         struct hw_pmu_info *inf;
1629         void __iomem *dev_csr;
1630         struct resource res;
1631         int enable_bit;
1632
1633         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1634         if (!ctx)
1635                 return NULL;
1636
1637         if (of_address_to_resource(np, 0, &res) < 0) {
1638                 dev_err(dev, "PMU type %d: No resource address found\n", type);
1639                 return NULL;
1640         }
1641
1642         dev_csr = devm_ioremap_resource(dev, &res);
1643         if (IS_ERR(dev_csr)) {
1644                 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
1645                 return NULL;
1646         }
1647
1648         /* A PMU device node without enable-bit-index is always enabled */
1649         if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
1650                 enable_bit = 0;
1651
1652         ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1653         if (!ctx->name) {
1654                 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
1655                 return NULL;
1656         }
1657
1658         inf = &ctx->inf;
1659         inf->type = type;
1660         inf->csr = dev_csr;
1661         inf->enable_mask = 1 << enable_bit;
1662
1663         return ctx;
1664 }
1665
1666 static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1667                                  struct platform_device *pdev)
1668 {
1669         struct xgene_pmu_dev_ctx *ctx;
1670         struct device_node *np;
1671
1672         for_each_child_of_node(pdev->dev.of_node, np) {
1673                 if (!of_device_is_available(np))
1674                         continue;
1675
1676                 if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))
1677                         ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C);
1678                 else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))
1679                         ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB);
1680                 else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))
1681                         ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB);
1682                 else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))
1683                         ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC);
1684                 else
1685                         ctx = NULL;
1686
1687                 if (!ctx)
1688                         continue;
1689
1690                 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1691                         /* Can't add the PMU device, skip it */
1692                         devm_kfree(xgene_pmu->dev, ctx);
1693                         continue;
1694                 }
1695
1696                 switch (ctx->inf.type) {
1697                 case PMU_TYPE_L3C:
1698                         list_add(&ctx->next, &xgene_pmu->l3cpmus);
1699                         break;
1700                 case PMU_TYPE_IOB:
1701                         list_add(&ctx->next, &xgene_pmu->iobpmus);
1702                         break;
1703                 case PMU_TYPE_IOB_SLOW:
1704                         list_add(&ctx->next, &xgene_pmu->iobpmus);
1705                         break;
1706                 case PMU_TYPE_MCB:
1707                         list_add(&ctx->next, &xgene_pmu->mcbpmus);
1708                         break;
1709                 case PMU_TYPE_MC:
1710                         list_add(&ctx->next, &xgene_pmu->mcpmus);
1711                         break;
1712                 }
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1719                                    struct platform_device *pdev)
1720 {
1721         if (has_acpi_companion(&pdev->dev))
1722                 return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);
1723         return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);
1724 }
1725
1726 static const struct xgene_pmu_data xgene_pmu_data = {
1727         .id   = PCP_PMU_V1,
1728 };
1729
1730 static const struct xgene_pmu_data xgene_pmu_v2_data = {
1731         .id   = PCP_PMU_V2,
1732 };
1733
1734 static const struct xgene_pmu_ops xgene_pmu_ops = {
1735         .mask_int = xgene_pmu_mask_int,
1736         .unmask_int = xgene_pmu_unmask_int,
1737         .read_counter = xgene_pmu_read_counter32,
1738         .write_counter = xgene_pmu_write_counter32,
1739         .write_evttype = xgene_pmu_write_evttype,
1740         .write_agentmsk = xgene_pmu_write_agentmsk,
1741         .write_agent1msk = xgene_pmu_write_agent1msk,
1742         .enable_counter = xgene_pmu_enable_counter,
1743         .disable_counter = xgene_pmu_disable_counter,
1744         .enable_counter_int = xgene_pmu_enable_counter_int,
1745         .disable_counter_int = xgene_pmu_disable_counter_int,
1746         .reset_counters = xgene_pmu_reset_counters,
1747         .start_counters = xgene_pmu_start_counters,
1748         .stop_counters = xgene_pmu_stop_counters,
1749 };
1750
1751 static const struct xgene_pmu_ops xgene_pmu_v3_ops = {
1752         .mask_int = xgene_pmu_v3_mask_int,
1753         .unmask_int = xgene_pmu_v3_unmask_int,
1754         .read_counter = xgene_pmu_read_counter64,
1755         .write_counter = xgene_pmu_write_counter64,
1756         .write_evttype = xgene_pmu_write_evttype,
1757         .write_agentmsk = xgene_pmu_v3_write_agentmsk,
1758         .write_agent1msk = xgene_pmu_v3_write_agent1msk,
1759         .enable_counter = xgene_pmu_enable_counter,
1760         .disable_counter = xgene_pmu_disable_counter,
1761         .enable_counter_int = xgene_pmu_enable_counter_int,
1762         .disable_counter_int = xgene_pmu_disable_counter_int,
1763         .reset_counters = xgene_pmu_reset_counters,
1764         .start_counters = xgene_pmu_start_counters,
1765         .stop_counters = xgene_pmu_stop_counters,
1766 };
1767
1768 static const struct of_device_id xgene_pmu_of_match[] = {
1769         { .compatible   = "apm,xgene-pmu",      .data = &xgene_pmu_data },
1770         { .compatible   = "apm,xgene-pmu-v2",   .data = &xgene_pmu_v2_data },
1771         {},
1772 };
1773 MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
1774 #ifdef CONFIG_ACPI
1775 static const struct acpi_device_id xgene_pmu_acpi_match[] = {
1776         {"APMC0D5B", PCP_PMU_V1},
1777         {"APMC0D5C", PCP_PMU_V2},
1778         {"APMC0D83", PCP_PMU_V3},
1779         {},
1780 };
1781 MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match);
1782 #endif
1783
1784 static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
1785 {
1786         struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1787                                                        node);
1788
1789         if (cpumask_empty(&xgene_pmu->cpu))
1790                 cpumask_set_cpu(cpu, &xgene_pmu->cpu);
1791
1792         /* Overflow interrupt also should use the same CPU */
1793         WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1794
1795         return 0;
1796 }
1797
1798 static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1799 {
1800         struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1801                                                        node);
1802         struct xgene_pmu_dev_ctx *ctx;
1803         unsigned int target;
1804
1805         if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))
1806                 return 0;
1807         target = cpumask_any_but(cpu_online_mask, cpu);
1808         if (target >= nr_cpu_ids)
1809                 return 0;
1810
1811         list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1812                 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1813         }
1814         list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1815                 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1816         }
1817         list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1818                 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1819         }
1820         list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1821                 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1822         }
1823
1824         cpumask_set_cpu(target, &xgene_pmu->cpu);
1825         /* Overflow interrupt also should use the same CPU */
1826         WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1827
1828         return 0;
1829 }
1830
1831 static int xgene_pmu_probe(struct platform_device *pdev)
1832 {
1833         const struct xgene_pmu_data *dev_data;
1834         const struct of_device_id *of_id;
1835         struct xgene_pmu *xgene_pmu;
1836         int irq, rc;
1837         int version;
1838
1839         /* Install a hook to update the reader CPU in case it goes offline */
1840         rc = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1841                                       "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE",
1842                                       xgene_pmu_online_cpu,
1843                                       xgene_pmu_offline_cpu);
1844         if (rc)
1845                 return rc;
1846
1847         xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);
1848         if (!xgene_pmu)
1849                 return -ENOMEM;
1850         xgene_pmu->dev = &pdev->dev;
1851         platform_set_drvdata(pdev, xgene_pmu);
1852
1853         version = -EINVAL;
1854         of_id = of_match_device(xgene_pmu_of_match, &pdev->dev);
1855         if (of_id) {
1856                 dev_data = (const struct xgene_pmu_data *) of_id->data;
1857                 version = dev_data->id;
1858         }
1859
1860 #ifdef CONFIG_ACPI
1861         if (ACPI_COMPANION(&pdev->dev)) {
1862                 const struct acpi_device_id *acpi_id;
1863
1864                 acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev);
1865                 if (acpi_id)
1866                         version = (int) acpi_id->driver_data;
1867         }
1868 #endif
1869         if (version < 0)
1870                 return -ENODEV;
1871
1872         if (version == PCP_PMU_V3)
1873                 xgene_pmu->ops = &xgene_pmu_v3_ops;
1874         else
1875                 xgene_pmu->ops = &xgene_pmu_ops;
1876
1877         INIT_LIST_HEAD(&xgene_pmu->l3cpmus);
1878         INIT_LIST_HEAD(&xgene_pmu->iobpmus);
1879         INIT_LIST_HEAD(&xgene_pmu->mcbpmus);
1880         INIT_LIST_HEAD(&xgene_pmu->mcpmus);
1881
1882         xgene_pmu->version = version;
1883         dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);
1884
1885         xgene_pmu->pcppmu_csr = devm_platform_ioremap_resource(pdev, 0);
1886         if (IS_ERR(xgene_pmu->pcppmu_csr)) {
1887                 dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");
1888                 return PTR_ERR(xgene_pmu->pcppmu_csr);
1889         }
1890
1891         irq = platform_get_irq(pdev, 0);
1892         if (irq < 0)
1893                 return -EINVAL;
1894
1895         rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,
1896                                 IRQF_NOBALANCING | IRQF_NO_THREAD,
1897                                 dev_name(&pdev->dev), xgene_pmu);
1898         if (rc) {
1899                 dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);
1900                 return rc;
1901         }
1902
1903         xgene_pmu->irq = irq;
1904
1905         raw_spin_lock_init(&xgene_pmu->lock);
1906
1907         /* Check for active MCBs and MCUs */
1908         rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
1909         if (rc) {
1910                 dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");
1911                 xgene_pmu->mcb_active_mask = 0x1;
1912                 xgene_pmu->mc_active_mask = 0x1;
1913         }
1914
1915         /* Add this instance to the list used by the hotplug callback */
1916         rc = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1917                                       &xgene_pmu->node);
1918         if (rc) {
1919                 dev_err(&pdev->dev, "Error %d registering hotplug", rc);
1920                 return rc;
1921         }
1922
1923         /* Walk through the tree for all PMU perf devices */
1924         rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev);
1925         if (rc) {
1926                 dev_err(&pdev->dev, "No PMU perf devices found!\n");
1927                 goto out_unregister;
1928         }
1929
1930         /* Enable interrupt */
1931         xgene_pmu->ops->unmask_int(xgene_pmu);
1932
1933         return 0;
1934
1935 out_unregister:
1936         cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1937                                     &xgene_pmu->node);
1938         return rc;
1939 }
1940
1941 static void
1942 xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus)
1943 {
1944         struct xgene_pmu_dev_ctx *ctx;
1945
1946         list_for_each_entry(ctx, pmus, next) {
1947                 perf_pmu_unregister(&ctx->pmu_dev->pmu);
1948         }
1949 }
1950
1951 static int xgene_pmu_remove(struct platform_device *pdev)
1952 {
1953         struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);
1954
1955         xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);
1956         xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);
1957         xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);
1958         xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);
1959         cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1960                                     &xgene_pmu->node);
1961
1962         return 0;
1963 }
1964
1965 static struct platform_driver xgene_pmu_driver = {
1966         .probe = xgene_pmu_probe,
1967         .remove = xgene_pmu_remove,
1968         .driver = {
1969                 .name           = "xgene-pmu",
1970                 .of_match_table = xgene_pmu_of_match,
1971                 .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match),
1972                 .suppress_bind_attrs = true,
1973         },
1974 };
1975
1976 builtin_platform_driver(xgene_pmu_driver);