drivers/perf/riscv_pmu_sbi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * RISC-V performance counter support.
   4  *
   5  * Copyright (C) 2021 Western Digital Corporation or its affiliates.
   6  *
   7  * This code is based on ARM perf event code which is in turn based on
   8  * sparc64 and x86 code.
   9  */
  10
  11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
  12
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/perf/riscv_pmu.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of.h>
  20 #include <linux/cpu_pm.h>
  21 #include <linux/sched/clock.h>
  22
  23 #include <asm/errata_list.h>
  24 #include <asm/sbi.h>
  25 #include <asm/hwcap.h>
  26
  27 #define SYSCTL_NO_USER_ACCESS   0
  28 #define SYSCTL_USER_ACCESS      1
  29 #define SYSCTL_LEGACY           2
  30
  31 #define PERF_EVENT_FLAG_NO_USER_ACCESS  BIT(SYSCTL_NO_USER_ACCESS)
  32 #define PERF_EVENT_FLAG_USER_ACCESS     BIT(SYSCTL_USER_ACCESS)
  33 #define PERF_EVENT_FLAG_LEGACY          BIT(SYSCTL_LEGACY)
  34
  35 PMU_FORMAT_ATTR(event, "config:0-47");
  36 PMU_FORMAT_ATTR(firmware, "config:63");
  37
  38 static struct attribute *riscv_arch_formats_attr[] = {
  39         &format_attr_event.attr,
  40         &format_attr_firmware.attr,
  41         NULL,
  42 };
  43
  44 static struct attribute_group riscv_pmu_format_group = {
  45         .name = "format",
  46         .attrs = riscv_arch_formats_attr,
  47 };
  48
  49 static const struct attribute_group *riscv_pmu_attr_groups[] = {
  50         &riscv_pmu_format_group,
  51         NULL,
  52 };
  53
  54 /* Allow user mode access by default */
  55 static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS;
  56
  57 /*
  58  * RISC-V doesn't have heterogeneous harts yet. This need to be part of
  59  * per_cpu in case of harts with different pmu counters
  60  */
  61 static union sbi_pmu_ctr_info *pmu_ctr_list;
  62 static bool riscv_pmu_use_irq;
  63 static unsigned int riscv_pmu_irq_num;
  64 static unsigned int riscv_pmu_irq;
  65
  66 /* Cache the available counters in a bitmask */
  67 static unsigned long cmask;
  68
  69 struct sbi_pmu_event_data {
  70         union {
  71                 union {
  72                         struct hw_gen_event {
  73                                 uint32_t event_code:16;
  74                                 uint32_t event_type:4;
  75                                 uint32_t reserved:12;
  76                         } hw_gen_event;
  77                         struct hw_cache_event {
  78                                 uint32_t result_id:1;
  79                                 uint32_t op_id:2;
  80                                 uint32_t cache_id:13;
  81                                 uint32_t event_type:4;
  82                                 uint32_t reserved:12;
  83                         } hw_cache_event;
  84                 };
  85                 uint32_t event_idx;
  86         };
  87 };
  88
  89 static const struct sbi_pmu_event_data pmu_hw_event_map[] = {
  90         [PERF_COUNT_HW_CPU_CYCLES]              = {.hw_gen_event = {
  91                                                         SBI_PMU_HW_CPU_CYCLES,
  92                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
  93         [PERF_COUNT_HW_INSTRUCTIONS]            = {.hw_gen_event = {
  94                                                         SBI_PMU_HW_INSTRUCTIONS,
  95                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
  96         [PERF_COUNT_HW_CACHE_REFERENCES]        = {.hw_gen_event = {
  97                                                         SBI_PMU_HW_CACHE_REFERENCES,
  98                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
  99         [PERF_COUNT_HW_CACHE_MISSES]            = {.hw_gen_event = {
 100                                                         SBI_PMU_HW_CACHE_MISSES,
 101                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 102         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = {.hw_gen_event = {
 103                                                         SBI_PMU_HW_BRANCH_INSTRUCTIONS,
 104                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 105         [PERF_COUNT_HW_BRANCH_MISSES]           = {.hw_gen_event = {
 106                                                         SBI_PMU_HW_BRANCH_MISSES,
 107                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 108         [PERF_COUNT_HW_BUS_CYCLES]              = {.hw_gen_event = {
 109                                                         SBI_PMU_HW_BUS_CYCLES,
 110                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 111         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = {.hw_gen_event = {
 112                                                         SBI_PMU_HW_STALLED_CYCLES_FRONTEND,
 113                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 114         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = {.hw_gen_event = {
 115                                                         SBI_PMU_HW_STALLED_CYCLES_BACKEND,
 116                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 117         [PERF_COUNT_HW_REF_CPU_CYCLES]          = {.hw_gen_event = {
 118                                                         SBI_PMU_HW_REF_CPU_CYCLES,
 119                                                         SBI_PMU_EVENT_TYPE_HW, 0}},
 120 };
 121
 122 #define C(x) PERF_COUNT_HW_CACHE_##x
 123 static const struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
 124 [PERF_COUNT_HW_CACHE_OP_MAX]
 125 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 126         [C(L1D)] = {
 127                 [C(OP_READ)] = {
 128                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 129                                         C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 130                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 131                                         C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 132                 },
 133                 [C(OP_WRITE)] = {
 134                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 135                                         C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 136                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 137                                         C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 138                 },
 139                 [C(OP_PREFETCH)] = {
 140                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 141                                         C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 142                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 143                                         C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 144                 },
 145         },
 146         [C(L1I)] = {
 147                 [C(OP_READ)] = {
 148                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 149                                         C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 150                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
 151                                         C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 152                 },
 153                 [C(OP_WRITE)] = {
 154                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 155                                         C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 156                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 157                                         C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 158                 },
 159                 [C(OP_PREFETCH)] = {
 160                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 161                                         C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 162                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 163                                         C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 164                 },
 165         },
 166         [C(LL)] = {
 167                 [C(OP_READ)] = {
 168                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 169                                         C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 170                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 171                                         C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 172                 },
 173                 [C(OP_WRITE)] = {
 174                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 175                                         C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 176                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 177                                         C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 178                 },
 179                 [C(OP_PREFETCH)] = {
 180                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 181                                         C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 182                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 183                                         C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 184                 },
 185         },
 186         [C(DTLB)] = {
 187                 [C(OP_READ)] = {
 188                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 189                                         C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 190                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 191                                         C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 192                 },
 193                 [C(OP_WRITE)] = {
 194                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 195                                         C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 196                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 197                                         C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 198                 },
 199                 [C(OP_PREFETCH)] = {
 200                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 201                                         C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 202                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 203                                         C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 204                 },
 205         },
 206         [C(ITLB)] = {
 207                 [C(OP_READ)] = {
 208                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 209                                         C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 210                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 211                                         C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 212                 },
 213                 [C(OP_WRITE)] = {
 214                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 215                                         C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 216                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 217                                         C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 218                 },
 219                 [C(OP_PREFETCH)] = {
 220                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 221                                         C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 222                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 223                                         C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 224                 },
 225         },
 226         [C(BPU)] = {
 227                 [C(OP_READ)] = {
 228                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 229                                         C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 230                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 231                                         C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 232                 },
 233                 [C(OP_WRITE)] = {
 234                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 235                                         C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 236                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 237                                         C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 238                 },
 239                 [C(OP_PREFETCH)] = {
 240                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 241                                         C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 242                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 243                                         C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 244                 },
 245         },
 246         [C(NODE)] = {
 247                 [C(OP_READ)] = {
 248                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 249                                         C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 250                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 251                                         C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 252                 },
 253                 [C(OP_WRITE)] = {
 254                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 255                                         C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 256                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 257                                         C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 258                 },
 259                 [C(OP_PREFETCH)] = {
 260                         [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
 261                                         C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 262                         [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
 263                                         C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
 264                 },
 265         },
 266 };
 267
 268 static int pmu_sbi_ctr_get_width(int idx)
 269 {
 270         return pmu_ctr_list[idx].width;
 271 }
 272
 273 static bool pmu_sbi_ctr_is_fw(int cidx)
 274 {
 275         union sbi_pmu_ctr_info *info;
 276
 277         info = &pmu_ctr_list[cidx];
 278         if (!info)
 279                 return false;
 280
 281         return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
 282 }
 283
 284 /*
 285  * Returns the counter width of a programmable counter and number of hardware
 286  * counters. As we don't support heterogeneous CPUs yet, it is okay to just
 287  * return the counter width of the first programmable counter.
 288  */
 289 int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr)
 290 {
 291         int i;
 292         union sbi_pmu_ctr_info *info;
 293         u32 hpm_width = 0, hpm_count = 0;
 294
 295         if (!cmask)
 296                 return -EINVAL;
 297
 298         for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) {
 299                 info = &pmu_ctr_list[i];
 300                 if (!info)
 301                         continue;
 302                 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET)
 303                         hpm_width = info->width;
 304                 if (info->type == SBI_PMU_CTR_TYPE_HW)
 305                         hpm_count++;
 306         }
 307
 308         *hw_ctr_width = hpm_width;
 309         *num_hw_ctr = hpm_count;
 310
 311         return 0;
 312 }
 313 EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info);
 314
 315 static uint8_t pmu_sbi_csr_index(struct perf_event *event)
 316 {
 317         return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE;
 318 }
 319
 320 static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event)
 321 {
 322         unsigned long cflags = 0;
 323         bool guest_events = false;
 324
 325         if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS)
 326                 guest_events = true;
 327         if (event->attr.exclude_kernel)
 328                 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH;
 329         if (event->attr.exclude_user)
 330                 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH;
 331         if (guest_events && event->attr.exclude_hv)
 332                 cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
 333         if (event->attr.exclude_host)
 334                 cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH;
 335         if (event->attr.exclude_guest)
 336                 cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH;
 337
 338         return cflags;
 339 }
 340
 341 static int pmu_sbi_ctr_get_idx(struct perf_event *event)
 342 {
 343         struct hw_perf_event *hwc = &event->hw;
 344         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 345         struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
 346         struct sbiret ret;
 347         int idx;
 348         uint64_t cbase = 0, cmask = rvpmu->cmask;
 349         unsigned long cflags = 0;
 350
 351         cflags = pmu_sbi_get_filter_flags(event);
 352
 353         /*
 354          * In legacy mode, we have to force the fixed counters for those events
 355          * but not in the user access mode as we want to use the other counters
 356          * that support sampling/filtering.
 357          */
 358         if (hwc->flags & PERF_EVENT_FLAG_LEGACY) {
 359                 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) {
 360                         cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
 361                         cmask = 1;
 362                 } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) {
 363                         cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
 364                         cmask = 1UL << (CSR_INSTRET - CSR_CYCLE);
 365                 }
 366         }
 367
 368         /* retrieve the available counter index */
 369 #if defined(CONFIG_32BIT)
 370         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
 371                         cmask, cflags, hwc->event_base, hwc->config,
 372                         hwc->config >> 32);
 373 #else
 374         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
 375                         cmask, cflags, hwc->event_base, hwc->config, 0);
 376 #endif
 377         if (ret.error) {
 378                 pr_debug("Not able to find a counter for event %lx config %llx\n",
 379                         hwc->event_base, hwc->config);
 380                 return sbi_err_map_linux_errno(ret.error);
 381         }
 382
 383         idx = ret.value;
 384         if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value)
 385                 return -ENOENT;
 386
 387         /* Additional sanity check for the counter id */
 388         if (pmu_sbi_ctr_is_fw(idx)) {
 389                 if (!test_and_set_bit(idx, cpuc->used_fw_ctrs))
 390                         return idx;
 391         } else {
 392                 if (!test_and_set_bit(idx, cpuc->used_hw_ctrs))
 393                         return idx;
 394         }
 395
 396         return -ENOENT;
 397 }
 398
 399 static void pmu_sbi_ctr_clear_idx(struct perf_event *event)
 400 {
 401
 402         struct hw_perf_event *hwc = &event->hw;
 403         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 404         struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
 405         int idx = hwc->idx;
 406
 407         if (pmu_sbi_ctr_is_fw(idx))
 408                 clear_bit(idx, cpuc->used_fw_ctrs);
 409         else
 410                 clear_bit(idx, cpuc->used_hw_ctrs);
 411 }
 412
 413 static int pmu_event_find_cache(u64 config)
 414 {
 415         unsigned int cache_type, cache_op, cache_result, ret;
 416
 417         cache_type = (config >>  0) & 0xff;
 418         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 419                 return -EINVAL;
 420
 421         cache_op = (config >>  8) & 0xff;
 422         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 423                 return -EINVAL;
 424
 425         cache_result = (config >> 16) & 0xff;
 426         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 427                 return -EINVAL;
 428
 429         ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx;
 430
 431         return ret;
 432 }
 433
 434 static bool pmu_sbi_is_fw_event(struct perf_event *event)
 435 {
 436         u32 type = event->attr.type;
 437         u64 config = event->attr.config;
 438
 439         if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1))
 440                 return true;
 441         else
 442                 return false;
 443 }
 444
 445 static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
 446 {
 447         u32 type = event->attr.type;
 448         u64 config = event->attr.config;
 449         int bSoftware;
 450         u64 raw_config_val;
 451         int ret;
 452
 453         switch (type) {
 454         case PERF_TYPE_HARDWARE:
 455                 if (config >= PERF_COUNT_HW_MAX)
 456                         return -EINVAL;
 457                 ret = pmu_hw_event_map[event->attr.config].event_idx;
 458                 break;
 459         case PERF_TYPE_HW_CACHE:
 460                 ret = pmu_event_find_cache(config);
 461                 break;
 462         case PERF_TYPE_RAW:
 463                 /*
 464                  * As per SBI specification, the upper 16 bits must be unused for
 465                  * a raw event. Use the MSB (63b) to distinguish between hardware
 466                  * raw event and firmware events.
 467                  */
 468                 bSoftware = config >> 63;
 469                 raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
 470                 if (bSoftware) {
 471                         ret = (raw_config_val & 0xFFFF) |
 472                                 (SBI_PMU_EVENT_TYPE_FW << 16);
 473                 } else {
 474                         ret = RISCV_PMU_RAW_EVENT_IDX;
 475                         *econfig = raw_config_val;
 476                 }
 477                 break;
 478         default:
 479                 ret = -EINVAL;
 480                 break;
 481         }
 482
 483         return ret;
 484 }
 485
 486 static u64 pmu_sbi_ctr_read(struct perf_event *event)
 487 {
 488         struct hw_perf_event *hwc = &event->hw;
 489         int idx = hwc->idx;
 490         struct sbiret ret;
 491         union sbi_pmu_ctr_info info;
 492         u64 val = 0;
 493
 494         if (pmu_sbi_is_fw_event(event)) {
 495                 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
 496                                 hwc->idx, 0, 0, 0, 0, 0);
 497                 if (!ret.error)
 498                         val = ret.value;
 499         } else {
 500                 info = pmu_ctr_list[idx];
 501                 val = riscv_pmu_ctr_read_csr(info.csr);
 502                 if (IS_ENABLED(CONFIG_32BIT))
 503                         val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val;
 504         }
 505
 506         return val;
 507 }
 508
 509 static void pmu_sbi_set_scounteren(void *arg)
 510 {
 511         struct perf_event *event = (struct perf_event *)arg;
 512
 513         csr_write(CSR_SCOUNTEREN,
 514                   csr_read(CSR_SCOUNTEREN) | (1 << pmu_sbi_csr_index(event)));
 515 }
 516
 517 static void pmu_sbi_reset_scounteren(void *arg)
 518 {
 519         struct perf_event *event = (struct perf_event *)arg;
 520
 521         csr_write(CSR_SCOUNTEREN,
 522                   csr_read(CSR_SCOUNTEREN) & ~(1 << pmu_sbi_csr_index(event)));
 523 }
 524
 525 static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
 526 {
 527         struct sbiret ret;
 528         struct hw_perf_event *hwc = &event->hw;
 529         unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
 530
 531 #if defined(CONFIG_32BIT)
 532         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
 533                         1, flag, ival, ival >> 32, 0);
 534 #else
 535         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
 536                         1, flag, ival, 0, 0);
 537 #endif
 538         if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
 539                 pr_err("Starting counter idx %d failed with error %d\n",
 540                         hwc->idx, sbi_err_map_linux_errno(ret.error));
 541
 542         if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) &&
 543             (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
 544                 pmu_sbi_set_scounteren((void *)event);
 545 }
 546
 547 static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
 548 {
 549         struct sbiret ret;
 550         struct hw_perf_event *hwc = &event->hw;
 551
 552         if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) &&
 553             (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
 554                 pmu_sbi_reset_scounteren((void *)event);
 555
 556         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0);
 557         if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
 558                 flag != SBI_PMU_STOP_FLAG_RESET)
 559                 pr_err("Stopping counter idx %d failed with error %d\n",
 560                         hwc->idx, sbi_err_map_linux_errno(ret.error));
 561 }
 562
 563 static int pmu_sbi_find_num_ctrs(void)
 564 {
 565         struct sbiret ret;
 566
 567         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0);
 568         if (!ret.error)
 569                 return ret.value;
 570         else
 571                 return sbi_err_map_linux_errno(ret.error);
 572 }
 573
 574 static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
 575 {
 576         struct sbiret ret;
 577         int i, num_hw_ctr = 0, num_fw_ctr = 0;
 578         union sbi_pmu_ctr_info cinfo;
 579
 580         pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL);
 581         if (!pmu_ctr_list)
 582                 return -ENOMEM;
 583
 584         for (i = 0; i < nctr; i++) {
 585                 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
 586                 if (ret.error)
 587                         /* The logical counter ids are not expected to be contiguous */
 588                         continue;
 589
 590                 *mask |= BIT(i);
 591
 592                 cinfo.value = ret.value;
 593                 if (cinfo.type == SBI_PMU_CTR_TYPE_FW)
 594                         num_fw_ctr++;
 595                 else
 596                         num_hw_ctr++;
 597                 pmu_ctr_list[i].value = cinfo.value;
 598         }
 599
 600         pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr);
 601
 602         return 0;
 603 }
 604
 605 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
 606 {
 607         /*
 608          * No need to check the error because we are disabling all the counters
 609          * which may include counters that are not enabled yet.
 610          */
 611         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
 612                   0, pmu->cmask, 0, 0, 0, 0);
 613 }
 614
 615 static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
 616 {
 617         struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
 618
 619         /* No need to check the error here as we can't do anything about the error */
 620         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0,
 621                   cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0);
 622 }
 623
 624 /*
 625  * This function starts all the used counters in two step approach.
 626  * Any counter that did not overflow can be start in a single step
 627  * while the overflowed counters need to be started with updated initialization
 628  * value.
 629  */
 630 static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 631                                                unsigned long ctr_ovf_mask)
 632 {
 633         int idx = 0;
 634         struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
 635         struct perf_event *event;
 636         unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
 637         unsigned long ctr_start_mask = 0;
 638         uint64_t max_period;
 639         struct hw_perf_event *hwc;
 640         u64 init_val = 0;
 641
 642         ctr_start_mask = cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask;
 643
 644         /* Start all the counters that did not overflow in a single shot */
 645         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask,
 646                   0, 0, 0, 0);
 647
 648         /* Reinitialize and start all the counter that overflowed */
 649         while (ctr_ovf_mask) {
 650                 if (ctr_ovf_mask & 0x01) {
 651                         event = cpu_hw_evt->events[idx];
 652                         hwc = &event->hw;
 653                         max_period = riscv_pmu_ctr_get_width_mask(event);
 654                         init_val = local64_read(&hwc->prev_count) & max_period;
 655 #if defined(CONFIG_32BIT)
 656                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 657                                   flag, init_val, init_val >> 32, 0);
 658 #else
 659                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 660                                   flag, init_val, 0, 0);
 661 #endif
 662                         perf_event_update_userpage(event);
 663                 }
 664                 ctr_ovf_mask = ctr_ovf_mask >> 1;
 665                 idx++;
 666         }
 667 }
 668
 669 static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
 670 {
 671         struct perf_sample_data data;
 672         struct pt_regs *regs;
 673         struct hw_perf_event *hw_evt;
 674         union sbi_pmu_ctr_info *info;
 675         int lidx, hidx, fidx;
 676         struct riscv_pmu *pmu;
 677         struct perf_event *event;
 678         unsigned long overflow;
 679         unsigned long overflowed_ctrs = 0;
 680         struct cpu_hw_events *cpu_hw_evt = dev;
 681         u64 start_clock = sched_clock();
 682
 683         if (WARN_ON_ONCE(!cpu_hw_evt))
 684                 return IRQ_NONE;
 685
 686         /* Firmware counter don't support overflow yet */
 687         fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
 688         event = cpu_hw_evt->events[fidx];
 689         if (!event) {
 690                 csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
 691                 return IRQ_NONE;
 692         }
 693
 694         pmu = to_riscv_pmu(event->pmu);
 695         pmu_sbi_stop_hw_ctrs(pmu);
 696
 697         /* Overflow status register should only be read after counter are stopped */
 698         ALT_SBI_PMU_OVERFLOW(overflow);
 699
 700         /*
 701          * Overflow interrupt pending bit should only be cleared after stopping
 702          * all the counters to avoid any race condition.
 703          */
 704         csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
 705
 706         /* No overflow bit is set */
 707         if (!overflow)
 708                 return IRQ_NONE;
 709
 710         regs = get_irq_regs();
 711
 712         for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
 713                 struct perf_event *event = cpu_hw_evt->events[lidx];
 714
 715                 /* Skip if invalid event or user did not request a sampling */
 716                 if (!event || !is_sampling_event(event))
 717                         continue;
 718
 719                 info = &pmu_ctr_list[lidx];
 720                 /* Do a sanity check */
 721                 if (!info || info->type != SBI_PMU_CTR_TYPE_HW)
 722                         continue;
 723
 724                 /* compute hardware counter index */
 725                 hidx = info->csr - CSR_CYCLE;
 726                 /* check if the corresponding bit is set in sscountovf */
 727                 if (!(overflow & (1 << hidx)))
 728                         continue;
 729
 730                 /*
 731                  * Keep a track of overflowed counters so that they can be started
 732                  * with updated initial value.
 733                  */
 734                 overflowed_ctrs |= 1 << lidx;
 735                 hw_evt = &event->hw;
 736                 riscv_pmu_event_update(event);
 737                 perf_sample_data_init(&data, 0, hw_evt->last_period);
 738                 if (riscv_pmu_event_set_period(event)) {
 739                         /*
 740                          * Unlike other ISAs, RISC-V don't have to disable interrupts
 741                          * to avoid throttling here. As per the specification, the
 742                          * interrupt remains disabled until the OF bit is set.
 743                          * Interrupts are enabled again only during the start.
 744                          * TODO: We will need to stop the guest counters once
 745                          * virtualization support is added.
 746                          */
 747                         perf_event_overflow(event, &data, regs);
 748                 }
 749         }
 750
 751         pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
 752         perf_sample_event_took(sched_clock() - start_clock);
 753
 754         return IRQ_HANDLED;
 755 }
 756
 757 static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
 758 {
 759         struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
 760         struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
 761
 762         /*
 763          * We keep enabling userspace access to CYCLE, TIME and INSTRET via the
 764          * legacy option but that will be removed in the future.
 765          */
 766         if (sysctl_perf_user_access == SYSCTL_LEGACY)
 767                 csr_write(CSR_SCOUNTEREN, 0x7);
 768         else
 769                 csr_write(CSR_SCOUNTEREN, 0x2);
 770
 771         /* Stop all the counters so that they can be enabled from perf */
 772         pmu_sbi_stop_all(pmu);
 773
 774         if (riscv_pmu_use_irq) {
 775                 cpu_hw_evt->irq = riscv_pmu_irq;
 776                 csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
 777                 csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
 778                 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
 779         }
 780
 781         return 0;
 782 }
 783
 784 static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
 785 {
 786         if (riscv_pmu_use_irq) {
 787                 disable_percpu_irq(riscv_pmu_irq);
 788                 csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
 789         }
 790
 791         /* Disable all counters access for user mode now */
 792         csr_write(CSR_SCOUNTEREN, 0x0);
 793
 794         return 0;
 795 }
 796
 797 static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev)
 798 {
 799         int ret;
 800         struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
 801         struct irq_domain *domain = NULL;
 802
 803         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
 804                 riscv_pmu_irq_num = RV_IRQ_PMU;
 805                 riscv_pmu_use_irq = true;
 806         } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
 807                    riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
 808                    riscv_cached_marchid(0) == 0 &&
 809                    riscv_cached_mimpid(0) == 0) {
 810                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
 811                 riscv_pmu_use_irq = true;
 812         }
 813
 814         if (!riscv_pmu_use_irq)
 815                 return -EOPNOTSUPP;
 816
 817         domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(),
 818                                           DOMAIN_BUS_ANY);
 819         if (!domain) {
 820                 pr_err("Failed to find INTC IRQ root domain\n");
 821                 return -ENODEV;
 822         }
 823
 824         riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num);
 825         if (!riscv_pmu_irq) {
 826                 pr_err("Failed to map PMU interrupt for node\n");
 827                 return -ENODEV;
 828         }
 829
 830         ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
 831         if (ret) {
 832                 pr_err("registering percpu irq failed [%d]\n", ret);
 833                 return ret;
 834         }
 835
 836         return 0;
 837 }
 838
 839 #ifdef CONFIG_CPU_PM
 840 static int riscv_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
 841                                 void *v)
 842 {
 843         struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb);
 844         struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
 845         int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS);
 846         struct perf_event *event;
 847         int idx;
 848
 849         if (!enabled)
 850                 return NOTIFY_OK;
 851
 852         for (idx = 0; idx < RISCV_MAX_COUNTERS; idx++) {
 853                 event = cpuc->events[idx];
 854                 if (!event)
 855                         continue;
 856
 857                 switch (cmd) {
 858                 case CPU_PM_ENTER:
 859                         /*
 860                          * Stop and update the counter
 861                          */
 862                         riscv_pmu_stop(event, PERF_EF_UPDATE);
 863                         break;
 864                 case CPU_PM_EXIT:
 865                 case CPU_PM_ENTER_FAILED:
 866                         /*
 867                          * Restore and enable the counter.
 868                          */
 869                         riscv_pmu_start(event, PERF_EF_RELOAD);
 870                         break;
 871                 default:
 872                         break;
 873                 }
 874         }
 875
 876         return NOTIFY_OK;
 877 }
 878
 879 static int riscv_pm_pmu_register(struct riscv_pmu *pmu)
 880 {
 881         pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify;
 882         return cpu_pm_register_notifier(&pmu->riscv_pm_nb);
 883 }
 884
 885 static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu)
 886 {
 887         cpu_pm_unregister_notifier(&pmu->riscv_pm_nb);
 888 }
 889 #else
 890 static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; }
 891 static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { }
 892 #endif
 893
 894 static void riscv_pmu_destroy(struct riscv_pmu *pmu)
 895 {
 896         riscv_pm_pmu_unregister(pmu);
 897         cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
 898 }
 899
 900 static void pmu_sbi_event_init(struct perf_event *event)
 901 {
 902         /*
 903          * The permissions are set at event_init so that we do not depend
 904          * on the sysctl value that can change.
 905          */
 906         if (sysctl_perf_user_access == SYSCTL_NO_USER_ACCESS)
 907                 event->hw.flags |= PERF_EVENT_FLAG_NO_USER_ACCESS;
 908         else if (sysctl_perf_user_access == SYSCTL_USER_ACCESS)
 909                 event->hw.flags |= PERF_EVENT_FLAG_USER_ACCESS;
 910         else
 911                 event->hw.flags |= PERF_EVENT_FLAG_LEGACY;
 912 }
 913
 914 static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struct *mm)
 915 {
 916         if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS)
 917                 return;
 918
 919         if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) {
 920                 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
 921                     event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) {
 922                         return;
 923                 }
 924         }
 925
 926         /*
 927          * The user mmapped the event to directly access it: this is where
 928          * we determine based on sysctl_perf_user_access if we grant userspace
 929          * the direct access to this event. That means that within the same
 930          * task, some events may be directly accessible and some other may not,
 931          * if the user changes the value of sysctl_perf_user_accesss in the
 932          * meantime.
 933          */
 934
 935         event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
 936
 937         /*
 938          * We must enable userspace access *before* advertising in the user page
 939          * that it is possible to do so to avoid any race.
 940          * And we must notify all cpus here because threads that currently run
 941          * on other cpus will try to directly access the counter too without
 942          * calling pmu_sbi_ctr_start.
 943          */
 944         if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS)
 945                 on_each_cpu_mask(mm_cpumask(mm),
 946                                  pmu_sbi_set_scounteren, (void *)event, 1);
 947 }
 948
 949 static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_struct *mm)
 950 {
 951         if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS)
 952                 return;
 953
 954         if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) {
 955                 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
 956                     event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) {
 957                         return;
 958                 }
 959         }
 960
 961         /*
 962          * Here we can directly remove user access since the user does not have
 963          * access to the user page anymore so we avoid the racy window where the
 964          * user could have read cap_user_rdpmc to true right before we disable
 965          * it.
 966          */
 967         event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
 968
 969         if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS)
 970                 on_each_cpu_mask(mm_cpumask(mm),
 971                                  pmu_sbi_reset_scounteren, (void *)event, 1);
 972 }
 973
 974 static void riscv_pmu_update_counter_access(void *info)
 975 {
 976         if (sysctl_perf_user_access == SYSCTL_LEGACY)
 977                 csr_write(CSR_SCOUNTEREN, 0x7);
 978         else
 979                 csr_write(CSR_SCOUNTEREN, 0x2);
 980 }
 981
 982 static int riscv_pmu_proc_user_access_handler(struct ctl_table *table,
 983                                               int write, void *buffer,
 984                                               size_t *lenp, loff_t *ppos)
 985 {
 986         int prev = sysctl_perf_user_access;
 987         int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
 988
 989         /*
 990          * Test against the previous value since we clear SCOUNTEREN when
 991          * sysctl_perf_user_access is set to SYSCTL_USER_ACCESS, but we should
 992          * not do that if that was already the case.
 993          */
 994         if (ret || !write || prev == sysctl_perf_user_access)
 995                 return ret;
 996
 997         on_each_cpu(riscv_pmu_update_counter_access, NULL, 1);
 998
 999         return 0;
1000 }
1001
1002 static struct ctl_table sbi_pmu_sysctl_table[] = {
1003         {
1004                 .procname       = "perf_user_access",
1005                 .data           = &sysctl_perf_user_access,
1006                 .maxlen         = sizeof(unsigned int),
1007                 .mode           = 0644,
1008                 .proc_handler   = riscv_pmu_proc_user_access_handler,
1009                 .extra1         = SYSCTL_ZERO,
1010                 .extra2         = SYSCTL_TWO,
1011         },
1012         { }
1013 };
1014
1015 static int pmu_sbi_device_probe(struct platform_device *pdev)
1016 {
1017         struct riscv_pmu *pmu = NULL;
1018         int ret = -ENODEV;
1019         int num_counters;
1020
1021         pr_info("SBI PMU extension is available\n");
1022         pmu = riscv_pmu_alloc();
1023         if (!pmu)
1024                 return -ENOMEM;
1025
1026         num_counters = pmu_sbi_find_num_ctrs();
1027         if (num_counters < 0) {
1028                 pr_err("SBI PMU extension doesn't provide any counters\n");
1029                 goto out_free;
1030         }
1031
1032         /* It is possible to get from SBI more than max number of counters */
1033         if (num_counters > RISCV_MAX_COUNTERS) {
1034                 num_counters = RISCV_MAX_COUNTERS;
1035                 pr_info("SBI returned more than maximum number of counters. Limiting the number of counters to %d\n", num_counters);
1036         }
1037
1038         /* cache all the information about counters now */
1039         if (pmu_sbi_get_ctrinfo(num_counters, &cmask))
1040                 goto out_free;
1041
1042         ret = pmu_sbi_setup_irqs(pmu, pdev);
1043         if (ret < 0) {
1044                 pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n");
1045                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1046                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
1047         }
1048
1049         pmu->pmu.attr_groups = riscv_pmu_attr_groups;
1050         pmu->cmask = cmask;
1051         pmu->ctr_start = pmu_sbi_ctr_start;
1052         pmu->ctr_stop = pmu_sbi_ctr_stop;
1053         pmu->event_map = pmu_sbi_event_map;
1054         pmu->ctr_get_idx = pmu_sbi_ctr_get_idx;
1055         pmu->ctr_get_width = pmu_sbi_ctr_get_width;
1056         pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
1057         pmu->ctr_read = pmu_sbi_ctr_read;
1058         pmu->event_init = pmu_sbi_event_init;
1059         pmu->event_mapped = pmu_sbi_event_mapped;
1060         pmu->event_unmapped = pmu_sbi_event_unmapped;
1061         pmu->csr_index = pmu_sbi_csr_index;
1062
1063         ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1064         if (ret)
1065                 return ret;
1066
1067         ret = riscv_pm_pmu_register(pmu);
1068         if (ret)
1069                 goto out_unregister;
1070
1071         ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
1072         if (ret)
1073                 goto out_unregister;
1074
1075         register_sysctl("kernel", sbi_pmu_sysctl_table);
1076
1077         return 0;
1078
1079 out_unregister:
1080         riscv_pmu_destroy(pmu);
1081
1082 out_free:
1083         kfree(pmu);
1084         return ret;
1085 }
1086
1087 static struct platform_driver pmu_sbi_driver = {
1088         .probe          = pmu_sbi_device_probe,
1089         .driver         = {
1090                 .name   = RISCV_PMU_SBI_PDEV_NAME,
1091         },
1092 };
1093
1094 static int __init pmu_sbi_devinit(void)
1095 {
1096         int ret;
1097         struct platform_device *pdev;
1098
1099         if (sbi_spec_version < sbi_mk_version(0, 3) ||
1100             !sbi_probe_extension(SBI_EXT_PMU)) {
1101                 return 0;
1102         }
1103
1104         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
1105                                       "perf/riscv/pmu:starting",
1106                                       pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
1107         if (ret) {
1108                 pr_err("CPU hotplug notifier could not be registered: %d\n",
1109                        ret);
1110                 return ret;
1111         }
1112
1113         ret = platform_driver_register(&pmu_sbi_driver);
1114         if (ret)
1115                 return ret;
1116
1117         pdev = platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NULL, 0);
1118         if (IS_ERR(pdev)) {
1119                 platform_driver_unregister(&pmu_sbi_driver);
1120                 return PTR_ERR(pdev);
1121         }
1122
1123         /* Notify legacy implementation that SBI pmu is available*/
1124         riscv_pmu_legacy_skip_init();
1125
1126         return ret;
1127 }
1128 device_initcall(pmu_sbi_devinit)