drivers/perf/riscv_pmu_legacy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * RISC-V performance counter support.
   4  *
   5  * Copyright (C) 2021 Western Digital Corporation or its affiliates.
   6  *
   7  * This implementation is based on old RISC-V perf and ARM perf event code
   8  * which are in turn based on sparc64 and x86 code.
   9  */
  10
  11 #include <linux/mod_devicetable.h>
  12 #include <linux/perf/riscv_pmu.h>
  13 #include <linux/platform_device.h>
  14
  15 #define RISCV_PMU_LEGACY_CYCLE          0
  16 #define RISCV_PMU_LEGACY_INSTRET        2
  17
  18 static bool pmu_init_done;
  19
  20 static int pmu_legacy_ctr_get_idx(struct perf_event *event)
  21 {
  22         struct perf_event_attr *attr = &event->attr;
  23
  24         if (event->attr.type != PERF_TYPE_HARDWARE)
  25                 return -EOPNOTSUPP;
  26         if (attr->config == PERF_COUNT_HW_CPU_CYCLES)
  27                 return RISCV_PMU_LEGACY_CYCLE;
  28         else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)
  29                 return RISCV_PMU_LEGACY_INSTRET;
  30         else
  31                 return -EOPNOTSUPP;
  32 }
  33
  34 /* For legacy config & counter index are same */
  35 static int pmu_legacy_event_map(struct perf_event *event, u64 *config)
  36 {
  37         return pmu_legacy_ctr_get_idx(event);
  38 }
  39
  40 static u64 pmu_legacy_read_ctr(struct perf_event *event)
  41 {
  42         struct hw_perf_event *hwc = &event->hw;
  43         int idx = hwc->idx;
  44         u64 val;
  45
  46         if (idx == RISCV_PMU_LEGACY_CYCLE) {
  47                 val = riscv_pmu_ctr_read_csr(CSR_CYCLE);
  48                 if (IS_ENABLED(CONFIG_32BIT))
  49                         val = (u64)riscv_pmu_ctr_read_csr(CSR_CYCLEH) << 32 | val;
  50         } else if (idx == RISCV_PMU_LEGACY_INSTRET) {
  51                 val = riscv_pmu_ctr_read_csr(CSR_INSTRET);
  52                 if (IS_ENABLED(CONFIG_32BIT))
  53                         val = ((u64)riscv_pmu_ctr_read_csr(CSR_INSTRETH)) << 32 | val;
  54         } else
  55                 return 0;
  56
  57         return val;
  58 }
  59
  60 static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival)
  61 {
  62         struct hw_perf_event *hwc = &event->hw;
  63         u64 initial_val = pmu_legacy_read_ctr(event);
  64
  65         /**
  66          * The legacy method doesn't really have a start/stop method.
  67          * It also can not update the counter with a initial value.
  68          * But we still need to set the prev_count so that read() can compute
  69          * the delta. Just use the current counter value to set the prev_count.
  70          */
  71         local64_set(&hwc->prev_count, initial_val);
  72 }
  73
  74 static uint8_t pmu_legacy_csr_index(struct perf_event *event)
  75 {
  76         return event->hw.idx;
  77 }
  78
  79 static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm)
  80 {
  81         if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
  82             event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
  83                 return;
  84
  85         event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
  86 }
  87
  88 static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm)
  89 {
  90         if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
  91             event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
  92                 return;
  93
  94         event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
  95 }
  96
  97 /*
  98  * This is just a simple implementation to allow legacy implementations
  99  * compatible with new RISC-V PMU driver framework.
 100  * This driver only allows reading two counters i.e CYCLE & INSTRET.
 101  * However, it can not start or stop the counter. Thus, it is not very useful
 102  * will be removed in future.
 103  */
 104 static void pmu_legacy_init(struct riscv_pmu *pmu)
 105 {
 106         pr_info("Legacy PMU implementation is available\n");
 107
 108         pmu->cmask = BIT(RISCV_PMU_LEGACY_CYCLE) |
 109                 BIT(RISCV_PMU_LEGACY_INSTRET);
 110         pmu->ctr_start = pmu_legacy_ctr_start;
 111         pmu->ctr_stop = NULL;
 112         pmu->event_map = pmu_legacy_event_map;
 113         pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;
 114         pmu->ctr_get_width = NULL;
 115         pmu->ctr_clear_idx = NULL;
 116         pmu->ctr_read = pmu_legacy_read_ctr;
 117         pmu->event_mapped = pmu_legacy_event_mapped;
 118         pmu->event_unmapped = pmu_legacy_event_unmapped;
 119         pmu->csr_index = pmu_legacy_csr_index;
 120
 121         perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
 122 }
 123
 124 static int pmu_legacy_device_probe(struct platform_device *pdev)
 125 {
 126         struct riscv_pmu *pmu = NULL;
 127
 128         pmu = riscv_pmu_alloc();
 129         if (!pmu)
 130                 return -ENOMEM;
 131         pmu_legacy_init(pmu);
 132
 133         return 0;
 134 }
 135
 136 static struct platform_driver pmu_legacy_driver = {
 137         .probe          = pmu_legacy_device_probe,
 138         .driver         = {
 139                 .name   = RISCV_PMU_LEGACY_PDEV_NAME,
 140         },
 141 };
 142
 143 static int __init riscv_pmu_legacy_devinit(void)
 144 {
 145         int ret;
 146         struct platform_device *pdev;
 147
 148         if (likely(pmu_init_done))
 149                 return 0;
 150
 151         ret = platform_driver_register(&pmu_legacy_driver);
 152         if (ret)
 153                 return ret;
 154
 155         pdev = platform_device_register_simple(RISCV_PMU_LEGACY_PDEV_NAME, -1, NULL, 0);
 156         if (IS_ERR(pdev)) {
 157                 platform_driver_unregister(&pmu_legacy_driver);
 158                 return PTR_ERR(pdev);
 159         }
 160
 161         return ret;
 162 }
 163 late_initcall(riscv_pmu_legacy_devinit);
 164
 165 void riscv_pmu_legacy_skip_init(void)
 166 {
 167         pmu_init_done = true;
 168 }