1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
7 * This implementation is based on old RISC-V perf and ARM perf event code
8 * which are in turn based on sparc64 and x86 code.
11 #include <linux/cpumask.h>
12 #include <linux/irq.h>
13 #include <linux/irqdesc.h>
14 #include <linux/perf/riscv_pmu.h>
15 #include <linux/printk.h>
16 #include <linux/smp.h>
20 static unsigned long csr_read_num(int csr_num)
22 #define switchcase_csr_read(__csr_num, __val) {\
24 __val = csr_read(__csr_num); \
26 #define switchcase_csr_read_2(__csr_num, __val) {\
27 switchcase_csr_read(__csr_num + 0, __val) \
28 switchcase_csr_read(__csr_num + 1, __val)}
29 #define switchcase_csr_read_4(__csr_num, __val) {\
30 switchcase_csr_read_2(__csr_num + 0, __val) \
31 switchcase_csr_read_2(__csr_num + 2, __val)}
32 #define switchcase_csr_read_8(__csr_num, __val) {\
33 switchcase_csr_read_4(__csr_num + 0, __val) \
34 switchcase_csr_read_4(__csr_num + 4, __val)}
35 #define switchcase_csr_read_16(__csr_num, __val) {\
36 switchcase_csr_read_8(__csr_num + 0, __val) \
37 switchcase_csr_read_8(__csr_num + 8, __val)}
38 #define switchcase_csr_read_32(__csr_num, __val) {\
39 switchcase_csr_read_16(__csr_num + 0, __val) \
40 switchcase_csr_read_16(__csr_num + 16, __val)}
42 unsigned long ret = 0;
45 switchcase_csr_read_32(CSR_CYCLE, ret)
46 switchcase_csr_read_32(CSR_CYCLEH, ret)
52 #undef switchcase_csr_read_32
53 #undef switchcase_csr_read_16
54 #undef switchcase_csr_read_8
55 #undef switchcase_csr_read_4
56 #undef switchcase_csr_read_2
57 #undef switchcase_csr_read
61 * Read the CSR of a corresponding counter.
63 unsigned long riscv_pmu_ctr_read_csr(unsigned long csr)
65 if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H ||
66 (csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) {
67 pr_err("Invalid performance counter csr %lx\n", csr);
71 return csr_read_num(csr);
74 u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)
77 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
78 struct hw_perf_event *hwc = &event->hw;
80 if (!rvpmu->ctr_get_width)
82 * If the pmu driver doesn't support counter width, set it to default
83 * maximum allowed by the specification.
88 /* Handle init case where idx is not initialized yet */
89 cwidth = rvpmu->ctr_get_width(0);
91 cwidth = rvpmu->ctr_get_width(hwc->idx);
94 return GENMASK_ULL(cwidth, 0);
97 u64 riscv_pmu_event_update(struct perf_event *event)
99 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
100 struct hw_perf_event *hwc = &event->hw;
101 u64 prev_raw_count, new_raw_count;
105 if (!rvpmu->ctr_read)
108 cmask = riscv_pmu_ctr_get_width_mask(event);
111 prev_raw_count = local64_read(&hwc->prev_count);
112 new_raw_count = rvpmu->ctr_read(event);
113 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
115 } while (oldval != prev_raw_count);
117 delta = (new_raw_count - prev_raw_count) & cmask;
118 local64_add(delta, &event->count);
119 local64_sub(delta, &hwc->period_left);
124 void riscv_pmu_stop(struct perf_event *event, int flags)
126 struct hw_perf_event *hwc = &event->hw;
127 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
129 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
131 if (!(hwc->state & PERF_HES_STOPPED)) {
132 if (rvpmu->ctr_stop) {
133 rvpmu->ctr_stop(event, 0);
134 hwc->state |= PERF_HES_STOPPED;
136 riscv_pmu_event_update(event);
137 hwc->state |= PERF_HES_UPTODATE;
141 int riscv_pmu_event_set_period(struct perf_event *event)
143 struct hw_perf_event *hwc = &event->hw;
144 s64 left = local64_read(&hwc->period_left);
145 s64 period = hwc->sample_period;
147 uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);
149 if (unlikely(left <= -period)) {
151 local64_set(&hwc->period_left, left);
152 hwc->last_period = period;
156 if (unlikely(left <= 0)) {
158 local64_set(&hwc->period_left, left);
159 hwc->last_period = period;
164 * Limit the maximum period to prevent the counter value
165 * from overtaking the one we are about to program. In
166 * effect we are reducing max_period to account for
167 * interrupt latency (and we are being very conservative).
169 if (left > (max_period >> 1))
170 left = (max_period >> 1);
172 local64_set(&hwc->prev_count, (u64)-left);
177 void riscv_pmu_start(struct perf_event *event, int flags)
179 struct hw_perf_event *hwc = &event->hw;
180 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
181 uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);
184 if (flags & PERF_EF_RELOAD)
185 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
188 riscv_pmu_event_set_period(event);
189 init_val = local64_read(&hwc->prev_count) & max_period;
190 rvpmu->ctr_start(event, init_val);
191 perf_event_update_userpage(event);
194 static int riscv_pmu_add(struct perf_event *event, int flags)
196 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
197 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
198 struct hw_perf_event *hwc = &event->hw;
201 idx = rvpmu->ctr_get_idx(event);
206 cpuc->events[idx] = event;
208 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
209 if (flags & PERF_EF_START)
210 riscv_pmu_start(event, PERF_EF_RELOAD);
212 /* Propagate our changes to the userspace mapping. */
213 perf_event_update_userpage(event);
218 static void riscv_pmu_del(struct perf_event *event, int flags)
220 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
221 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
222 struct hw_perf_event *hwc = &event->hw;
224 riscv_pmu_stop(event, PERF_EF_UPDATE);
225 cpuc->events[hwc->idx] = NULL;
226 /* The firmware need to reset the counter mapping */
228 rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);
230 if (rvpmu->ctr_clear_idx)
231 rvpmu->ctr_clear_idx(event);
232 perf_event_update_userpage(event);
236 static void riscv_pmu_read(struct perf_event *event)
238 riscv_pmu_event_update(event);
241 static int riscv_pmu_event_init(struct perf_event *event)
243 struct hw_perf_event *hwc = &event->hw;
244 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
246 u64 event_config = 0;
250 mapped_event = rvpmu->event_map(event, &event_config);
251 if (mapped_event < 0) {
252 pr_debug("event %x:%llx not supported\n", event->attr.type,
258 * idx is set to -1 because the index of a general event should not be
259 * decided until binding to some counter in pmu->add().
260 * config will contain the information about counter CSR
261 * the idx will contain the counter index
263 hwc->config = event_config;
265 hwc->event_base = mapped_event;
267 if (!is_sampling_event(event)) {
269 * For non-sampling runs, limit the sample_period to half
270 * of the counter width. That way, the new counter value
271 * is far less likely to overtake the previous one unless
272 * you have some serious IRQ latency issues.
274 cmask = riscv_pmu_ctr_get_width_mask(event);
275 hwc->sample_period = cmask >> 1;
276 hwc->last_period = hwc->sample_period;
277 local64_set(&hwc->period_left, hwc->sample_period);
283 struct riscv_pmu *riscv_pmu_alloc(void)
285 struct riscv_pmu *pmu;
287 struct cpu_hw_events *cpuc;
289 pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
293 pmu->hw_events = alloc_percpu_gfp(struct cpu_hw_events, GFP_KERNEL);
294 if (!pmu->hw_events) {
295 pr_info("failed to allocate per-cpu PMU data.\n");
299 for_each_possible_cpu(cpuid) {
300 cpuc = per_cpu_ptr(pmu->hw_events, cpuid);
302 for (i = 0; i < RISCV_MAX_COUNTERS; i++)
303 cpuc->events[i] = NULL;
305 pmu->pmu = (struct pmu) {
306 .event_init = riscv_pmu_event_init,
307 .add = riscv_pmu_add,
308 .del = riscv_pmu_del,
309 .start = riscv_pmu_start,
310 .stop = riscv_pmu_stop,
311 .read = riscv_pmu_read,