drivers/perf/riscv_pmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * RISC-V performance counter support.
   4  *
   5  * Copyright (C) 2021 Western Digital Corporation or its affiliates.
   6  *
   7  * This implementation is based on old RISC-V perf and ARM perf event code
   8  * which are in turn based on sparc64 and x86 code.
   9  */
  10
  11 #include <linux/cpumask.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqdesc.h>
  14 #include <linux/perf/riscv_pmu.h>
  15 #include <linux/printk.h>
  16 #include <linux/smp.h>
  17 #include <linux/sched_clock.h>
  18
  19 #include <asm/sbi.h>
  20
  21 static bool riscv_perf_user_access(struct perf_event *event)
  22 {
  23         return ((event->attr.type == PERF_TYPE_HARDWARE) ||
  24                 (event->attr.type == PERF_TYPE_HW_CACHE) ||
  25                 (event->attr.type == PERF_TYPE_RAW)) &&
  26                 !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
  27 }
  28
  29 void arch_perf_update_userpage(struct perf_event *event,
  30                                struct perf_event_mmap_page *userpg, u64 now)
  31 {
  32         struct clock_read_data *rd;
  33         unsigned int seq;
  34         u64 ns;
  35
  36         userpg->cap_user_time = 0;
  37         userpg->cap_user_time_zero = 0;
  38         userpg->cap_user_time_short = 0;
  39         userpg->cap_user_rdpmc = riscv_perf_user_access(event);
  40
  41         userpg->pmc_width = 64;
  42
  43         do {
  44                 rd = sched_clock_read_begin(&seq);
  45
  46                 userpg->time_mult = rd->mult;
  47                 userpg->time_shift = rd->shift;
  48                 userpg->time_zero = rd->epoch_ns;
  49                 userpg->time_cycles = rd->epoch_cyc;
  50                 userpg->time_mask = rd->sched_clock_mask;
  51
  52                 /*
  53                  * Subtract the cycle base, such that software that
  54                  * doesn't know about cap_user_time_short still 'works'
  55                  * assuming no wraps.
  56                  */
  57                 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
  58                 userpg->time_zero -= ns;
  59
  60         } while (sched_clock_read_retry(seq));
  61
  62         userpg->time_offset = userpg->time_zero - now;
  63
  64         /*
  65          * time_shift is not expected to be greater than 31 due to
  66          * the original published conversion algorithm shifting a
  67          * 32-bit value (now specifies a 64-bit value) - refer
  68          * perf_event_mmap_page documentation in perf_event.h.
  69          */
  70         if (userpg->time_shift == 32) {
  71                 userpg->time_shift = 31;
  72                 userpg->time_mult >>= 1;
  73         }
  74
  75         /*
  76          * Internal timekeeping for enabled/running/stopped times
  77          * is always computed with the sched_clock.
  78          */
  79         userpg->cap_user_time = 1;
  80         userpg->cap_user_time_zero = 1;
  81         userpg->cap_user_time_short = 1;
  82 }
  83
  84 static unsigned long csr_read_num(int csr_num)
  85 {
  86 #define switchcase_csr_read(__csr_num, __val)           {\
  87         case __csr_num:                                 \
  88                 __val = csr_read(__csr_num);            \
  89                 break; }
  90 #define switchcase_csr_read_2(__csr_num, __val)         {\
  91         switchcase_csr_read(__csr_num + 0, __val)        \
  92         switchcase_csr_read(__csr_num + 1, __val)}
  93 #define switchcase_csr_read_4(__csr_num, __val)         {\
  94         switchcase_csr_read_2(__csr_num + 0, __val)      \
  95         switchcase_csr_read_2(__csr_num + 2, __val)}
  96 #define switchcase_csr_read_8(__csr_num, __val)         {\
  97         switchcase_csr_read_4(__csr_num + 0, __val)      \
  98         switchcase_csr_read_4(__csr_num + 4, __val)}
  99 #define switchcase_csr_read_16(__csr_num, __val)        {\
 100         switchcase_csr_read_8(__csr_num + 0, __val)      \
 101         switchcase_csr_read_8(__csr_num + 8, __val)}
 102 #define switchcase_csr_read_32(__csr_num, __val)        {\
 103         switchcase_csr_read_16(__csr_num + 0, __val)     \
 104         switchcase_csr_read_16(__csr_num + 16, __val)}
 105
 106         unsigned long ret = 0;
 107
 108         switch (csr_num) {
 109         switchcase_csr_read_32(CSR_CYCLE, ret)
 110         switchcase_csr_read_32(CSR_CYCLEH, ret)
 111         default :
 112                 break;
 113         }
 114
 115         return ret;
 116 #undef switchcase_csr_read_32
 117 #undef switchcase_csr_read_16
 118 #undef switchcase_csr_read_8
 119 #undef switchcase_csr_read_4
 120 #undef switchcase_csr_read_2
 121 #undef switchcase_csr_read
 122 }
 123
 124 /*
 125  * Read the CSR of a corresponding counter.
 126  */
 127 unsigned long riscv_pmu_ctr_read_csr(unsigned long csr)
 128 {
 129         if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H ||
 130            (csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) {
 131                 pr_err("Invalid performance counter csr %lx\n", csr);
 132                 return -EINVAL;
 133         }
 134
 135         return csr_read_num(csr);
 136 }
 137
 138 u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)
 139 {
 140         int cwidth;
 141         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 142         struct hw_perf_event *hwc = &event->hw;
 143
 144         if (!rvpmu->ctr_get_width)
 145         /**
 146          * If the pmu driver doesn't support counter width, set it to default
 147          * maximum allowed by the specification.
 148          */
 149                 cwidth = 63;
 150         else {
 151                 if (hwc->idx == -1)
 152                         /* Handle init case where idx is not initialized yet */
 153                         cwidth = rvpmu->ctr_get_width(0);
 154                 else
 155                         cwidth = rvpmu->ctr_get_width(hwc->idx);
 156         }
 157
 158         return GENMASK_ULL(cwidth, 0);
 159 }
 160
 161 u64 riscv_pmu_event_update(struct perf_event *event)
 162 {
 163         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 164         struct hw_perf_event *hwc = &event->hw;
 165         u64 prev_raw_count, new_raw_count;
 166         unsigned long cmask;
 167         u64 oldval, delta;
 168
 169         if (!rvpmu->ctr_read)
 170                 return 0;
 171
 172         cmask = riscv_pmu_ctr_get_width_mask(event);
 173
 174         do {
 175                 prev_raw_count = local64_read(&hwc->prev_count);
 176                 new_raw_count = rvpmu->ctr_read(event);
 177                 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 178                                          new_raw_count);
 179         } while (oldval != prev_raw_count);
 180
 181         delta = (new_raw_count - prev_raw_count) & cmask;
 182         local64_add(delta, &event->count);
 183         local64_sub(delta, &hwc->period_left);
 184
 185         return delta;
 186 }
 187
 188 void riscv_pmu_stop(struct perf_event *event, int flags)
 189 {
 190         struct hw_perf_event *hwc = &event->hw;
 191         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 192
 193         WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 194
 195         if (!(hwc->state & PERF_HES_STOPPED)) {
 196                 if (rvpmu->ctr_stop) {
 197                         rvpmu->ctr_stop(event, 0);
 198                         hwc->state |= PERF_HES_STOPPED;
 199                 }
 200                 riscv_pmu_event_update(event);
 201                 hwc->state |= PERF_HES_UPTODATE;
 202         }
 203 }
 204
 205 int riscv_pmu_event_set_period(struct perf_event *event)
 206 {
 207         struct hw_perf_event *hwc = &event->hw;
 208         s64 left = local64_read(&hwc->period_left);
 209         s64 period = hwc->sample_period;
 210         int overflow = 0;
 211         uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);
 212
 213         if (unlikely(left <= -period)) {
 214                 left = period;
 215                 local64_set(&hwc->period_left, left);
 216                 hwc->last_period = period;
 217                 overflow = 1;
 218         }
 219
 220         if (unlikely(left <= 0)) {
 221                 left += period;
 222                 local64_set(&hwc->period_left, left);
 223                 hwc->last_period = period;
 224                 overflow = 1;
 225         }
 226
 227         /*
 228          * Limit the maximum period to prevent the counter value
 229          * from overtaking the one we are about to program. In
 230          * effect we are reducing max_period to account for
 231          * interrupt latency (and we are being very conservative).
 232          */
 233         if (left > (max_period >> 1))
 234                 left = (max_period >> 1);
 235
 236         local64_set(&hwc->prev_count, (u64)-left);
 237
 238         perf_event_update_userpage(event);
 239
 240         return overflow;
 241 }
 242
 243 void riscv_pmu_start(struct perf_event *event, int flags)
 244 {
 245         struct hw_perf_event *hwc = &event->hw;
 246         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 247         uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);
 248         u64 init_val;
 249
 250         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 251                 return;
 252
 253         if (flags & PERF_EF_RELOAD)
 254                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 255
 256         hwc->state = 0;
 257         riscv_pmu_event_set_period(event);
 258         init_val = local64_read(&hwc->prev_count) & max_period;
 259         rvpmu->ctr_start(event, init_val);
 260         perf_event_update_userpage(event);
 261 }
 262
 263 static int riscv_pmu_add(struct perf_event *event, int flags)
 264 {
 265         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 266         struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
 267         struct hw_perf_event *hwc = &event->hw;
 268         int idx;
 269
 270         idx = rvpmu->ctr_get_idx(event);
 271         if (idx < 0)
 272                 return idx;
 273
 274         hwc->idx = idx;
 275         cpuc->events[idx] = event;
 276         cpuc->n_events++;
 277         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 278         if (flags & PERF_EF_START)
 279                 riscv_pmu_start(event, PERF_EF_RELOAD);
 280
 281         /* Propagate our changes to the userspace mapping. */
 282         perf_event_update_userpage(event);
 283
 284         return 0;
 285 }
 286
 287 static void riscv_pmu_del(struct perf_event *event, int flags)
 288 {
 289         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 290         struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
 291         struct hw_perf_event *hwc = &event->hw;
 292
 293         riscv_pmu_stop(event, PERF_EF_UPDATE);
 294         cpuc->events[hwc->idx] = NULL;
 295         /* The firmware need to reset the counter mapping */
 296         if (rvpmu->ctr_stop)
 297                 rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);
 298         cpuc->n_events--;
 299         if (rvpmu->ctr_clear_idx)
 300                 rvpmu->ctr_clear_idx(event);
 301         perf_event_update_userpage(event);
 302         hwc->idx = -1;
 303 }
 304
 305 static void riscv_pmu_read(struct perf_event *event)
 306 {
 307         riscv_pmu_event_update(event);
 308 }
 309
 310 static int riscv_pmu_event_init(struct perf_event *event)
 311 {
 312         struct hw_perf_event *hwc = &event->hw;
 313         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 314         int mapped_event;
 315         u64 event_config = 0;
 316         uint64_t cmask;
 317
 318         hwc->flags = 0;
 319         mapped_event = rvpmu->event_map(event, &event_config);
 320         if (mapped_event < 0) {
 321                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 322                          event->attr.config);
 323                 return mapped_event;
 324         }
 325
 326         /*
 327          * idx is set to -1 because the index of a general event should not be
 328          * decided until binding to some counter in pmu->add().
 329          * config will contain the information about counter CSR
 330          * the idx will contain the counter index
 331          */
 332         hwc->config = event_config;
 333         hwc->idx = -1;
 334         hwc->event_base = mapped_event;
 335
 336         if (rvpmu->event_init)
 337                 rvpmu->event_init(event);
 338
 339         if (!is_sampling_event(event)) {
 340                 /*
 341                  * For non-sampling runs, limit the sample_period to half
 342                  * of the counter width. That way, the new counter value
 343                  * is far less likely to overtake the previous one unless
 344                  * you have some serious IRQ latency issues.
 345                  */
 346                 cmask = riscv_pmu_ctr_get_width_mask(event);
 347                 hwc->sample_period  =  cmask >> 1;
 348                 hwc->last_period    = hwc->sample_period;
 349                 local64_set(&hwc->period_left, hwc->sample_period);
 350         }
 351
 352         return 0;
 353 }
 354
 355 static int riscv_pmu_event_idx(struct perf_event *event)
 356 {
 357         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 358
 359         if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
 360                 return 0;
 361
 362         if (rvpmu->csr_index)
 363                 return rvpmu->csr_index(event) + 1;
 364
 365         return 0;
 366 }
 367
 368 static void riscv_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
 369 {
 370         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 371
 372         if (rvpmu->event_mapped) {
 373                 rvpmu->event_mapped(event, mm);
 374                 perf_event_update_userpage(event);
 375         }
 376 }
 377
 378 static void riscv_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
 379 {
 380         struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
 381
 382         if (rvpmu->event_unmapped) {
 383                 rvpmu->event_unmapped(event, mm);
 384                 perf_event_update_userpage(event);
 385         }
 386 }
 387
 388 struct riscv_pmu *riscv_pmu_alloc(void)
 389 {
 390         struct riscv_pmu *pmu;
 391         int cpuid, i;
 392         struct cpu_hw_events *cpuc;
 393
 394         pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
 395         if (!pmu)
 396                 goto out;
 397
 398         pmu->hw_events = alloc_percpu_gfp(struct cpu_hw_events, GFP_KERNEL);
 399         if (!pmu->hw_events) {
 400                 pr_info("failed to allocate per-cpu PMU data.\n");
 401                 goto out_free_pmu;
 402         }
 403
 404         for_each_possible_cpu(cpuid) {
 405                 cpuc = per_cpu_ptr(pmu->hw_events, cpuid);
 406                 cpuc->n_events = 0;
 407                 for (i = 0; i < RISCV_MAX_COUNTERS; i++)
 408                         cpuc->events[i] = NULL;
 409         }
 410         pmu->pmu = (struct pmu) {
 411                 .event_init     = riscv_pmu_event_init,
 412                 .event_mapped   = riscv_pmu_event_mapped,
 413                 .event_unmapped = riscv_pmu_event_unmapped,
 414                 .event_idx      = riscv_pmu_event_idx,
 415                 .add            = riscv_pmu_add,
 416                 .del            = riscv_pmu_del,
 417                 .start          = riscv_pmu_start,
 418                 .stop           = riscv_pmu_stop,
 419                 .read           = riscv_pmu_read,
 420         };
 421
 422         return pmu;
 423
 424 out_free_pmu:
 425         kfree(pmu);
 426 out:
 427         return NULL;
 428 }