1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI probing code for ARM performance counters.
5 * Copyright (C) 2017 ARM Ltd.
8 #include <linux/acpi.h>
9 #include <linux/cpumask.h>
10 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <linux/irqdesc.h>
13 #include <linux/percpu.h>
14 #include <linux/perf/arm_pmu.h>
17 #include <asm/cputype.h>
19 static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
20 static DEFINE_PER_CPU(int, pmu_irqs);
22 static int arm_pmu_acpi_register_irq(int cpu)
24 struct acpi_madt_generic_interrupt *gicc;
27 gicc = acpi_cpu_get_madt_gicc(cpu);
29 gsi = gicc->performance_interrupt;
32 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
33 * have an interrupt. QEMU advertises this by using a GSI of zero,
34 * which is not known to be valid on any hardware despite being
35 * valid per the spec. Take the pragmatic approach and reject a
36 * GSI of zero for now.
41 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
42 trigger = ACPI_EDGE_SENSITIVE;
44 trigger = ACPI_LEVEL_SENSITIVE;
47 * Helpfully, the MADT GICC doesn't have a polarity flag for the
48 * "performance interrupt". Luckily, on compliant GICs the polarity is
49 * a fixed value in HW (for both SPIs and PPIs) that we cannot change
52 * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
53 * may not match the real polarity, but that should not matter.
55 * Other interrupt controllers are not supported with ACPI.
57 return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
60 static void arm_pmu_acpi_unregister_irq(int cpu)
62 struct acpi_madt_generic_interrupt *gicc;
65 gicc = acpi_cpu_get_madt_gicc(cpu);
67 gsi = gicc->performance_interrupt;
69 acpi_unregister_gsi(gsi);
72 #if IS_ENABLED(CONFIG_ARM_SPE_PMU)
73 static struct resource spe_resources[] = {
76 .flags = IORESOURCE_IRQ,
80 static struct platform_device spe_dev = {
81 .name = ARMV8_SPE_PDEV_NAME,
83 .resource = spe_resources,
84 .num_resources = ARRAY_SIZE(spe_resources)
88 * For lack of a better place, hook the normal PMU MADT walk
89 * and create a SPE device if we detect a recent MADT with
90 * a homogeneous PPI mapping.
92 static void arm_spe_acpi_register_device(void)
94 int cpu, hetid, irq, ret;
99 * Sanity check all the GICC tables for the same interrupt number.
100 * For now, we only support homogeneous ACPI/SPE machines.
102 for_each_possible_cpu(cpu) {
103 struct acpi_madt_generic_interrupt *gicc;
105 gicc = acpi_cpu_get_madt_gicc(cpu);
106 if (gicc->header.length < ACPI_MADT_GICC_SPE)
110 gsi = gicc->spe_interrupt;
113 hetid = find_acpi_cpu_topology_hetero_id(cpu);
115 } else if ((gsi != gicc->spe_interrupt) ||
116 (hetid != find_acpi_cpu_topology_hetero_id(cpu))) {
117 pr_warn("ACPI: SPE must be homogeneous\n");
122 irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
125 pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
129 spe_resources[0].start = irq;
130 ret = platform_device_register(&spe_dev);
132 pr_warn("ACPI: SPE: Unable to register device\n");
133 acpi_unregister_gsi(gsi);
137 static inline void arm_spe_acpi_register_device(void)
140 #endif /* CONFIG_ARM_SPE_PMU */
142 static int arm_pmu_acpi_parse_irqs(void)
144 int irq, cpu, irq_cpu, err;
146 for_each_possible_cpu(cpu) {
147 irq = arm_pmu_acpi_register_irq(cpu);
150 pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
153 } else if (irq == 0) {
154 pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
158 * Log and request the IRQ so the core arm_pmu code can manage
159 * it. We'll have to sanity-check IRQs later when we associate
160 * them with their PMUs.
162 per_cpu(pmu_irqs, cpu) = irq;
163 err = armpmu_request_irq(irq, cpu);
171 for_each_possible_cpu(cpu) {
172 irq = per_cpu(pmu_irqs, cpu);
176 arm_pmu_acpi_unregister_irq(cpu);
179 * Blat all copies of the IRQ so that we only unregister the
180 * corresponding GSI once (e.g. when we have PPIs).
182 for_each_possible_cpu(irq_cpu) {
183 if (per_cpu(pmu_irqs, irq_cpu) == irq)
184 per_cpu(pmu_irqs, irq_cpu) = 0;
191 static struct arm_pmu *arm_pmu_acpi_find_pmu(void)
193 unsigned long cpuid = read_cpuid_id();
197 for_each_possible_cpu(cpu) {
198 pmu = per_cpu(probed_pmus, cpu);
199 if (!pmu || pmu->acpi_cpuid != cpuid)
209 * Check whether the new IRQ is compatible with those already associated with
210 * the PMU (e.g. we don't have mismatched PPIs).
212 static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
214 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
220 for_each_cpu(cpu, &pmu->supported_cpus) {
221 int other_irq = per_cpu(hw_events->irq, cpu);
225 if (irq == other_irq)
227 if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
230 pr_warn("mismatched PPIs detected\n");
237 static void arm_pmu_acpi_associate_pmu_cpu(struct arm_pmu *pmu,
240 int irq = per_cpu(pmu_irqs, cpu);
242 per_cpu(probed_pmus, cpu) = pmu;
244 if (pmu_irq_matches(pmu, irq)) {
245 struct pmu_hw_events __percpu *hw_events;
246 hw_events = pmu->hw_events;
247 per_cpu(hw_events->irq, cpu) = irq;
250 cpumask_set_cpu(cpu, &pmu->supported_cpus);
254 * This must run before the common arm_pmu hotplug logic, so that we can
255 * associate a CPU and its interrupt before the common code tries to manage the
256 * affinity and so on.
258 * Note that hotplug events are serialized, so we cannot race with another CPU
259 * coming up. The perf core won't open events while a hotplug event is in
262 static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
266 /* If we've already probed this CPU, we have nothing to do */
267 if (per_cpu(probed_pmus, cpu))
270 pmu = arm_pmu_acpi_find_pmu();
272 pr_warn_ratelimited("Unable to associate CPU%d with a PMU\n",
277 arm_pmu_acpi_associate_pmu_cpu(pmu, cpu);
281 static void arm_pmu_acpi_probe_matching_cpus(struct arm_pmu *pmu,
286 for_each_online_cpu(cpu) {
287 unsigned long cpu_cpuid = per_cpu(cpu_data, cpu).reg_midr;
289 if (cpu_cpuid == cpuid)
290 arm_pmu_acpi_associate_pmu_cpu(pmu, cpu);
294 int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
300 ret = arm_pmu_acpi_parse_irqs();
304 ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_ACPI_STARTING,
305 "perf/arm/pmu_acpi:starting",
306 arm_pmu_acpi_cpu_starting, NULL);
311 * Initialise and register the set of PMUs which we know about right
312 * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
313 * could handle late hotplug, but this may lead to deadlock since we
314 * might try to register a hotplug notifier instance from within a
317 * There's also the problem of having access to the right init_fn,
318 * without tying this too deeply into the "real" PMU driver.
320 * For the moment, as with the platform/DT case, we need at least one
321 * of a PMU's CPUs to be online at probe time.
323 for_each_online_cpu(cpu) {
324 struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
328 /* If we've already probed this CPU, we have nothing to do */
332 pmu = armpmu_alloc();
334 pr_warn("Unable to allocate PMU for CPU%d\n",
339 cpuid = per_cpu(cpu_data, cpu).reg_midr;
340 pmu->acpi_cpuid = cpuid;
342 arm_pmu_acpi_probe_matching_cpus(pmu, cpuid);
345 if (ret == -ENODEV) {
346 /* PMU not handled by this driver, or not present */
349 pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
353 base_name = pmu->name;
354 pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
356 pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
360 ret = armpmu_register(pmu);
362 pr_warn("Failed to register PMU for CPU%d\n", cpu);
371 static int arm_pmu_acpi_init(void)
376 arm_spe_acpi_register_device();
380 subsys_initcall(arm_pmu_acpi_init)