drivers/perf/arm-cmn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2016-2020 Arm Limited
   3 // CMN-600 Coherent Mesh Network PMU driver
   4
   5 #include <linux/acpi.h>
   6 #include <linux/bitfield.h>
   7 #include <linux/bitops.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12 #include <linux/kernel.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/perf_event.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/sort.h>
  20
  21 /* Common register stuff */
  22 #define CMN_NODE_INFO                   0x0000
  23 #define CMN_NI_NODE_TYPE                GENMASK_ULL(15, 0)
  24 #define CMN_NI_NODE_ID                  GENMASK_ULL(31, 16)
  25 #define CMN_NI_LOGICAL_ID               GENMASK_ULL(47, 32)
  26
  27 #define CMN_NODEID_DEVID(reg)           ((reg) & 3)
  28 #define CMN_NODEID_EXT_DEVID(reg)       ((reg) & 1)
  29 #define CMN_NODEID_PID(reg)             (((reg) >> 2) & 1)
  30 #define CMN_NODEID_EXT_PID(reg)         (((reg) >> 1) & 3)
  31 #define CMN_NODEID_1x1_PID(reg)         (((reg) >> 2) & 7)
  32 #define CMN_NODEID_X(reg, bits)         ((reg) >> (3 + (bits)))
  33 #define CMN_NODEID_Y(reg, bits)         (((reg) >> 3) & ((1U << (bits)) - 1))
  34
  35 #define CMN_CHILD_INFO                  0x0080
  36 #define CMN_CI_CHILD_COUNT              GENMASK_ULL(15, 0)
  37 #define CMN_CI_CHILD_PTR_OFFSET         GENMASK_ULL(31, 16)
  38
  39 #define CMN_CHILD_NODE_ADDR             GENMASK(29, 0)
  40 #define CMN_CHILD_NODE_EXTERNAL         BIT(31)
  41
  42 #define CMN_MAX_DIMENSION               12
  43 #define CMN_MAX_XPS                     (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
  44 #define CMN_MAX_DTMS                    (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
  45
  46 /* The CFG node has various info besides the discovery tree */
  47 #define CMN_CFGM_PERIPH_ID_01           0x0008
  48 #define CMN_CFGM_PID0_PART_0            GENMASK_ULL(7, 0)
  49 #define CMN_CFGM_PID1_PART_1            GENMASK_ULL(35, 32)
  50 #define CMN_CFGM_PERIPH_ID_23           0x0010
  51 #define CMN_CFGM_PID2_REVISION          GENMASK_ULL(7, 4)
  52
  53 #define CMN_CFGM_INFO_GLOBAL            0x900
  54 #define CMN_INFO_MULTIPLE_DTM_EN        BIT_ULL(63)
  55 #define CMN_INFO_RSP_VC_NUM             GENMASK_ULL(53, 52)
  56 #define CMN_INFO_DAT_VC_NUM             GENMASK_ULL(51, 50)
  57
  58 #define CMN_CFGM_INFO_GLOBAL_1          0x908
  59 #define CMN_INFO_SNP_VC_NUM             GENMASK_ULL(3, 2)
  60 #define CMN_INFO_REQ_VC_NUM             GENMASK_ULL(1, 0)
  61
  62 /* XPs also have some local topology info which has uses too */
  63 #define CMN_MXP__CONNECT_INFO(p)        (0x0008 + 8 * (p))
  64 #define CMN__CONNECT_INFO_DEVICE_TYPE   GENMASK_ULL(4, 0)
  65
  66 #define CMN_MAX_PORTS                   6
  67 #define CI700_CONNECT_INFO_P2_5_OFFSET  0x10
  68
  69 /* PMU registers occupy the 3rd 4KB page of each node's region */
  70 #define CMN_PMU_OFFSET                  0x2000
  71
  72 /* For most nodes, this is all there is */
  73 #define CMN_PMU_EVENT_SEL               0x000
  74 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL   GENMASK_ULL(44, 42)
  75 #define CMN__PMU_SN_HOME_SEL            GENMASK_ULL(40, 39)
  76 #define CMN__PMU_HBT_LBT_SEL            GENMASK_ULL(38, 37)
  77 #define CMN__PMU_CLASS_OCCUP_ID         GENMASK_ULL(36, 35)
  78 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */
  79 #define CMN__PMU_OCCUP1_ID              GENMASK_ULL(34, 32)
  80
  81 /* HN-Ps are weird... */
  82 #define CMN_HNP_PMU_EVENT_SEL           0x008
  83
  84 /* DTMs live in the PMU space of XP registers */
  85 #define CMN_DTM_WPn(n)                  (0x1A0 + (n) * 0x18)
  86 #define CMN_DTM_WPn_CONFIG(n)           (CMN_DTM_WPn(n) + 0x00)
  87 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM   GENMASK_ULL(20, 19)
  88 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2  GENMASK_ULL(18, 17)
  89 #define CMN_DTM_WPn_CONFIG_WP_COMBINE   BIT(9)
  90 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
  91 #define CMN600_WPn_CONFIG_WP_COMBINE    BIT(6)
  92 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE  BIT(5)
  93 #define CMN_DTM_WPn_CONFIG_WP_GRP       GENMASK_ULL(5, 4)
  94 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL   GENMASK_ULL(3, 1)
  95 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL   BIT(0)
  96 #define CMN_DTM_WPn_VAL(n)              (CMN_DTM_WPn(n) + 0x08)
  97 #define CMN_DTM_WPn_MASK(n)             (CMN_DTM_WPn(n) + 0x10)
  98
  99 #define CMN_DTM_PMU_CONFIG              0x210
 100 #define CMN__PMEVCNT0_INPUT_SEL         GENMASK_ULL(37, 32)
 101 #define CMN__PMEVCNT0_INPUT_SEL_WP      0x00
 102 #define CMN__PMEVCNT0_INPUT_SEL_XP      0x04
 103 #define CMN__PMEVCNT0_INPUT_SEL_DEV     0x10
 104 #define CMN__PMEVCNT0_GLOBAL_NUM        GENMASK_ULL(18, 16)
 105 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n)       ((n) * 4)
 106 #define CMN__PMEVCNT_PAIRED(n)          BIT(4 + (n))
 107 #define CMN__PMEVCNT23_COMBINED         BIT(2)
 108 #define CMN__PMEVCNT01_COMBINED         BIT(1)
 109 #define CMN_DTM_PMU_CONFIG_PMU_EN       BIT(0)
 110
 111 #define CMN_DTM_PMEVCNT                 0x220
 112
 113 #define CMN_DTM_PMEVCNTSR               0x240
 114
 115 #define CMN_DTM_UNIT_INFO               0x0910
 116
 117 #define CMN_DTM_NUM_COUNTERS            4
 118 /* Want more local counters? Why not replicate the whole DTM! Ugh... */
 119 #define CMN_DTM_OFFSET(n)               ((n) * 0x200)
 120
 121 /* The DTC node is where the magic happens */
 122 #define CMN_DT_DTC_CTL                  0x0a00
 123 #define CMN_DT_DTC_CTL_DT_EN            BIT(0)
 124
 125 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
 126 #define _CMN_DT_CNT_REG(n)              ((((n) / 2) * 4 + (n) % 2) * 4)
 127 #define CMN_DT_PMEVCNT(n)               (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
 128 #define CMN_DT_PMCCNTR                  (CMN_PMU_OFFSET + 0x40)
 129
 130 #define CMN_DT_PMEVCNTSR(n)             (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
 131 #define CMN_DT_PMCCNTRSR                (CMN_PMU_OFFSET + 0x90)
 132
 133 #define CMN_DT_PMCR                     (CMN_PMU_OFFSET + 0x100)
 134 #define CMN_DT_PMCR_PMU_EN              BIT(0)
 135 #define CMN_DT_PMCR_CNTR_RST            BIT(5)
 136 #define CMN_DT_PMCR_OVFL_INTR_EN        BIT(6)
 137
 138 #define CMN_DT_PMOVSR                   (CMN_PMU_OFFSET + 0x118)
 139 #define CMN_DT_PMOVSR_CLR               (CMN_PMU_OFFSET + 0x120)
 140
 141 #define CMN_DT_PMSSR                    (CMN_PMU_OFFSET + 0x128)
 142 #define CMN_DT_PMSSR_SS_STATUS(n)       BIT(n)
 143
 144 #define CMN_DT_PMSRR                    (CMN_PMU_OFFSET + 0x130)
 145 #define CMN_DT_PMSRR_SS_REQ             BIT(0)
 146
 147 #define CMN_DT_NUM_COUNTERS             8
 148 #define CMN_MAX_DTCS                    4
 149
 150 /*
 151  * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
 152  * so throwing away one bit to make overflow handling easy is no big deal.
 153  */
 154 #define CMN_COUNTER_INIT                0x80000000
 155 /* Similarly for the 40-bit cycle counter */
 156 #define CMN_CC_INIT                     0x8000000000ULL
 157
 158
 159 /* Event attributes */
 160 #define CMN_CONFIG_TYPE                 GENMASK_ULL(15, 0)
 161 #define CMN_CONFIG_EVENTID              GENMASK_ULL(26, 16)
 162 #define CMN_CONFIG_OCCUPID              GENMASK_ULL(30, 27)
 163 #define CMN_CONFIG_BYNODEID             BIT_ULL(31)
 164 #define CMN_CONFIG_NODEID               GENMASK_ULL(47, 32)
 165
 166 #define CMN_EVENT_TYPE(event)           FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
 167 #define CMN_EVENT_EVENTID(event)        FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
 168 #define CMN_EVENT_OCCUPID(event)        FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
 169 #define CMN_EVENT_BYNODEID(event)       FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
 170 #define CMN_EVENT_NODEID(event)         FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
 171
 172 #define CMN_CONFIG_WP_COMBINE           GENMASK_ULL(30, 27)
 173 #define CMN_CONFIG_WP_DEV_SEL           GENMASK_ULL(50, 48)
 174 #define CMN_CONFIG_WP_CHN_SEL           GENMASK_ULL(55, 51)
 175 /* Note that we don't yet support the tertiary match group on newer IPs */
 176 #define CMN_CONFIG_WP_GRP               BIT_ULL(56)
 177 #define CMN_CONFIG_WP_EXCLUSIVE         BIT_ULL(57)
 178 #define CMN_CONFIG1_WP_VAL              GENMASK_ULL(63, 0)
 179 #define CMN_CONFIG2_WP_MASK             GENMASK_ULL(63, 0)
 180
 181 #define CMN_EVENT_WP_COMBINE(event)     FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
 182 #define CMN_EVENT_WP_DEV_SEL(event)     FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
 183 #define CMN_EVENT_WP_CHN_SEL(event)     FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
 184 #define CMN_EVENT_WP_GRP(event)         FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
 185 #define CMN_EVENT_WP_EXCLUSIVE(event)   FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
 186 #define CMN_EVENT_WP_VAL(event)         FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
 187 #define CMN_EVENT_WP_MASK(event)        FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
 188
 189 /* Made-up event IDs for watchpoint direction */
 190 #define CMN_WP_UP                       0
 191 #define CMN_WP_DOWN                     2
 192
 193
 194 /* Internal values for encoding event support */
 195 enum cmn_model {
 196         CMN600 = 1,
 197         CMN650 = 2,
 198         CMN700 = 4,
 199         CI700 = 8,
 200         /* ...and then we can use bitmap tricks for commonality */
 201         CMN_ANY = -1,
 202         NOT_CMN600 = -2,
 203         CMN_650ON = CMN650 | CMN700,
 204 };
 205
 206 /* Actual part numbers and revision IDs defined by the hardware */
 207 enum cmn_part {
 208         PART_CMN600 = 0x434,
 209         PART_CMN650 = 0x436,
 210         PART_CMN700 = 0x43c,
 211         PART_CI700 = 0x43a,
 212 };
 213
 214 /* CMN-600 r0px shouldn't exist in silicon, thankfully */
 215 enum cmn_revision {
 216         REV_CMN600_R1P0,
 217         REV_CMN600_R1P1,
 218         REV_CMN600_R1P2,
 219         REV_CMN600_R1P3,
 220         REV_CMN600_R2P0,
 221         REV_CMN600_R3P0,
 222         REV_CMN600_R3P1,
 223         REV_CMN650_R0P0 = 0,
 224         REV_CMN650_R1P0,
 225         REV_CMN650_R1P1,
 226         REV_CMN650_R2P0,
 227         REV_CMN650_R1P2,
 228         REV_CMN700_R0P0 = 0,
 229         REV_CMN700_R1P0,
 230         REV_CMN700_R2P0,
 231         REV_CMN700_R3P0,
 232         REV_CI700_R0P0 = 0,
 233         REV_CI700_R1P0,
 234         REV_CI700_R2P0,
 235 };
 236
 237 enum cmn_node_type {
 238         CMN_TYPE_INVALID,
 239         CMN_TYPE_DVM,
 240         CMN_TYPE_CFG,
 241         CMN_TYPE_DTC,
 242         CMN_TYPE_HNI,
 243         CMN_TYPE_HNF,
 244         CMN_TYPE_XP,
 245         CMN_TYPE_SBSX,
 246         CMN_TYPE_MPAM_S,
 247         CMN_TYPE_MPAM_NS,
 248         CMN_TYPE_RNI,
 249         CMN_TYPE_RND = 0xd,
 250         CMN_TYPE_RNSAM = 0xf,
 251         CMN_TYPE_MTSX,
 252         CMN_TYPE_HNP,
 253         CMN_TYPE_CXRA = 0x100,
 254         CMN_TYPE_CXHA,
 255         CMN_TYPE_CXLA,
 256         CMN_TYPE_CCRA,
 257         CMN_TYPE_CCHA,
 258         CMN_TYPE_CCLA,
 259         CMN_TYPE_CCLA_RNI,
 260         CMN_TYPE_HNS = 0x200,
 261         CMN_TYPE_HNS_MPAM_S,
 262         CMN_TYPE_HNS_MPAM_NS,
 263         /* Not a real node type */
 264         CMN_TYPE_WP = 0x7770
 265 };
 266
 267 enum cmn_filter_select {
 268         SEL_NONE = -1,
 269         SEL_OCCUP1ID,
 270         SEL_CLASS_OCCUP_ID,
 271         SEL_CBUSY_SNTHROTTLE_SEL,
 272         SEL_HBT_LBT_SEL,
 273         SEL_SN_HOME_SEL,
 274         SEL_MAX
 275 };
 276
 277 struct arm_cmn_node {
 278         void __iomem *pmu_base;
 279         u16 id, logid;
 280         enum cmn_node_type type;
 281
 282         int dtm;
 283         union {
 284                 /* DN/HN-F/CXHA */
 285                 struct {
 286                         u8 val : 4;
 287                         u8 count : 4;
 288                 } occupid[SEL_MAX];
 289                 /* XP */
 290                 u8 dtc;
 291         };
 292         union {
 293                 u8 event[4];
 294                 __le32 event_sel;
 295                 u16 event_w[4];
 296                 __le64 event_sel_w;
 297         };
 298 };
 299
 300 struct arm_cmn_dtm {
 301         void __iomem *base;
 302         u32 pmu_config_low;
 303         union {
 304                 u8 input_sel[4];
 305                 __le32 pmu_config_high;
 306         };
 307         s8 wp_event[4];
 308 };
 309
 310 struct arm_cmn_dtc {
 311         void __iomem *base;
 312         int irq;
 313         int irq_friend;
 314         bool cc_active;
 315
 316         struct perf_event *counters[CMN_DT_NUM_COUNTERS];
 317         struct perf_event *cycles;
 318 };
 319
 320 #define CMN_STATE_DISABLED      BIT(0)
 321 #define CMN_STATE_TXN           BIT(1)
 322
 323 struct arm_cmn {
 324         struct device *dev;
 325         void __iomem *base;
 326         unsigned int state;
 327
 328         enum cmn_revision rev;
 329         enum cmn_part part;
 330         u8 mesh_x;
 331         u8 mesh_y;
 332         u16 num_xps;
 333         u16 num_dns;
 334         bool multi_dtm;
 335         u8 ports_used;
 336         struct {
 337                 unsigned int rsp_vc_num : 2;
 338                 unsigned int dat_vc_num : 2;
 339                 unsigned int snp_vc_num : 2;
 340                 unsigned int req_vc_num : 2;
 341         };
 342
 343         struct arm_cmn_node *xps;
 344         struct arm_cmn_node *dns;
 345
 346         struct arm_cmn_dtm *dtms;
 347         struct arm_cmn_dtc *dtc;
 348         unsigned int num_dtcs;
 349
 350         int cpu;
 351         struct hlist_node cpuhp_node;
 352
 353         struct pmu pmu;
 354         struct dentry *debug;
 355 };
 356
 357 #define to_cmn(p)       container_of(p, struct arm_cmn, pmu)
 358
 359 static int arm_cmn_hp_state;
 360
 361 struct arm_cmn_nodeid {
 362         u8 x;
 363         u8 y;
 364         u8 port;
 365         u8 dev;
 366 };
 367
 368 static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
 369 {
 370         return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2);
 371 }
 372
 373 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id)
 374 {
 375         struct arm_cmn_nodeid nid;
 376
 377         if (cmn->num_xps == 1) {
 378                 nid.x = 0;
 379                 nid.y = 0;
 380                 nid.port = CMN_NODEID_1x1_PID(id);
 381                 nid.dev = CMN_NODEID_DEVID(id);
 382         } else {
 383                 int bits = arm_cmn_xyidbits(cmn);
 384
 385                 nid.x = CMN_NODEID_X(id, bits);
 386                 nid.y = CMN_NODEID_Y(id, bits);
 387                 if (cmn->ports_used & 0xc) {
 388                         nid.port = CMN_NODEID_EXT_PID(id);
 389                         nid.dev = CMN_NODEID_EXT_DEVID(id);
 390                 } else {
 391                         nid.port = CMN_NODEID_PID(id);
 392                         nid.dev = CMN_NODEID_DEVID(id);
 393                 }
 394         }
 395         return nid;
 396 }
 397
 398 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,
 399                                                const struct arm_cmn_node *dn)
 400 {
 401         struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
 402         int xp_idx = cmn->mesh_x * nid.y + nid.x;
 403
 404         return cmn->xps + xp_idx;
 405 }
 406 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
 407                                          enum cmn_node_type type)
 408 {
 409         struct arm_cmn_node *dn;
 410
 411         for (dn = cmn->dns; dn->type; dn++)
 412                 if (dn->type == type)
 413                         return dn;
 414         return NULL;
 415 }
 416
 417 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)
 418 {
 419         switch (cmn->part) {
 420         case PART_CMN600:
 421                 return CMN600;
 422         case PART_CMN650:
 423                 return CMN650;
 424         case PART_CMN700:
 425                 return CMN700;
 426         case PART_CI700:
 427                 return CI700;
 428         default:
 429                 return 0;
 430         };
 431 }
 432
 433 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,
 434                                        const struct arm_cmn_node *xp, int port)
 435 {
 436         int offset = CMN_MXP__CONNECT_INFO(port);
 437
 438         if (port >= 2) {
 439                 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)
 440                         return 0;
 441                 /*
 442                  * CI-700 may have extra ports, but still has the
 443                  * mesh_port_connect_info registers in the way.
 444                  */
 445                 if (cmn->part == PART_CI700)
 446                         offset += CI700_CONNECT_INFO_P2_5_OFFSET;
 447         }
 448
 449         return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset);
 450 }
 451
 452 static struct dentry *arm_cmn_debugfs;
 453
 454 #ifdef CONFIG_DEBUG_FS
 455 static const char *arm_cmn_device_type(u8 type)
 456 {
 457         switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {
 458                 case 0x00: return "        |";
 459                 case 0x01: return "  RN-I  |";
 460                 case 0x02: return "  RN-D  |";
 461                 case 0x04: return " RN-F_B |";
 462                 case 0x05: return "RN-F_B_E|";
 463                 case 0x06: return " RN-F_A |";
 464                 case 0x07: return "RN-F_A_E|";
 465                 case 0x08: return "  HN-T  |";
 466                 case 0x09: return "  HN-I  |";
 467                 case 0x0a: return "  HN-D  |";
 468                 case 0x0b: return "  HN-P  |";
 469                 case 0x0c: return "  SN-F  |";
 470                 case 0x0d: return "  SBSX  |";
 471                 case 0x0e: return "  HN-F  |";
 472                 case 0x0f: return " SN-F_E |";
 473                 case 0x10: return " SN-F_D |";
 474                 case 0x11: return "  CXHA  |";
 475                 case 0x12: return "  CXRA  |";
 476                 case 0x13: return "  CXRH  |";
 477                 case 0x14: return " RN-F_D |";
 478                 case 0x15: return "RN-F_D_E|";
 479                 case 0x16: return " RN-F_C |";
 480                 case 0x17: return "RN-F_C_E|";
 481                 case 0x18: return " RN-F_E |";
 482                 case 0x19: return "RN-F_E_E|";
 483                 case 0x1c: return "  MTSX  |";
 484                 case 0x1d: return "  HN-V  |";
 485                 case 0x1e: return "  CCG   |";
 486                 default:   return "  ????  |";
 487         }
 488 }
 489
 490 static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d)
 491 {
 492         struct arm_cmn *cmn = s->private;
 493         struct arm_cmn_node *dn;
 494
 495         for (dn = cmn->dns; dn->type; dn++) {
 496                 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
 497
 498                 if (dn->type == CMN_TYPE_XP)
 499                         continue;
 500                 /* Ignore the extra components that will overlap on some ports */
 501                 if (dn->type < CMN_TYPE_HNI)
 502                         continue;
 503
 504                 if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d)
 505                         continue;
 506
 507                 seq_printf(s, "   #%-2d  |", dn->logid);
 508                 return;
 509         }
 510         seq_puts(s, "        |");
 511 }
 512
 513 static int arm_cmn_map_show(struct seq_file *s, void *data)
 514 {
 515         struct arm_cmn *cmn = s->private;
 516         int x, y, p, pmax = fls(cmn->ports_used);
 517
 518         seq_puts(s, "     X");
 519         for (x = 0; x < cmn->mesh_x; x++)
 520                 seq_printf(s, "    %d    ", x);
 521         seq_puts(s, "\nY P D+");
 522         y = cmn->mesh_y;
 523         while (y--) {
 524                 int xp_base = cmn->mesh_x * y;
 525                 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION];
 526
 527                 for (x = 0; x < cmn->mesh_x; x++)
 528                         seq_puts(s, "--------+");
 529
 530                 seq_printf(s, "\n%d    |", y);
 531                 for (x = 0; x < cmn->mesh_x; x++) {
 532                         struct arm_cmn_node *xp = cmn->xps + xp_base + x;
 533
 534                         for (p = 0; p < CMN_MAX_PORTS; p++)
 535                                 port[p][x] = arm_cmn_device_connect_info(cmn, xp, p);
 536                         seq_printf(s, " XP #%-2d |", xp_base + x);
 537                 }
 538
 539                 seq_puts(s, "\n     |");
 540                 for (x = 0; x < cmn->mesh_x; x++) {
 541                         u8 dtc = cmn->xps[xp_base + x].dtc;
 542
 543                         if (dtc & (dtc - 1))
 544                                 seq_puts(s, " DTC ?? |");
 545                         else
 546                                 seq_printf(s, " DTC %ld  |", __ffs(dtc));
 547                 }
 548                 seq_puts(s, "\n     |");
 549                 for (x = 0; x < cmn->mesh_x; x++)
 550                         seq_puts(s, "........|");
 551
 552                 for (p = 0; p < pmax; p++) {
 553                         seq_printf(s, "\n  %d  |", p);
 554                         for (x = 0; x < cmn->mesh_x; x++)
 555                                 seq_puts(s, arm_cmn_device_type(port[p][x]));
 556                         seq_puts(s, "\n    0|");
 557                         for (x = 0; x < cmn->mesh_x; x++)
 558                                 arm_cmn_show_logid(s, x, y, p, 0);
 559                         seq_puts(s, "\n    1|");
 560                         for (x = 0; x < cmn->mesh_x; x++)
 561                                 arm_cmn_show_logid(s, x, y, p, 1);
 562                 }
 563                 seq_puts(s, "\n-----+");
 564         }
 565         for (x = 0; x < cmn->mesh_x; x++)
 566                 seq_puts(s, "--------+");
 567         seq_puts(s, "\n");
 568         return 0;
 569 }
 570 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map);
 571
 572 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)
 573 {
 574         const char *name  = "map";
 575
 576         if (id > 0)
 577                 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id);
 578         if (!name)
 579                 return;
 580
 581         cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops);
 582 }
 583 #else
 584 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}
 585 #endif
 586
 587 struct arm_cmn_hw_event {
 588         struct arm_cmn_node *dn;
 589         u64 dtm_idx[4];
 590         unsigned int dtc_idx;
 591         u8 dtcs_used;
 592         u8 num_dns;
 593         u8 dtm_offset;
 594         bool wide_sel;
 595         enum cmn_filter_select filter_sel;
 596 };
 597
 598 #define for_each_hw_dn(hw, dn, i) \
 599         for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
 600
 601 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
 602 {
 603         BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
 604         return (struct arm_cmn_hw_event *)&event->hw;
 605 }
 606
 607 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
 608 {
 609         x[pos / 32] |= (u64)val << ((pos % 32) * 2);
 610 }
 611
 612 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
 613 {
 614         return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
 615 }
 616
 617 struct arm_cmn_event_attr {
 618         struct device_attribute attr;
 619         enum cmn_model model;
 620         enum cmn_node_type type;
 621         enum cmn_filter_select fsel;
 622         u16 eventid;
 623         u8 occupid;
 624 };
 625
 626 struct arm_cmn_format_attr {
 627         struct device_attribute attr;
 628         u64 field;
 629         int config;
 630 };
 631
 632 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\
 633         (&((struct arm_cmn_event_attr[]) {{                             \
 634                 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL),  \
 635                 .model = _model,                                        \
 636                 .type = _type,                                          \
 637                 .eventid = _eventid,                                    \
 638                 .occupid = _occupid,                                    \
 639                 .fsel = _fsel,                                          \
 640         }})[0].attr.attr)
 641 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid)                  \
 642         _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE)
 643
 644 static ssize_t arm_cmn_event_show(struct device *dev,
 645                                   struct device_attribute *attr, char *buf)
 646 {
 647         struct arm_cmn_event_attr *eattr;
 648
 649         eattr = container_of(attr, typeof(*eattr), attr);
 650
 651         if (eattr->type == CMN_TYPE_DTC)
 652                 return sysfs_emit(buf, "type=0x%x\n", eattr->type);
 653
 654         if (eattr->type == CMN_TYPE_WP)
 655                 return sysfs_emit(buf,
 656                                   "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
 657                                   eattr->type, eattr->eventid);
 658
 659         if (eattr->fsel > SEL_NONE)
 660                 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
 661                                   eattr->type, eattr->eventid, eattr->occupid);
 662
 663         return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type,
 664                           eattr->eventid);
 665 }
 666
 667 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
 668                                              struct attribute *attr,
 669                                              int unused)
 670 {
 671         struct device *dev = kobj_to_dev(kobj);
 672         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
 673         struct arm_cmn_event_attr *eattr;
 674         enum cmn_node_type type;
 675         u16 eventid;
 676
 677         eattr = container_of(attr, typeof(*eattr), attr.attr);
 678
 679         if (!(eattr->model & arm_cmn_model(cmn)))
 680                 return 0;
 681
 682         type = eattr->type;
 683         eventid = eattr->eventid;
 684
 685         /* Watchpoints aren't nodes, so avoid confusion */
 686         if (type == CMN_TYPE_WP)
 687                 return attr->mode;
 688
 689         /* Hide XP events for unused interfaces/channels */
 690         if (type == CMN_TYPE_XP) {
 691                 unsigned int intf = (eventid >> 2) & 7;
 692                 unsigned int chan = eventid >> 5;
 693
 694                 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
 695                         return 0;
 696
 697                 if (chan == 4 && cmn->part == PART_CMN600)
 698                         return 0;
 699
 700                 if ((chan == 5 && cmn->rsp_vc_num < 2) ||
 701                     (chan == 6 && cmn->dat_vc_num < 2) ||
 702                     (chan == 7 && cmn->snp_vc_num < 2) ||
 703                     (chan == 8 && cmn->req_vc_num < 2))
 704                         return 0;
 705         }
 706
 707         /* Revision-specific differences */
 708         if (cmn->part == PART_CMN600) {
 709                 if (cmn->rev < REV_CMN600_R1P3) {
 710                         if (type == CMN_TYPE_CXRA && eventid > 0x10)
 711                                 return 0;
 712                 }
 713                 if (cmn->rev < REV_CMN600_R1P2) {
 714                         if (type == CMN_TYPE_HNF && eventid == 0x1b)
 715                                 return 0;
 716                         if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)
 717                                 return 0;
 718                 }
 719         } else if (cmn->part == PART_CMN650) {
 720                 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {
 721                         if (type == CMN_TYPE_HNF && eventid > 0x22)
 722                                 return 0;
 723                         if (type == CMN_TYPE_SBSX && eventid == 0x17)
 724                                 return 0;
 725                         if (type == CMN_TYPE_RNI && eventid > 0x10)
 726                                 return 0;
 727                 }
 728         } else if (cmn->part == PART_CMN700) {
 729                 if (cmn->rev < REV_CMN700_R2P0) {
 730                         if (type == CMN_TYPE_HNF && eventid > 0x2c)
 731                                 return 0;
 732                         if (type == CMN_TYPE_CCHA && eventid > 0x74)
 733                                 return 0;
 734                         if (type == CMN_TYPE_CCLA && eventid > 0x27)
 735                                 return 0;
 736                 }
 737                 if (cmn->rev < REV_CMN700_R1P0) {
 738                         if (type == CMN_TYPE_HNF && eventid > 0x2b)
 739                                 return 0;
 740                 }
 741         }
 742
 743         if (!arm_cmn_node(cmn, type))
 744                 return 0;
 745
 746         return attr->mode;
 747 }
 748
 749 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel)    \
 750         _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel)
 751 #define CMN_EVENT_DTC(_name)                                    \
 752         CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0)
 753 #define CMN_EVENT_HNF(_model, _name, _event)                    \
 754         CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 755 #define CMN_EVENT_HNI(_name, _event)                            \
 756         CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event)
 757 #define CMN_EVENT_HNP(_name, _event)                            \
 758         CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event)
 759 #define __CMN_EVENT_XP(_name, _event)                           \
 760         CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event)
 761 #define CMN_EVENT_SBSX(_model, _name, _event)                   \
 762         CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event)
 763 #define CMN_EVENT_RNID(_model, _name, _event)                   \
 764         CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event)
 765 #define CMN_EVENT_MTSX(_name, _event)                           \
 766         CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event)
 767 #define CMN_EVENT_CXRA(_model, _name, _event)                           \
 768         CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event)
 769 #define CMN_EVENT_CXHA(_name, _event)                           \
 770         CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event)
 771 #define CMN_EVENT_CCRA(_name, _event)                           \
 772         CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event)
 773 #define CMN_EVENT_CCHA(_name, _event)                           \
 774         CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event)
 775 #define CMN_EVENT_CCLA(_name, _event)                           \
 776         CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event)
 777 #define CMN_EVENT_CCLA_RNI(_name, _event)                               \
 778         CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event)
 779 #define CMN_EVENT_HNS(_name, _event)                            \
 780         CMN_EVENT_ATTR(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
 781
 782 #define CMN_EVENT_DVM(_model, _name, _event)                    \
 783         _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE)
 784 #define CMN_EVENT_DVM_OCC(_model, _name, _event)                        \
 785         _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID),   \
 786         _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \
 787         _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID)
 788
 789 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event)          \
 790         _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_OCCUP1ID), \
 791         _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 1, SEL_OCCUP1ID), \
 792         _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 2, SEL_OCCUP1ID), \
 793         _CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, 3, SEL_OCCUP1ID), \
 794         _CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, 4, SEL_OCCUP1ID)
 795 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event)                  \
 796         _CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, 0, SEL_CLASS_OCCUP_ID), \
 797         _CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, 1, SEL_CLASS_OCCUP_ID), \
 798         _CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, 2, SEL_CLASS_OCCUP_ID), \
 799         _CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, 3, SEL_CLASS_OCCUP_ID)
 800 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event)                  \
 801         _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \
 802         _CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \
 803         _CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \
 804         _CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \
 805         _CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \
 806         _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \
 807         _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL)
 808
 809 #define CMN_EVENT_HNF_OCC(_model, _name, _event)                        \
 810         CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 811 #define CMN_EVENT_HNF_CLS(_model, _name, _event)                        \
 812         CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNS, _event)
 813 #define CMN_EVENT_HNF_SNT(_model, _name, _event)                        \
 814         CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 815
 816 #define CMN_EVENT_HNS_OCC(_name, _event)                                \
 817         CMN_EVENT_HN_OCC(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event),   \
 818         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_rxsnp, CMN_TYPE_HNS, _event, 5, SEL_OCCUP1ID), \
 819         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 6, SEL_OCCUP1ID), \
 820         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 7, SEL_OCCUP1ID)
 821 #define CMN_EVENT_HNS_CLS( _name, _event)                               \
 822         CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
 823 #define CMN_EVENT_HNS_SNT(_name, _event)                                \
 824         CMN_EVENT_HN_SNT(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
 825 #define CMN_EVENT_HNS_HBT(_name, _event)                                \
 826         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_HBT_LBT_SEL), \
 827         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 1, SEL_HBT_LBT_SEL), \
 828         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 2, SEL_HBT_LBT_SEL)
 829 #define CMN_EVENT_HNS_SNH(_name, _event)                                \
 830         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_SN_HOME_SEL), \
 831         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_sn, CMN_TYPE_HNS, _event, 1, SEL_SN_HOME_SEL), \
 832         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_home, CMN_TYPE_HNS, _event, 2, SEL_SN_HOME_SEL)
 833
 834 #define _CMN_EVENT_XP_MESH(_name, _event)                       \
 835         __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)),         \
 836         __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)),         \
 837         __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)),         \
 838         __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2))
 839
 840 #define _CMN_EVENT_XP_PORT(_name, _event)                       \
 841         __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)),        \
 842         __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)),        \
 843         __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)),        \
 844         __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2))
 845
 846 #define _CMN_EVENT_XP(_name, _event)                            \
 847         _CMN_EVENT_XP_MESH(_name, _event),                      \
 848         _CMN_EVENT_XP_PORT(_name, _event)
 849
 850 /* Good thing there are only 3 fundamental XP events... */
 851 #define CMN_EVENT_XP(_name, _event)                             \
 852         _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)),        \
 853         _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)),        \
 854         _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)),        \
 855         _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)),        \
 856         _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)),        \
 857         _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)),       \
 858         _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)),       \
 859         _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)),       \
 860         _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5))
 861
 862 #define CMN_EVENT_XP_DAT(_name, _event)                         \
 863         _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)),   \
 864         _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5))
 865
 866
 867 static struct attribute *arm_cmn_event_attrs[] = {
 868         CMN_EVENT_DTC(cycles),
 869
 870         /*
 871          * DVM node events conflict with HN-I events in the equivalent PMU
 872          * slot, but our lazy short-cut of using the DTM counter index for
 873          * the PMU index as well happens to avoid that by construction.
 874          */
 875         CMN_EVENT_DVM(CMN600, rxreq_dvmop,              0x01),
 876         CMN_EVENT_DVM(CMN600, rxreq_dvmsync,            0x02),
 877         CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03),
 878         CMN_EVENT_DVM(CMN600, rxreq_retried,            0x04),
 879         CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy,  0x05),
 880         CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi,           0x01),
 881         CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi,            0x02),
 882         CMN_EVENT_DVM(NOT_CMN600, dvmop_pici,           0x03),
 883         CMN_EVENT_DVM(NOT_CMN600, dvmop_vici,           0x04),
 884         CMN_EVENT_DVM(NOT_CMN600, dvmsync,              0x05),
 885         CMN_EVENT_DVM(NOT_CMN600, vmid_filtered,        0x06),
 886         CMN_EVENT_DVM(NOT_CMN600, rndop_filtered,       0x07),
 887         CMN_EVENT_DVM(NOT_CMN600, retry,                0x08),
 888         CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv,          0x09),
 889         CMN_EVENT_DVM(NOT_CMN600, txsnp_stall,          0x0a),
 890         CMN_EVENT_DVM(NOT_CMN600, trkfull,              0x0b),
 891         CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy,    0x0c),
 892         CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha,   0x0d),
 893         CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn,    0x0e),
 894         CMN_EVENT_DVM(CMN700, trk_alloc,                0x0f),
 895         CMN_EVENT_DVM(CMN700, trk_cxha_alloc,           0x10),
 896         CMN_EVENT_DVM(CMN700, trk_pdn_alloc,            0x11),
 897         CMN_EVENT_DVM(CMN700, txsnp_stall_limit,        0x12),
 898         CMN_EVENT_DVM(CMN700, rxsnp_stall_starv,        0x13),
 899         CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op,      0x14),
 900
 901         CMN_EVENT_HNF(CMN_ANY, cache_miss,              0x01),
 902         CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access,     0x02),
 903         CMN_EVENT_HNF(CMN_ANY, cache_fill,              0x03),
 904         CMN_EVENT_HNF(CMN_ANY, pocq_retry,              0x04),
 905         CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd,         0x05),
 906         CMN_EVENT_HNF(CMN_ANY, sf_hit,                  0x06),
 907         CMN_EVENT_HNF(CMN_ANY, sf_evictions,            0x07),
 908         CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent,         0x08),
 909         CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent,         0x09),
 910         CMN_EVENT_HNF(CMN_ANY, slc_eviction,            0x0a),
 911         CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way,    0x0b),
 912         CMN_EVENT_HNF(CMN_ANY, mc_retries,              0x0c),
 913         CMN_EVENT_HNF(CMN_ANY, mc_reqs,                 0x0d),
 914         CMN_EVENT_HNF(CMN_ANY, qos_hh_retry,            0x0e),
 915         CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy,  0x0f),
 916         CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz,            0x10),
 917         CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz,     0x11),
 918         CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full,      0x12),
 919         CMN_EVENT_HNF(CMN_ANY, cmp_adq_full,            0x13),
 920         CMN_EVENT_HNF(CMN_ANY, txdat_stall,             0x14),
 921         CMN_EVENT_HNF(CMN_ANY, txrsp_stall,             0x15),
 922         CMN_EVENT_HNF(CMN_ANY, seq_full,                0x16),
 923         CMN_EVENT_HNF(CMN_ANY, seq_hit,                 0x17),
 924         CMN_EVENT_HNF(CMN_ANY, snp_sent,                0x18),
 925         CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent,       0x19),
 926         CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent,       0x1a),
 927         CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk,          0x1b),
 928         CMN_EVENT_HNF(CMN_ANY, intv_dirty,              0x1c),
 929         CMN_EVENT_HNF(CMN_ANY, stash_snp_sent,          0x1d),
 930         CMN_EVENT_HNF(CMN_ANY, stash_data_pull,         0x1e),
 931         CMN_EVENT_HNF(CMN_ANY, snp_fwded,               0x1f),
 932         CMN_EVENT_HNF(NOT_CMN600, atomic_fwd,           0x20),
 933         CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim,         0x21),
 934         CMN_EVENT_HNF(NOT_CMN600, mpam_softlim,         0x22),
 935         CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster,      0x23),
 936         CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict,    0x24),
 937         CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line,  0x25),
 938         CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup,     0x26),
 939         CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry,     0x27),
 940         CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs,        0x28),
 941         CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin,      0x29),
 942         CMN_EVENT_HNF_SNT(CMN700, sn_throttle,          0x2a),
 943         CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min,      0x2b),
 944         CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise,  0x2c),
 945         CMN_EVENT_HNF(CMN700, snp_intv_cln,             0x2d),
 946         CMN_EVENT_HNF(CMN700, nc_excl,                  0x2e),
 947         CMN_EVENT_HNF(CMN700, excl_mon_ovfl,            0x2f),
 948
 949         CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl,              0x20),
 950         CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl,              0x21),
 951         CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl,              0x22),
 952         CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl,              0x23),
 953         CMN_EVENT_HNI(wdb_occ_cnt_ovfl,                 0x24),
 954         CMN_EVENT_HNI(rrt_rd_alloc,                     0x25),
 955         CMN_EVENT_HNI(rrt_wr_alloc,                     0x26),
 956         CMN_EVENT_HNI(rdt_rd_alloc,                     0x27),
 957         CMN_EVENT_HNI(rdt_wr_alloc,                     0x28),
 958         CMN_EVENT_HNI(wdb_alloc,                        0x29),
 959         CMN_EVENT_HNI(txrsp_retryack,                   0x2a),
 960         CMN_EVENT_HNI(arvalid_no_arready,               0x2b),
 961         CMN_EVENT_HNI(arready_no_arvalid,               0x2c),
 962         CMN_EVENT_HNI(awvalid_no_awready,               0x2d),
 963         CMN_EVENT_HNI(awready_no_awvalid,               0x2e),
 964         CMN_EVENT_HNI(wvalid_no_wready,                 0x2f),
 965         CMN_EVENT_HNI(txdat_stall,                      0x30),
 966         CMN_EVENT_HNI(nonpcie_serialization,            0x31),
 967         CMN_EVENT_HNI(pcie_serialization,               0x32),
 968
 969         /*
 970          * HN-P events squat on top of the HN-I similarly to DVM events, except
 971          * for being crammed into the same physical node as well. And of course
 972          * where would the fun be if the same events were in the same order...
 973          */
 974         CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl,              0x01),
 975         CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl,              0x02),
 976         CMN_EVENT_HNP(wdb_occ_cnt_ovfl,                 0x03),
 977         CMN_EVENT_HNP(rrt_wr_alloc,                     0x04),
 978         CMN_EVENT_HNP(rdt_wr_alloc,                     0x05),
 979         CMN_EVENT_HNP(wdb_alloc,                        0x06),
 980         CMN_EVENT_HNP(awvalid_no_awready,               0x07),
 981         CMN_EVENT_HNP(awready_no_awvalid,               0x08),
 982         CMN_EVENT_HNP(wvalid_no_wready,                 0x09),
 983         CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl,              0x11),
 984         CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl,              0x12),
 985         CMN_EVENT_HNP(rrt_rd_alloc,                     0x13),
 986         CMN_EVENT_HNP(rdt_rd_alloc,                     0x14),
 987         CMN_EVENT_HNP(arvalid_no_arready,               0x15),
 988         CMN_EVENT_HNP(arready_no_arvalid,               0x16),
 989
 990         CMN_EVENT_XP(txflit_valid,                      0x01),
 991         CMN_EVENT_XP(txflit_stall,                      0x02),
 992         CMN_EVENT_XP_DAT(partial_dat_flit,              0x03),
 993         /* We treat watchpoints as a special made-up class of XP events */
 994         CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP),
 995         CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN),
 996
 997         CMN_EVENT_SBSX(CMN_ANY, rd_req,                 0x01),
 998         CMN_EVENT_SBSX(CMN_ANY, wr_req,                 0x02),
 999         CMN_EVENT_SBSX(CMN_ANY, cmo_req,                0x03),
1000         CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack,         0x04),
1001         CMN_EVENT_SBSX(CMN_ANY, txdat_flitv,            0x05),
1002         CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv,            0x06),
1003         CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11),
1004         CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12),
1005         CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13),
1006         CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl,       0x14),
1007         CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15),
1008         CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16),
1009         CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl,    0x17),
1010         CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready,     0x21),
1011         CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready,     0x22),
1012         CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready,       0x23),
1013         CMN_EVENT_SBSX(CMN_ANY, txdat_stall,            0x24),
1014         CMN_EVENT_SBSX(CMN_ANY, txrsp_stall,            0x25),
1015
1016         CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats,         0x01),
1017         CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats,         0x02),
1018         CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats,         0x03),
1019         CMN_EVENT_RNID(CMN_ANY, rxdat_flits,            0x04),
1020         CMN_EVENT_RNID(CMN_ANY, txdat_flits,            0x05),
1021         CMN_EVENT_RNID(CMN_ANY, txreq_flits_total,      0x06),
1022         CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried,    0x07),
1023         CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl,           0x08),
1024         CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl,           0x09),
1025         CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed,   0x0a),
1026         CMN_EVENT_RNID(CMN_ANY, wrcancel_sent,          0x0b),
1027         CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats,         0x0c),
1028         CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats,         0x0d),
1029         CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats,         0x0e),
1030         CMN_EVENT_RNID(CMN_ANY, rrt_alloc,              0x0f),
1031         CMN_EVENT_RNID(CMN_ANY, wrt_alloc,              0x10),
1032         CMN_EVENT_RNID(CMN600, rdb_unord,               0x11),
1033         CMN_EVENT_RNID(CMN600, rdb_replay,              0x12),
1034         CMN_EVENT_RNID(CMN600, rdb_hybrid,              0x13),
1035         CMN_EVENT_RNID(CMN600, rdb_ord,                 0x14),
1036         CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl,       0x11),
1037         CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl,       0x12),
1038         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13),
1039         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14),
1040         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15),
1041         CMN_EVENT_RNID(NOT_CMN600, wrt_throttled,       0x16),
1042         CMN_EVENT_RNID(CMN700, ldb_full,                0x17),
1043         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18),
1044         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19),
1045         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a),
1046         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b),
1047         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c),
1048         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d),
1049         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e),
1050         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f),
1051         CMN_EVENT_RNID(CMN700, rrt_burst_alloc,         0x20),
1052         CMN_EVENT_RNID(CMN700, awid_hash,               0x21),
1053         CMN_EVENT_RNID(CMN700, atomic_alloc,            0x22),
1054         CMN_EVENT_RNID(CMN700, atomic_occ_ovfl,         0x23),
1055
1056         CMN_EVENT_MTSX(tc_lookup,                       0x01),
1057         CMN_EVENT_MTSX(tc_fill,                         0x02),
1058         CMN_EVENT_MTSX(tc_miss,                         0x03),
1059         CMN_EVENT_MTSX(tdb_forward,                     0x04),
1060         CMN_EVENT_MTSX(tcq_hazard,                      0x05),
1061         CMN_EVENT_MTSX(tcq_rd_alloc,                    0x06),
1062         CMN_EVENT_MTSX(tcq_wr_alloc,                    0x07),
1063         CMN_EVENT_MTSX(tcq_cmo_alloc,                   0x08),
1064         CMN_EVENT_MTSX(axi_rd_req,                      0x09),
1065         CMN_EVENT_MTSX(axi_wr_req,                      0x0a),
1066         CMN_EVENT_MTSX(tcq_occ_cnt_ovfl,                0x0b),
1067         CMN_EVENT_MTSX(tdb_occ_cnt_ovfl,                0x0c),
1068
1069         CMN_EVENT_CXRA(CMN_ANY, rht_occ,                0x01),
1070         CMN_EVENT_CXRA(CMN_ANY, sht_occ,                0x02),
1071         CMN_EVENT_CXRA(CMN_ANY, rdb_occ,                0x03),
1072         CMN_EVENT_CXRA(CMN_ANY, wdb_occ,                0x04),
1073         CMN_EVENT_CXRA(CMN_ANY, ssb_occ,                0x05),
1074         CMN_EVENT_CXRA(CMN_ANY, snp_bcasts,             0x06),
1075         CMN_EVENT_CXRA(CMN_ANY, req_chains,             0x07),
1076         CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen,       0x08),
1077         CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls,          0x09),
1078         CMN_EVENT_CXRA(CMN_ANY, chidat_stalls,          0x0a),
1079         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b),
1080         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c),
1081         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d),
1082         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e),
1083         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f),
1084         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10),
1085         CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11),
1086         CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12),
1087         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13),
1088         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14),
1089         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15),
1090
1091         CMN_EVENT_CXHA(rddatbyp,                        0x21),
1092         CMN_EVENT_CXHA(chirsp_up_stall,                 0x22),
1093         CMN_EVENT_CXHA(chidat_up_stall,                 0x23),
1094         CMN_EVENT_CXHA(snppcrd_link0_stall,             0x24),
1095         CMN_EVENT_CXHA(snppcrd_link1_stall,             0x25),
1096         CMN_EVENT_CXHA(snppcrd_link2_stall,             0x26),
1097         CMN_EVENT_CXHA(reqtrk_occ,                      0x27),
1098         CMN_EVENT_CXHA(rdb_occ,                         0x28),
1099         CMN_EVENT_CXHA(rdbyp_occ,                       0x29),
1100         CMN_EVENT_CXHA(wdb_occ,                         0x2a),
1101         CMN_EVENT_CXHA(snptrk_occ,                      0x2b),
1102         CMN_EVENT_CXHA(sdb_occ,                         0x2c),
1103         CMN_EVENT_CXHA(snphaz_occ,                      0x2d),
1104
1105         CMN_EVENT_CCRA(rht_occ,                         0x41),
1106         CMN_EVENT_CCRA(sht_occ,                         0x42),
1107         CMN_EVENT_CCRA(rdb_occ,                         0x43),
1108         CMN_EVENT_CCRA(wdb_occ,                         0x44),
1109         CMN_EVENT_CCRA(ssb_occ,                         0x45),
1110         CMN_EVENT_CCRA(snp_bcasts,                      0x46),
1111         CMN_EVENT_CCRA(req_chains,                      0x47),
1112         CMN_EVENT_CCRA(req_chain_avglen,                0x48),
1113         CMN_EVENT_CCRA(chirsp_stalls,                   0x49),
1114         CMN_EVENT_CCRA(chidat_stalls,                   0x4a),
1115         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0,         0x4b),
1116         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1,         0x4c),
1117         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2,         0x4d),
1118         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0,         0x4e),
1119         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1,         0x4f),
1120         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2,         0x50),
1121         CMN_EVENT_CCRA(external_chirsp_stalls,          0x51),
1122         CMN_EVENT_CCRA(external_chidat_stalls,          0x52),
1123         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0,        0x53),
1124         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1,        0x54),
1125         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2,        0x55),
1126         CMN_EVENT_CCRA(rht_alloc,                       0x56),
1127         CMN_EVENT_CCRA(sht_alloc,                       0x57),
1128         CMN_EVENT_CCRA(rdb_alloc,                       0x58),
1129         CMN_EVENT_CCRA(wdb_alloc,                       0x59),
1130         CMN_EVENT_CCRA(ssb_alloc,                       0x5a),
1131
1132         CMN_EVENT_CCHA(rddatbyp,                        0x61),
1133         CMN_EVENT_CCHA(chirsp_up_stall,                 0x62),
1134         CMN_EVENT_CCHA(chidat_up_stall,                 0x63),
1135         CMN_EVENT_CCHA(snppcrd_link0_stall,             0x64),
1136         CMN_EVENT_CCHA(snppcrd_link1_stall,             0x65),
1137         CMN_EVENT_CCHA(snppcrd_link2_stall,             0x66),
1138         CMN_EVENT_CCHA(reqtrk_occ,                      0x67),
1139         CMN_EVENT_CCHA(rdb_occ,                         0x68),
1140         CMN_EVENT_CCHA(rdbyp_occ,                       0x69),
1141         CMN_EVENT_CCHA(wdb_occ,                         0x6a),
1142         CMN_EVENT_CCHA(snptrk_occ,                      0x6b),
1143         CMN_EVENT_CCHA(sdb_occ,                         0x6c),
1144         CMN_EVENT_CCHA(snphaz_occ,                      0x6d),
1145         CMN_EVENT_CCHA(reqtrk_alloc,                    0x6e),
1146         CMN_EVENT_CCHA(rdb_alloc,                       0x6f),
1147         CMN_EVENT_CCHA(rdbyp_alloc,                     0x70),
1148         CMN_EVENT_CCHA(wdb_alloc,                       0x71),
1149         CMN_EVENT_CCHA(snptrk_alloc,                    0x72),
1150         CMN_EVENT_CCHA(sdb_alloc,                       0x73),
1151         CMN_EVENT_CCHA(snphaz_alloc,                    0x74),
1152         CMN_EVENT_CCHA(pb_rhu_req_occ,                  0x75),
1153         CMN_EVENT_CCHA(pb_rhu_req_alloc,                0x76),
1154         CMN_EVENT_CCHA(pb_rhu_pcie_req_occ,             0x77),
1155         CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc,           0x78),
1156         CMN_EVENT_CCHA(pb_pcie_wr_req_occ,              0x79),
1157         CMN_EVENT_CCHA(pb_pcie_wr_req_alloc,            0x7a),
1158         CMN_EVENT_CCHA(pb_pcie_reg_req_occ,             0x7b),
1159         CMN_EVENT_CCHA(pb_pcie_reg_req_alloc,           0x7c),
1160         CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ,            0x7d),
1161         CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc,          0x7e),
1162         CMN_EVENT_CCHA(pb_rhu_dat_occ,                  0x7f),
1163         CMN_EVENT_CCHA(pb_rhu_dat_alloc,                0x80),
1164         CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ,             0x81),
1165         CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc,           0x82),
1166         CMN_EVENT_CCHA(pb_pcie_wr_dat_occ,              0x83),
1167         CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc,            0x84),
1168
1169         CMN_EVENT_CCLA(rx_cxs,                          0x21),
1170         CMN_EVENT_CCLA(tx_cxs,                          0x22),
1171         CMN_EVENT_CCLA(rx_cxs_avg_size,                 0x23),
1172         CMN_EVENT_CCLA(tx_cxs_avg_size,                 0x24),
1173         CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure,        0x25),
1174         CMN_EVENT_CCLA(link_crdbuf_occ,                 0x26),
1175         CMN_EVENT_CCLA(link_crdbuf_alloc,               0x27),
1176         CMN_EVENT_CCLA(pfwd_rcvr_cxs,                   0x28),
1177         CMN_EVENT_CCLA(pfwd_sndr_num_flits,             0x29),
1178         CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd,     0x2a),
1179         CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd,    0x2b),
1180
1181         CMN_EVENT_HNS_HBT(cache_miss,                   0x01),
1182         CMN_EVENT_HNS_HBT(slc_sf_cache_access,          0x02),
1183         CMN_EVENT_HNS_HBT(cache_fill,                   0x03),
1184         CMN_EVENT_HNS_HBT(pocq_retry,                   0x04),
1185         CMN_EVENT_HNS_HBT(pocq_reqs_recvd,              0x05),
1186         CMN_EVENT_HNS_HBT(sf_hit,                       0x06),
1187         CMN_EVENT_HNS_HBT(sf_evictions,                 0x07),
1188         CMN_EVENT_HNS(dir_snoops_sent,                  0x08),
1189         CMN_EVENT_HNS(brd_snoops_sent,                  0x09),
1190         CMN_EVENT_HNS_HBT(slc_eviction,                 0x0a),
1191         CMN_EVENT_HNS_HBT(slc_fill_invalid_way,         0x0b),
1192         CMN_EVENT_HNS(mc_retries_local,                 0x0c),
1193         CMN_EVENT_HNS_SNH(mc_reqs_local,                0x0d),
1194         CMN_EVENT_HNS(qos_hh_retry,                     0x0e),
1195         CMN_EVENT_HNS_OCC(qos_pocq_occupancy,           0x0f),
1196         CMN_EVENT_HNS(pocq_addrhaz,                     0x10),
1197         CMN_EVENT_HNS(pocq_atomic_addrhaz,              0x11),
1198         CMN_EVENT_HNS(ld_st_swp_adq_full,               0x12),
1199         CMN_EVENT_HNS(cmp_adq_full,                     0x13),
1200         CMN_EVENT_HNS(txdat_stall,                      0x14),
1201         CMN_EVENT_HNS(txrsp_stall,                      0x15),
1202         CMN_EVENT_HNS(seq_full,                         0x16),
1203         CMN_EVENT_HNS(seq_hit,                          0x17),
1204         CMN_EVENT_HNS(snp_sent,                         0x18),
1205         CMN_EVENT_HNS(sfbi_dir_snp_sent,                0x19),
1206         CMN_EVENT_HNS(sfbi_brd_snp_sent,                0x1a),
1207         CMN_EVENT_HNS(intv_dirty,                       0x1c),
1208         CMN_EVENT_HNS(stash_snp_sent,                   0x1d),
1209         CMN_EVENT_HNS(stash_data_pull,                  0x1e),
1210         CMN_EVENT_HNS(snp_fwded,                        0x1f),
1211         CMN_EVENT_HNS(atomic_fwd,                       0x20),
1212         CMN_EVENT_HNS(mpam_hardlim,                     0x21),
1213         CMN_EVENT_HNS(mpam_softlim,                     0x22),
1214         CMN_EVENT_HNS(snp_sent_cluster,                 0x23),
1215         CMN_EVENT_HNS(sf_imprecise_evict,               0x24),
1216         CMN_EVENT_HNS(sf_evict_shared_line,             0x25),
1217         CMN_EVENT_HNS_CLS(pocq_class_occup,             0x26),
1218         CMN_EVENT_HNS_CLS(pocq_class_retry,             0x27),
1219         CMN_EVENT_HNS_CLS(class_mc_reqs_local,          0x28),
1220         CMN_EVENT_HNS_CLS(class_cgnt_cmin,              0x29),
1221         CMN_EVENT_HNS_SNT(sn_throttle,                  0x2a),
1222         CMN_EVENT_HNS_SNT(sn_throttle_min,              0x2b),
1223         CMN_EVENT_HNS(sf_precise_to_imprecise,          0x2c),
1224         CMN_EVENT_HNS(snp_intv_cln,                     0x2d),
1225         CMN_EVENT_HNS(nc_excl,                          0x2e),
1226         CMN_EVENT_HNS(excl_mon_ovfl,                    0x2f),
1227         CMN_EVENT_HNS(snp_req_recvd,                    0x30),
1228         CMN_EVENT_HNS(snp_req_byp_pocq,                 0x31),
1229         CMN_EVENT_HNS(dir_ccgha_snp_sent,               0x32),
1230         CMN_EVENT_HNS(brd_ccgha_snp_sent,               0x33),
1231         CMN_EVENT_HNS(ccgha_snp_stall,                  0x34),
1232         CMN_EVENT_HNS(lbt_req_hardlim,                  0x35),
1233         CMN_EVENT_HNS(hbt_req_hardlim,                  0x36),
1234         CMN_EVENT_HNS(sf_reupdate,                      0x37),
1235         CMN_EVENT_HNS(excl_sf_imprecise,                0x38),
1236         CMN_EVENT_HNS(snp_pocq_addrhaz,                 0x39),
1237         CMN_EVENT_HNS(mc_retries_remote,                0x3a),
1238         CMN_EVENT_HNS_SNH(mc_reqs_remote,               0x3b),
1239         CMN_EVENT_HNS_CLS(class_mc_reqs_remote,         0x3c),
1240
1241         NULL
1242 };
1243
1244 static const struct attribute_group arm_cmn_event_attrs_group = {
1245         .name = "events",
1246         .attrs = arm_cmn_event_attrs,
1247         .is_visible = arm_cmn_event_attr_is_visible,
1248 };
1249
1250 static ssize_t arm_cmn_format_show(struct device *dev,
1251                                    struct device_attribute *attr, char *buf)
1252 {
1253         struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
1254         int lo = __ffs(fmt->field), hi = __fls(fmt->field);
1255
1256         if (lo == hi)
1257                 return sysfs_emit(buf, "config:%d\n", lo);
1258
1259         if (!fmt->config)
1260                 return sysfs_emit(buf, "config:%d-%d\n", lo, hi);
1261
1262         return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi);
1263 }
1264
1265 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld)                             \
1266         (&((struct arm_cmn_format_attr[]) {{                            \
1267                 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
1268                 .config = _cfg,                                         \
1269                 .field = _fld,                                          \
1270         }})[0].attr.attr)
1271 #define CMN_FORMAT_ATTR(_name, _fld)    _CMN_FORMAT_ATTR(_name, 0, _fld)
1272
1273 static struct attribute *arm_cmn_format_attrs[] = {
1274         CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
1275         CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
1276         CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
1277         CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
1278         CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
1279
1280         CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
1281         CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
1282         CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
1283         CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
1284         CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
1285
1286         _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
1287         _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
1288
1289         NULL
1290 };
1291
1292 static const struct attribute_group arm_cmn_format_attrs_group = {
1293         .name = "format",
1294         .attrs = arm_cmn_format_attrs,
1295 };
1296
1297 static ssize_t arm_cmn_cpumask_show(struct device *dev,
1298                                     struct device_attribute *attr, char *buf)
1299 {
1300         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1301
1302         return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
1303 }
1304
1305 static struct device_attribute arm_cmn_cpumask_attr =
1306                 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
1307
1308 static ssize_t arm_cmn_identifier_show(struct device *dev,
1309                                        struct device_attribute *attr, char *buf)
1310 {
1311         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1312
1313         return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev);
1314 }
1315
1316 static struct device_attribute arm_cmn_identifier_attr =
1317                 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL);
1318
1319 static struct attribute *arm_cmn_other_attrs[] = {
1320         &arm_cmn_cpumask_attr.attr,
1321         &arm_cmn_identifier_attr.attr,
1322         NULL,
1323 };
1324
1325 static const struct attribute_group arm_cmn_other_attrs_group = {
1326         .attrs = arm_cmn_other_attrs,
1327 };
1328
1329 static const struct attribute_group *arm_cmn_attr_groups[] = {
1330         &arm_cmn_event_attrs_group,
1331         &arm_cmn_format_attrs_group,
1332         &arm_cmn_other_attrs_group,
1333         NULL
1334 };
1335
1336 static int arm_cmn_wp_idx(struct perf_event *event)
1337 {
1338         return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
1339 }
1340
1341 static u32 arm_cmn_wp_config(struct perf_event *event)
1342 {
1343         u32 config;
1344         u32 dev = CMN_EVENT_WP_DEV_SEL(event);
1345         u32 chn = CMN_EVENT_WP_CHN_SEL(event);
1346         u32 grp = CMN_EVENT_WP_GRP(event);
1347         u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
1348         u32 combine = CMN_EVENT_WP_COMBINE(event);
1349         bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;
1350
1351         config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
1352                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
1353                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
1354                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
1355         if (exc)
1356                 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
1357                                       CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
1358         if (combine && !grp)
1359                 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
1360                                       CMN_DTM_WPn_CONFIG_WP_COMBINE;
1361         return config;
1362 }
1363
1364 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
1365 {
1366         if (!cmn->state)
1367                 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
1368         cmn->state |= state;
1369 }
1370
1371 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
1372 {
1373         cmn->state &= ~state;
1374         if (!cmn->state)
1375                 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
1376                                cmn->dtc[0].base + CMN_DT_PMCR);
1377 }
1378
1379 static void arm_cmn_pmu_enable(struct pmu *pmu)
1380 {
1381         arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
1382 }
1383
1384 static void arm_cmn_pmu_disable(struct pmu *pmu)
1385 {
1386         arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
1387 }
1388
1389 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
1390                             bool snapshot)
1391 {
1392         struct arm_cmn_dtm *dtm = NULL;
1393         struct arm_cmn_node *dn;
1394         unsigned int i, offset, dtm_idx;
1395         u64 reg, count = 0;
1396
1397         offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
1398         for_each_hw_dn(hw, dn, i) {
1399                 if (dtm != &cmn->dtms[dn->dtm]) {
1400                         dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1401                         reg = readq_relaxed(dtm->base + offset);
1402                 }
1403                 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1404                 count += (u16)(reg >> (dtm_idx * 16));
1405         }
1406         return count;
1407 }
1408
1409 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
1410 {
1411         u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
1412
1413         writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1414         return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
1415 }
1416
1417 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
1418 {
1419         u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
1420
1421         val = readl_relaxed(dtc->base + pmevcnt);
1422         writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
1423         return val - CMN_COUNTER_INIT;
1424 }
1425
1426 static void arm_cmn_init_counter(struct perf_event *event)
1427 {
1428         struct arm_cmn *cmn = to_cmn(event->pmu);
1429         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1430         unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx);
1431         u64 count;
1432
1433         for (i = 0; hw->dtcs_used & (1U << i); i++) {
1434                 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt);
1435                 cmn->dtc[i].counters[hw->dtc_idx] = event;
1436         }
1437
1438         count = arm_cmn_read_dtm(cmn, hw, false);
1439         local64_set(&event->hw.prev_count, count);
1440 }
1441
1442 static void arm_cmn_event_read(struct perf_event *event)
1443 {
1444         struct arm_cmn *cmn = to_cmn(event->pmu);
1445         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1446         u64 delta, new, prev;
1447         unsigned long flags;
1448         unsigned int i;
1449
1450         if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) {
1451                 i = __ffs(hw->dtcs_used);
1452                 delta = arm_cmn_read_cc(cmn->dtc + i);
1453                 local64_add(delta, &event->count);
1454                 return;
1455         }
1456         new = arm_cmn_read_dtm(cmn, hw, false);
1457         prev = local64_xchg(&event->hw.prev_count, new);
1458
1459         delta = new - prev;
1460
1461         local_irq_save(flags);
1462         for (i = 0; hw->dtcs_used & (1U << i); i++) {
1463                 new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx);
1464                 delta += new << 16;
1465         }
1466         local_irq_restore(flags);
1467         local64_add(delta, &event->count);
1468 }
1469
1470 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,
1471                                     enum cmn_filter_select fsel, u8 occupid)
1472 {
1473         u64 reg;
1474
1475         if (fsel == SEL_NONE)
1476                 return 0;
1477
1478         if (!dn->occupid[fsel].count) {
1479                 dn->occupid[fsel].val = occupid;
1480                 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL,
1481                                  dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) |
1482                       FIELD_PREP(CMN__PMU_SN_HOME_SEL,
1483                                  dn->occupid[SEL_SN_HOME_SEL].val) |
1484                       FIELD_PREP(CMN__PMU_HBT_LBT_SEL,
1485                                  dn->occupid[SEL_HBT_LBT_SEL].val) |
1486                       FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID,
1487                                  dn->occupid[SEL_CLASS_OCCUP_ID].val) |
1488                       FIELD_PREP(CMN__PMU_OCCUP1_ID,
1489                                  dn->occupid[SEL_OCCUP1ID].val);
1490                 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
1491         } else if (dn->occupid[fsel].val != occupid) {
1492                 return -EBUSY;
1493         }
1494         dn->occupid[fsel].count++;
1495         return 0;
1496 }
1497
1498 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,
1499                                      int eventid, bool wide_sel)
1500 {
1501         if (wide_sel) {
1502                 dn->event_w[dtm_idx] = eventid;
1503                 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
1504         } else {
1505                 dn->event[dtm_idx] = eventid;
1506                 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
1507         }
1508 }
1509
1510 static void arm_cmn_event_start(struct perf_event *event, int flags)
1511 {
1512         struct arm_cmn *cmn = to_cmn(event->pmu);
1513         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1514         struct arm_cmn_node *dn;
1515         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1516         int i;
1517
1518         if (type == CMN_TYPE_DTC) {
1519                 i = __ffs(hw->dtcs_used);
1520                 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1521                 cmn->dtc[i].cc_active = true;
1522         } else if (type == CMN_TYPE_WP) {
1523                 int wp_idx = arm_cmn_wp_idx(event);
1524                 u64 val = CMN_EVENT_WP_VAL(event);
1525                 u64 mask = CMN_EVENT_WP_MASK(event);
1526
1527                 for_each_hw_dn(hw, dn, i) {
1528                         void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1529
1530                         writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1531                         writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1532                 }
1533         } else for_each_hw_dn(hw, dn, i) {
1534                 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1535
1536                 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event),
1537                                          hw->wide_sel);
1538         }
1539 }
1540
1541 static void arm_cmn_event_stop(struct perf_event *event, int flags)
1542 {
1543         struct arm_cmn *cmn = to_cmn(event->pmu);
1544         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1545         struct arm_cmn_node *dn;
1546         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1547         int i;
1548
1549         if (type == CMN_TYPE_DTC) {
1550                 i = __ffs(hw->dtcs_used);
1551                 cmn->dtc[i].cc_active = false;
1552         } else if (type == CMN_TYPE_WP) {
1553                 int wp_idx = arm_cmn_wp_idx(event);
1554
1555                 for_each_hw_dn(hw, dn, i) {
1556                         void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1557
1558                         writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1559                         writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1560                 }
1561         } else for_each_hw_dn(hw, dn, i) {
1562                 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1563
1564                 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel);
1565         }
1566
1567         arm_cmn_event_read(event);
1568 }
1569
1570 struct arm_cmn_val {
1571         u8 dtm_count[CMN_MAX_DTMS];
1572         u8 occupid[CMN_MAX_DTMS][SEL_MAX];
1573         u8 wp[CMN_MAX_DTMS][4];
1574         int dtc_count;
1575         bool cycles;
1576 };
1577
1578 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,
1579                                   struct perf_event *event)
1580 {
1581         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1582         struct arm_cmn_node *dn;
1583         enum cmn_node_type type;
1584         int i;
1585
1586         if (is_software_event(event))
1587                 return;
1588
1589         type = CMN_EVENT_TYPE(event);
1590         if (type == CMN_TYPE_DTC) {
1591                 val->cycles = true;
1592                 return;
1593         }
1594
1595         val->dtc_count++;
1596
1597         for_each_hw_dn(hw, dn, i) {
1598                 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1599
1600                 val->dtm_count[dtm]++;
1601
1602                 if (sel > SEL_NONE)
1603                         val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;
1604
1605                 if (type != CMN_TYPE_WP)
1606                         continue;
1607
1608                 wp_idx = arm_cmn_wp_idx(event);
1609                 val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
1610         }
1611 }
1612
1613 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)
1614 {
1615         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1616         struct arm_cmn_node *dn;
1617         struct perf_event *sibling, *leader = event->group_leader;
1618         enum cmn_node_type type;
1619         struct arm_cmn_val *val;
1620         int i, ret = -EINVAL;
1621
1622         if (leader == event)
1623                 return 0;
1624
1625         if (event->pmu != leader->pmu && !is_software_event(leader))
1626                 return -EINVAL;
1627
1628         val = kzalloc(sizeof(*val), GFP_KERNEL);
1629         if (!val)
1630                 return -ENOMEM;
1631
1632         arm_cmn_val_add_event(cmn, val, leader);
1633         for_each_sibling_event(sibling, leader)
1634                 arm_cmn_val_add_event(cmn, val, sibling);
1635
1636         type = CMN_EVENT_TYPE(event);
1637         if (type == CMN_TYPE_DTC) {
1638                 ret = val->cycles ? -EINVAL : 0;
1639                 goto done;
1640         }
1641
1642         if (val->dtc_count == CMN_DT_NUM_COUNTERS)
1643                 goto done;
1644
1645         for_each_hw_dn(hw, dn, i) {
1646                 int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel;
1647
1648                 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)
1649                         goto done;
1650
1651                 if (sel > SEL_NONE && val->occupid[dtm][sel] &&
1652                     val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)
1653                         goto done;
1654
1655                 if (type != CMN_TYPE_WP)
1656                         continue;
1657
1658                 wp_idx = arm_cmn_wp_idx(event);
1659                 if (val->wp[dtm][wp_idx])
1660                         goto done;
1661
1662                 wp_cmb = val->wp[dtm][wp_idx ^ 1];
1663                 if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1)
1664                         goto done;
1665         }
1666
1667         ret = 0;
1668 done:
1669         kfree(val);
1670         return ret;
1671 }
1672
1673 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,
1674                                                  enum cmn_node_type type,
1675                                                  unsigned int eventid)
1676 {
1677         struct arm_cmn_event_attr *e;
1678         enum cmn_model model = arm_cmn_model(cmn);
1679
1680         for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) {
1681                 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr);
1682                 if (e->model & model && e->type == type && e->eventid == eventid)
1683                         return e->fsel;
1684         }
1685         return SEL_NONE;
1686 }
1687
1688
1689 static int arm_cmn_event_init(struct perf_event *event)
1690 {
1691         struct arm_cmn *cmn = to_cmn(event->pmu);
1692         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1693         struct arm_cmn_node *dn;
1694         enum cmn_node_type type;
1695         bool bynodeid;
1696         u16 nodeid, eventid;
1697
1698         if (event->attr.type != event->pmu->type)
1699                 return -ENOENT;
1700
1701         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
1702                 return -EINVAL;
1703
1704         event->cpu = cmn->cpu;
1705         if (event->cpu < 0)
1706                 return -EINVAL;
1707
1708         type = CMN_EVENT_TYPE(event);
1709         /* DTC events (i.e. cycles) already have everything they need */
1710         if (type == CMN_TYPE_DTC)
1711                 return arm_cmn_validate_group(cmn, event);
1712
1713         eventid = CMN_EVENT_EVENTID(event);
1714         /* For watchpoints we need the actual XP node here */
1715         if (type == CMN_TYPE_WP) {
1716                 type = CMN_TYPE_XP;
1717                 /* ...and we need a "real" direction */
1718                 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
1719                         return -EINVAL;
1720                 /* ...but the DTM may depend on which port we're watching */
1721                 if (cmn->multi_dtm)
1722                         hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2;
1723         } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) {
1724                 hw->wide_sel = true;
1725         }
1726
1727         /* This is sufficiently annoying to recalculate, so cache it */
1728         hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid);
1729
1730         bynodeid = CMN_EVENT_BYNODEID(event);
1731         nodeid = CMN_EVENT_NODEID(event);
1732
1733         hw->dn = arm_cmn_node(cmn, type);
1734         if (!hw->dn)
1735                 return -EINVAL;
1736         for (dn = hw->dn; dn->type == type; dn++) {
1737                 if (bynodeid && dn->id != nodeid) {
1738                         hw->dn++;
1739                         continue;
1740                 }
1741                 hw->num_dns++;
1742                 if (bynodeid)
1743                         break;
1744         }
1745
1746         if (!hw->num_dns) {
1747                 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid);
1748
1749                 dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
1750                         nodeid, nid.x, nid.y, nid.port, nid.dev, type);
1751                 return -EINVAL;
1752         }
1753         /*
1754          * Keep assuming non-cycles events count in all DTC domains; turns out
1755          * it's hard to make a worthwhile optimisation around this, short of
1756          * going all-in with domain-local counter allocation as well.
1757          */
1758         hw->dtcs_used = (1U << cmn->num_dtcs) - 1;
1759
1760         return arm_cmn_validate_group(cmn, event);
1761 }
1762
1763 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
1764                                 int i)
1765 {
1766         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1767         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1768
1769         while (i--) {
1770                 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;
1771                 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1772
1773                 if (type == CMN_TYPE_WP)
1774                         dtm->wp_event[arm_cmn_wp_idx(event)] = -1;
1775
1776                 if (hw->filter_sel > SEL_NONE)
1777                         hw->dn[i].occupid[hw->filter_sel].count--;
1778
1779                 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
1780                 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
1781         }
1782         memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
1783
1784         for (i = 0; hw->dtcs_used & (1U << i); i++)
1785                 cmn->dtc[i].counters[hw->dtc_idx] = NULL;
1786 }
1787
1788 static int arm_cmn_event_add(struct perf_event *event, int flags)
1789 {
1790         struct arm_cmn *cmn = to_cmn(event->pmu);
1791         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1792         struct arm_cmn_dtc *dtc = &cmn->dtc[0];
1793         struct arm_cmn_node *dn;
1794         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1795         unsigned int i, dtc_idx, input_sel;
1796
1797         if (type == CMN_TYPE_DTC) {
1798                 i = 0;
1799                 while (cmn->dtc[i].cycles)
1800                         if (++i == cmn->num_dtcs)
1801                                 return -ENOSPC;
1802
1803                 cmn->dtc[i].cycles = event;
1804                 hw->dtc_idx = CMN_DT_NUM_COUNTERS;
1805                 hw->dtcs_used = 1U << i;
1806
1807                 if (flags & PERF_EF_START)
1808                         arm_cmn_event_start(event, 0);
1809                 return 0;
1810         }
1811
1812         /* Grab a free global counter first... */
1813         dtc_idx = 0;
1814         while (dtc->counters[dtc_idx])
1815                 if (++dtc_idx == CMN_DT_NUM_COUNTERS)
1816                         return -ENOSPC;
1817
1818         hw->dtc_idx = dtc_idx;
1819
1820         /* ...then the local counters to feed it. */
1821         for_each_hw_dn(hw, dn, i) {
1822                 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1823                 unsigned int dtm_idx, shift;
1824                 u64 reg;
1825
1826                 dtm_idx = 0;
1827                 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
1828                         if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
1829                                 goto free_dtms;
1830
1831                 if (type == CMN_TYPE_XP) {
1832                         input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
1833                 } else if (type == CMN_TYPE_WP) {
1834                         int tmp, wp_idx = arm_cmn_wp_idx(event);
1835                         u32 cfg = arm_cmn_wp_config(event);
1836
1837                         if (dtm->wp_event[wp_idx] >= 0)
1838                                 goto free_dtms;
1839
1840                         tmp = dtm->wp_event[wp_idx ^ 1];
1841                         if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
1842                                         CMN_EVENT_WP_COMBINE(dtc->counters[tmp]))
1843                                 goto free_dtms;
1844
1845                         input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
1846                         dtm->wp_event[wp_idx] = dtc_idx;
1847                         writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
1848                 } else {
1849                         struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
1850
1851                         if (cmn->multi_dtm)
1852                                 nid.port %= 2;
1853
1854                         input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
1855                                     (nid.port << 4) + (nid.dev << 2);
1856
1857                         if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))
1858                                 goto free_dtms;
1859                 }
1860
1861                 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
1862
1863                 dtm->input_sel[dtm_idx] = input_sel;
1864                 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
1865                 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
1866                 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;
1867                 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
1868                 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;
1869                 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
1870         }
1871
1872         /* Go go go! */
1873         arm_cmn_init_counter(event);
1874
1875         if (flags & PERF_EF_START)
1876                 arm_cmn_event_start(event, 0);
1877
1878         return 0;
1879
1880 free_dtms:
1881         arm_cmn_event_clear(cmn, event, i);
1882         return -ENOSPC;
1883 }
1884
1885 static void arm_cmn_event_del(struct perf_event *event, int flags)
1886 {
1887         struct arm_cmn *cmn = to_cmn(event->pmu);
1888         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1889         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1890
1891         arm_cmn_event_stop(event, PERF_EF_UPDATE);
1892
1893         if (type == CMN_TYPE_DTC)
1894                 cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL;
1895         else
1896                 arm_cmn_event_clear(cmn, event, hw->num_dns);
1897 }
1898
1899 /*
1900  * We stop the PMU for both add and read, to avoid skew across DTM counters.
1901  * In theory we could use snapshots to read without stopping, but then it
1902  * becomes a lot trickier to deal with overlow and racing against interrupts,
1903  * plus it seems they don't work properly on some hardware anyway :(
1904  */
1905 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
1906 {
1907         arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
1908 }
1909
1910 static void arm_cmn_end_txn(struct pmu *pmu)
1911 {
1912         arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
1913 }
1914
1915 static int arm_cmn_commit_txn(struct pmu *pmu)
1916 {
1917         arm_cmn_end_txn(pmu);
1918         return 0;
1919 }
1920
1921 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)
1922 {
1923         unsigned int i;
1924
1925         perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu);
1926         for (i = 0; i < cmn->num_dtcs; i++)
1927                 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
1928         cmn->cpu = cpu;
1929 }
1930
1931 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
1932 {
1933         struct arm_cmn *cmn;
1934         int node;
1935
1936         cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
1937         node = dev_to_node(cmn->dev);
1938         if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)
1939                 arm_cmn_migrate(cmn, cpu);
1940         return 0;
1941 }
1942
1943 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
1944 {
1945         struct arm_cmn *cmn;
1946         unsigned int target;
1947         int node;
1948         cpumask_t mask;
1949
1950         cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
1951         if (cpu != cmn->cpu)
1952                 return 0;
1953
1954         node = dev_to_node(cmn->dev);
1955         if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) &&
1956             cpumask_andnot(&mask, &mask, cpumask_of(cpu)))
1957                 target = cpumask_any(&mask);
1958         else
1959                 target = cpumask_any_but(cpu_online_mask, cpu);
1960         if (target < nr_cpu_ids)
1961                 arm_cmn_migrate(cmn, target);
1962         return 0;
1963 }
1964
1965 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
1966 {
1967         struct arm_cmn_dtc *dtc = dev_id;
1968         irqreturn_t ret = IRQ_NONE;
1969
1970         for (;;) {
1971                 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
1972                 u64 delta;
1973                 int i;
1974
1975                 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
1976                         if (status & (1U << i)) {
1977                                 ret = IRQ_HANDLED;
1978                                 if (WARN_ON(!dtc->counters[i]))
1979                                         continue;
1980                                 delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
1981                                 local64_add(delta, &dtc->counters[i]->count);
1982                         }
1983                 }
1984
1985                 if (status & (1U << CMN_DT_NUM_COUNTERS)) {
1986                         ret = IRQ_HANDLED;
1987                         if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
1988                                 delta = arm_cmn_read_cc(dtc);
1989                                 local64_add(delta, &dtc->cycles->count);
1990                         }
1991                 }
1992
1993                 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
1994
1995                 if (!dtc->irq_friend)
1996                         return ret;
1997                 dtc += dtc->irq_friend;
1998         }
1999 }
2000
2001 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
2002 static int arm_cmn_init_irqs(struct arm_cmn *cmn)
2003 {
2004         int i, j, irq, err;
2005
2006         for (i = 0; i < cmn->num_dtcs; i++) {
2007                 irq = cmn->dtc[i].irq;
2008                 for (j = i; j--; ) {
2009                         if (cmn->dtc[j].irq == irq) {
2010                                 cmn->dtc[j].irq_friend = i - j;
2011                                 goto next;
2012                         }
2013                 }
2014                 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
2015                                        IRQF_NOBALANCING | IRQF_NO_THREAD,
2016                                        dev_name(cmn->dev), &cmn->dtc[i]);
2017                 if (err)
2018                         return err;
2019
2020                 err = irq_set_affinity(irq, cpumask_of(cmn->cpu));
2021                 if (err)
2022                         return err;
2023         next:
2024                 ; /* isn't C great? */
2025         }
2026         return 0;
2027 }
2028
2029 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)
2030 {
2031         int i;
2032
2033         dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
2034         dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
2035         writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
2036         for (i = 0; i < 4; i++) {
2037                 dtm->wp_event[i] = -1;
2038                 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
2039                 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
2040         }
2041 }
2042
2043 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
2044 {
2045         struct arm_cmn_dtc *dtc = cmn->dtc + idx;
2046
2047         dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
2048         dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
2049         if (dtc->irq < 0)
2050                 return dtc->irq;
2051
2052         writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
2053         writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
2054         writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
2055         writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
2056
2057         return 0;
2058 }
2059
2060 static int arm_cmn_node_cmp(const void *a, const void *b)
2061 {
2062         const struct arm_cmn_node *dna = a, *dnb = b;
2063         int cmp;
2064
2065         cmp = dna->type - dnb->type;
2066         if (!cmp)
2067                 cmp = dna->logid - dnb->logid;
2068         return cmp;
2069 }
2070
2071 static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
2072 {
2073         struct arm_cmn_node *dn, *xp;
2074         int dtc_idx = 0;
2075         u8 dtcs_present = (1 << cmn->num_dtcs) - 1;
2076
2077         cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
2078         if (!cmn->dtc)
2079                 return -ENOMEM;
2080
2081         sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
2082
2083         cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
2084
2085         for (dn = cmn->dns; dn->type; dn++) {
2086                 if (dn->type == CMN_TYPE_XP) {
2087                         dn->dtc &= dtcs_present;
2088                         continue;
2089                 }
2090
2091                 xp = arm_cmn_node_to_xp(cmn, dn);
2092                 dn->dtm = xp->dtm;
2093                 if (cmn->multi_dtm)
2094                         dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2;
2095
2096                 if (dn->type == CMN_TYPE_DTC) {
2097                         int err;
2098                         /* We do at least know that a DTC's XP must be in that DTC's domain */
2099                         if (xp->dtc == 0xf)
2100                                 xp->dtc = 1 << dtc_idx;
2101                         err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);
2102                         if (err)
2103                                 return err;
2104                 }
2105
2106                 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
2107                 if (dn->type == CMN_TYPE_RND)
2108                         dn->type = CMN_TYPE_RNI;
2109
2110                 /* We split the RN-I off already, so let the CCLA part match CCLA events */
2111                 if (dn->type == CMN_TYPE_CCLA_RNI)
2112                         dn->type = CMN_TYPE_CCLA;
2113         }
2114
2115         arm_cmn_set_state(cmn, CMN_STATE_DISABLED);
2116
2117         return 0;
2118 }
2119
2120 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
2121 {
2122         int level;
2123         u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
2124
2125         node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
2126         node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
2127         node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
2128
2129         node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
2130
2131         if (node->type == CMN_TYPE_CFG)
2132                 level = 0;
2133         else if (node->type == CMN_TYPE_XP)
2134                 level = 1;
2135         else
2136                 level = 2;
2137
2138         dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
2139                         (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
2140                         node->type, node->logid, offset);
2141 }
2142
2143 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)
2144 {
2145         switch (type) {
2146         case CMN_TYPE_HNP:
2147                 return CMN_TYPE_HNI;
2148         case CMN_TYPE_CCLA_RNI:
2149                 return CMN_TYPE_RNI;
2150         default:
2151                 return CMN_TYPE_INVALID;
2152         }
2153 }
2154
2155 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
2156 {
2157         void __iomem *cfg_region;
2158         struct arm_cmn_node cfg, *dn;
2159         struct arm_cmn_dtm *dtm;
2160         enum cmn_part part;
2161         u16 child_count, child_poff;
2162         u32 xp_offset[CMN_MAX_XPS];
2163         u64 reg;
2164         int i, j;
2165         size_t sz;
2166
2167         arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
2168         if (cfg.type != CMN_TYPE_CFG)
2169                 return -ENODEV;
2170
2171         cfg_region = cmn->base + rgn_offset;
2172
2173         reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
2174         part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
2175         part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
2176         if (cmn->part && cmn->part != part)
2177                 dev_warn(cmn->dev,
2178                          "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n",
2179                          cmn->part, part);
2180         cmn->part = part;
2181         if (!arm_cmn_model(cmn))
2182                 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part);
2183
2184         reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23);
2185         cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
2186
2187         reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
2188         cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;
2189         cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);
2190         cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);
2191
2192         reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
2193         cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);
2194         cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);
2195
2196         reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
2197         child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2198         child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2199
2200         cmn->num_xps = child_count;
2201         cmn->num_dns = cmn->num_xps;
2202
2203         /* Pass 1: visit the XPs, enumerate their children */
2204         for (i = 0; i < cmn->num_xps; i++) {
2205                 reg = readq_relaxed(cfg_region + child_poff + i * 8);
2206                 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
2207
2208                 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
2209                 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2210         }
2211
2212         /*
2213          * Some nodes effectively have two separate types, which we'll handle
2214          * by creating one of each internally. For a (very) safe initial upper
2215          * bound, account for double the number of non-XP nodes.
2216          */
2217         dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,
2218                           sizeof(*dn), GFP_KERNEL);
2219         if (!dn)
2220                 return -ENOMEM;
2221
2222         /* Initial safe upper bound on DTMs for any possible mesh layout */
2223         i = cmn->num_xps;
2224         if (cmn->multi_dtm)
2225                 i += cmn->num_xps + 1;
2226         dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);
2227         if (!dtm)
2228                 return -ENOMEM;
2229
2230         /* Pass 2: now we can actually populate the nodes */
2231         cmn->dns = dn;
2232         cmn->dtms = dtm;
2233         for (i = 0; i < cmn->num_xps; i++) {
2234                 void __iomem *xp_region = cmn->base + xp_offset[i];
2235                 struct arm_cmn_node *xp = dn++;
2236                 unsigned int xp_ports = 0;
2237
2238                 arm_cmn_init_node_info(cmn, xp_offset[i], xp);
2239                 /*
2240                  * Thanks to the order in which XP logical IDs seem to be
2241                  * assigned, we can handily infer the mesh X dimension by
2242                  * looking out for the XP at (0,1) without needing to know
2243                  * the exact node ID format, which we can later derive.
2244                  */
2245                 if (xp->id == (1 << 3))
2246                         cmn->mesh_x = xp->logid;
2247
2248                 if (cmn->part == PART_CMN600)
2249                         xp->dtc = 0xf;
2250                 else
2251                         xp->dtc = 1 << readl_relaxed(xp_region + CMN_DTM_UNIT_INFO);
2252
2253                 xp->dtm = dtm - cmn->dtms;
2254                 arm_cmn_init_dtm(dtm++, xp, 0);
2255                 /*
2256                  * Keeping track of connected ports will let us filter out
2257                  * unnecessary XP events easily. We can also reliably infer the
2258                  * "extra device ports" configuration for the node ID format
2259                  * from this, since in that case we will see at least one XP
2260                  * with port 2 connected, for the HN-D.
2261                  */
2262                 for (int p = 0; p < CMN_MAX_PORTS; p++)
2263                         if (arm_cmn_device_connect_info(cmn, xp, p))
2264                                 xp_ports |= BIT(p);
2265
2266                 if (cmn->multi_dtm && (xp_ports & 0xc))
2267                         arm_cmn_init_dtm(dtm++, xp, 1);
2268                 if (cmn->multi_dtm && (xp_ports & 0x30))
2269                         arm_cmn_init_dtm(dtm++, xp, 2);
2270
2271                 cmn->ports_used |= xp_ports;
2272
2273                 reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
2274                 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2275                 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2276
2277                 for (j = 0; j < child_count; j++) {
2278                         reg = readq_relaxed(xp_region + child_poff + j * 8);
2279                         /*
2280                          * Don't even try to touch anything external, since in general
2281                          * we haven't a clue how to power up arbitrary CHI requesters.
2282                          * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
2283                          * neither of which have any PMU events anyway.
2284                          * (Actually, CXLAs do seem to have grown some events in r1p2,
2285                          * but they don't go to regular XP DTMs, and they depend on
2286                          * secure configuration which we can't easily deal with)
2287                          */
2288                         if (reg & CMN_CHILD_NODE_EXTERNAL) {
2289                                 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
2290                                 continue;
2291                         }
2292
2293                         arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
2294
2295                         switch (dn->type) {
2296                         case CMN_TYPE_DTC:
2297                                 cmn->num_dtcs++;
2298                                 dn++;
2299                                 break;
2300                         /* These guys have PMU events */
2301                         case CMN_TYPE_DVM:
2302                         case CMN_TYPE_HNI:
2303                         case CMN_TYPE_HNF:
2304                         case CMN_TYPE_SBSX:
2305                         case CMN_TYPE_RNI:
2306                         case CMN_TYPE_RND:
2307                         case CMN_TYPE_MTSX:
2308                         case CMN_TYPE_CXRA:
2309                         case CMN_TYPE_CXHA:
2310                         case CMN_TYPE_CCRA:
2311                         case CMN_TYPE_CCHA:
2312                         case CMN_TYPE_CCLA:
2313                         case CMN_TYPE_HNS:
2314                                 dn++;
2315                                 break;
2316                         /* Nothing to see here */
2317                         case CMN_TYPE_MPAM_S:
2318                         case CMN_TYPE_MPAM_NS:
2319                         case CMN_TYPE_RNSAM:
2320                         case CMN_TYPE_CXLA:
2321                         case CMN_TYPE_HNS_MPAM_S:
2322                         case CMN_TYPE_HNS_MPAM_NS:
2323                                 break;
2324                         /*
2325                          * Split "optimised" combination nodes into separate
2326                          * types for the different event sets. Offsetting the
2327                          * base address lets us handle the second pmu_event_sel
2328                          * register via the normal mechanism later.
2329                          */
2330                         case CMN_TYPE_HNP:
2331                         case CMN_TYPE_CCLA_RNI:
2332                                 dn[1] = dn[0];
2333                                 dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL;
2334                                 dn[1].type = arm_cmn_subtype(dn->type);
2335                                 dn += 2;
2336                                 break;
2337                         /* Something has gone horribly wrong */
2338                         default:
2339                                 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
2340                                 return -ENODEV;
2341                         }
2342                 }
2343         }
2344
2345         /* Correct for any nodes we added or skipped */
2346         cmn->num_dns = dn - cmn->dns;
2347
2348         /* Cheeky +1 to help terminate pointer-based iteration later */
2349         sz = (void *)(dn + 1) - (void *)cmn->dns;
2350         dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);
2351         if (dn)
2352                 cmn->dns = dn;
2353
2354         sz = (void *)dtm - (void *)cmn->dtms;
2355         dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);
2356         if (dtm)
2357                 cmn->dtms = dtm;
2358
2359         /*
2360          * If mesh_x wasn't set during discovery then we never saw
2361          * an XP at (0,1), thus we must have an Nx1 configuration.
2362          */
2363         if (!cmn->mesh_x)
2364                 cmn->mesh_x = cmn->num_xps;
2365         cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
2366
2367         /* 1x1 config plays havoc with XP event encodings */
2368         if (cmn->num_xps == 1)
2369                 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
2370
2371         dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev);
2372         reg = cmn->ports_used;
2373         dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n",
2374                 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), &reg,
2375                 cmn->multi_dtm ? ", multi-DTM" : "");
2376
2377         return 0;
2378 }
2379
2380 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
2381 {
2382         struct resource *cfg, *root;
2383
2384         cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2385         if (!cfg)
2386                 return -EINVAL;
2387
2388         root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2389         if (!root)
2390                 return -EINVAL;
2391
2392         if (!resource_contains(cfg, root))
2393                 swap(cfg, root);
2394         /*
2395          * Note that devm_ioremap_resource() is dumb and won't let the platform
2396          * device claim cfg when the ACPI companion device has already claimed
2397          * root within it. But since they *are* already both claimed in the
2398          * appropriate name, we don't really need to do it again here anyway.
2399          */
2400         cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
2401         if (!cmn->base)
2402                 return -ENOMEM;
2403
2404         return root->start - cfg->start;
2405 }
2406
2407 static int arm_cmn600_of_probe(struct device_node *np)
2408 {
2409         u32 rootnode;
2410
2411         return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode;
2412 }
2413
2414 static int arm_cmn_probe(struct platform_device *pdev)
2415 {
2416         struct arm_cmn *cmn;
2417         const char *name;
2418         static atomic_t id;
2419         int err, rootnode, this_id;
2420
2421         cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
2422         if (!cmn)
2423                 return -ENOMEM;
2424
2425         cmn->dev = &pdev->dev;
2426         cmn->part = (unsigned long)device_get_match_data(cmn->dev);
2427         platform_set_drvdata(pdev, cmn);
2428
2429         if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {
2430                 rootnode = arm_cmn600_acpi_probe(pdev, cmn);
2431         } else {
2432                 rootnode = 0;
2433                 cmn->base = devm_platform_ioremap_resource(pdev, 0);
2434                 if (IS_ERR(cmn->base))
2435                         return PTR_ERR(cmn->base);
2436                 if (cmn->part == PART_CMN600)
2437                         rootnode = arm_cmn600_of_probe(pdev->dev.of_node);
2438         }
2439         if (rootnode < 0)
2440                 return rootnode;
2441
2442         err = arm_cmn_discover(cmn, rootnode);
2443         if (err)
2444                 return err;
2445
2446         err = arm_cmn_init_dtcs(cmn);
2447         if (err)
2448                 return err;
2449
2450         err = arm_cmn_init_irqs(cmn);
2451         if (err)
2452                 return err;
2453
2454         cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev));
2455         cmn->pmu = (struct pmu) {
2456                 .module = THIS_MODULE,
2457                 .attr_groups = arm_cmn_attr_groups,
2458                 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
2459                 .task_ctx_nr = perf_invalid_context,
2460                 .pmu_enable = arm_cmn_pmu_enable,
2461                 .pmu_disable = arm_cmn_pmu_disable,
2462                 .event_init = arm_cmn_event_init,
2463                 .add = arm_cmn_event_add,
2464                 .del = arm_cmn_event_del,
2465                 .start = arm_cmn_event_start,
2466                 .stop = arm_cmn_event_stop,
2467                 .read = arm_cmn_event_read,
2468                 .start_txn = arm_cmn_start_txn,
2469                 .commit_txn = arm_cmn_commit_txn,
2470                 .cancel_txn = arm_cmn_end_txn,
2471         };
2472
2473         this_id = atomic_fetch_inc(&id);
2474         name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id);
2475         if (!name)
2476                 return -ENOMEM;
2477
2478         err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
2479         if (err)
2480                 return err;
2481
2482         err = perf_pmu_register(&cmn->pmu, name, -1);
2483         if (err)
2484                 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2485         else
2486                 arm_cmn_debugfs_init(cmn, this_id);
2487
2488         return err;
2489 }
2490
2491 static int arm_cmn_remove(struct platform_device *pdev)
2492 {
2493         struct arm_cmn *cmn = platform_get_drvdata(pdev);
2494
2495         writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
2496
2497         perf_pmu_unregister(&cmn->pmu);
2498         cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2499         debugfs_remove(cmn->debug);
2500         return 0;
2501 }
2502
2503 #ifdef CONFIG_OF
2504 static const struct of_device_id arm_cmn_of_match[] = {
2505         { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 },
2506         { .compatible = "arm,cmn-650" },
2507         { .compatible = "arm,cmn-700" },
2508         { .compatible = "arm,ci-700" },
2509         {}
2510 };
2511 MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
2512 #endif
2513
2514 #ifdef CONFIG_ACPI
2515 static const struct acpi_device_id arm_cmn_acpi_match[] = {
2516         { "ARMHC600", PART_CMN600 },
2517         { "ARMHC650" },
2518         { "ARMHC700" },
2519         {}
2520 };
2521 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
2522 #endif
2523
2524 static struct platform_driver arm_cmn_driver = {
2525         .driver = {
2526                 .name = "arm-cmn",
2527                 .of_match_table = of_match_ptr(arm_cmn_of_match),
2528                 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
2529         },
2530         .probe = arm_cmn_probe,
2531         .remove = arm_cmn_remove,
2532 };
2533
2534 static int __init arm_cmn_init(void)
2535 {
2536         int ret;
2537
2538         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
2539                                       "perf/arm/cmn:online",
2540                                       arm_cmn_pmu_online_cpu,
2541                                       arm_cmn_pmu_offline_cpu);
2542         if (ret < 0)
2543                 return ret;
2544
2545         arm_cmn_hp_state = ret;
2546         arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL);
2547
2548         ret = platform_driver_register(&arm_cmn_driver);
2549         if (ret) {
2550                 cpuhp_remove_multi_state(arm_cmn_hp_state);
2551                 debugfs_remove(arm_cmn_debugfs);
2552         }
2553         return ret;
2554 }
2555
2556 static void __exit arm_cmn_exit(void)
2557 {
2558         platform_driver_unregister(&arm_cmn_driver);
2559         cpuhp_remove_multi_state(arm_cmn_hp_state);
2560         debugfs_remove(arm_cmn_debugfs);
2561 }
2562
2563 module_init(arm_cmn_init);
2564 module_exit(arm_cmn_exit);
2565
2566 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>");
2567 MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
2568 MODULE_LICENSE("GPL v2");