drivers/perf/arm-cmn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2016-2020 Arm Limited
   3 // CMN-600 Coherent Mesh Network PMU driver
   4
   5 #include <linux/acpi.h>
   6 #include <linux/bitfield.h>
   7 #include <linux/bitops.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12 #include <linux/kernel.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/perf_event.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/sort.h>
  20
  21 /* Common register stuff */
  22 #define CMN_NODE_INFO                   0x0000
  23 #define CMN_NI_NODE_TYPE                GENMASK_ULL(15, 0)
  24 #define CMN_NI_NODE_ID                  GENMASK_ULL(31, 16)
  25 #define CMN_NI_LOGICAL_ID               GENMASK_ULL(47, 32)
  26
  27 #define CMN_NODEID_DEVID(reg)           ((reg) & 3)
  28 #define CMN_NODEID_EXT_DEVID(reg)       ((reg) & 1)
  29 #define CMN_NODEID_PID(reg)             (((reg) >> 2) & 1)
  30 #define CMN_NODEID_EXT_PID(reg)         (((reg) >> 1) & 3)
  31 #define CMN_NODEID_1x1_PID(reg)         (((reg) >> 2) & 7)
  32 #define CMN_NODEID_X(reg, bits)         ((reg) >> (3 + (bits)))
  33 #define CMN_NODEID_Y(reg, bits)         (((reg) >> 3) & ((1U << (bits)) - 1))
  34
  35 #define CMN_CHILD_INFO                  0x0080
  36 #define CMN_CI_CHILD_COUNT              GENMASK_ULL(15, 0)
  37 #define CMN_CI_CHILD_PTR_OFFSET         GENMASK_ULL(31, 16)
  38
  39 #define CMN_CHILD_NODE_ADDR             GENMASK(29, 0)
  40 #define CMN_CHILD_NODE_EXTERNAL         BIT(31)
  41
  42 #define CMN_MAX_DIMENSION               12
  43 #define CMN_MAX_XPS                     (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
  44 #define CMN_MAX_DTMS                    (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
  45
  46 /* The CFG node has various info besides the discovery tree */
  47 #define CMN_CFGM_PERIPH_ID_01           0x0008
  48 #define CMN_CFGM_PID0_PART_0            GENMASK_ULL(7, 0)
  49 #define CMN_CFGM_PID1_PART_1            GENMASK_ULL(35, 32)
  50 #define CMN_CFGM_PERIPH_ID_23           0x0010
  51 #define CMN_CFGM_PID2_REVISION          GENMASK_ULL(7, 4)
  52
  53 #define CMN_CFGM_INFO_GLOBAL            0x900
  54 #define CMN_INFO_MULTIPLE_DTM_EN        BIT_ULL(63)
  55 #define CMN_INFO_RSP_VC_NUM             GENMASK_ULL(53, 52)
  56 #define CMN_INFO_DAT_VC_NUM             GENMASK_ULL(51, 50)
  57
  58 #define CMN_CFGM_INFO_GLOBAL_1          0x908
  59 #define CMN_INFO_SNP_VC_NUM             GENMASK_ULL(3, 2)
  60 #define CMN_INFO_REQ_VC_NUM             GENMASK_ULL(1, 0)
  61
  62 /* XPs also have some local topology info which has uses too */
  63 #define CMN_MXP__CONNECT_INFO(p)        (0x0008 + 8 * (p))
  64 #define CMN__CONNECT_INFO_DEVICE_TYPE   GENMASK_ULL(4, 0)
  65
  66 #define CMN_MAX_PORTS                   6
  67 #define CI700_CONNECT_INFO_P2_5_OFFSET  0x10
  68
  69 /* PMU registers occupy the 3rd 4KB page of each node's region */
  70 #define CMN_PMU_OFFSET                  0x2000
  71
  72 /* For most nodes, this is all there is */
  73 #define CMN_PMU_EVENT_SEL               0x000
  74 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL   GENMASK_ULL(44, 42)
  75 #define CMN__PMU_CLASS_OCCUP_ID         GENMASK_ULL(36, 35)
  76 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */
  77 #define CMN__PMU_OCCUP1_ID              GENMASK_ULL(34, 32)
  78
  79 /* HN-Ps are weird... */
  80 #define CMN_HNP_PMU_EVENT_SEL           0x008
  81
  82 /* DTMs live in the PMU space of XP registers */
  83 #define CMN_DTM_WPn(n)                  (0x1A0 + (n) * 0x18)
  84 #define CMN_DTM_WPn_CONFIG(n)           (CMN_DTM_WPn(n) + 0x00)
  85 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM   GENMASK_ULL(20, 19)
  86 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2  GENMASK_ULL(18, 17)
  87 #define CMN_DTM_WPn_CONFIG_WP_COMBINE   BIT(9)
  88 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
  89 #define CMN600_WPn_CONFIG_WP_COMBINE    BIT(6)
  90 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE  BIT(5)
  91 #define CMN_DTM_WPn_CONFIG_WP_GRP       GENMASK_ULL(5, 4)
  92 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL   GENMASK_ULL(3, 1)
  93 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL   BIT(0)
  94 #define CMN_DTM_WPn_VAL(n)              (CMN_DTM_WPn(n) + 0x08)
  95 #define CMN_DTM_WPn_MASK(n)             (CMN_DTM_WPn(n) + 0x10)
  96
  97 #define CMN_DTM_PMU_CONFIG              0x210
  98 #define CMN__PMEVCNT0_INPUT_SEL         GENMASK_ULL(37, 32)
  99 #define CMN__PMEVCNT0_INPUT_SEL_WP      0x00
 100 #define CMN__PMEVCNT0_INPUT_SEL_XP      0x04
 101 #define CMN__PMEVCNT0_INPUT_SEL_DEV     0x10
 102 #define CMN__PMEVCNT0_GLOBAL_NUM        GENMASK_ULL(18, 16)
 103 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n)       ((n) * 4)
 104 #define CMN__PMEVCNT_PAIRED(n)          BIT(4 + (n))
 105 #define CMN__PMEVCNT23_COMBINED         BIT(2)
 106 #define CMN__PMEVCNT01_COMBINED         BIT(1)
 107 #define CMN_DTM_PMU_CONFIG_PMU_EN       BIT(0)
 108
 109 #define CMN_DTM_PMEVCNT                 0x220
 110
 111 #define CMN_DTM_PMEVCNTSR               0x240
 112
 113 #define CMN_DTM_UNIT_INFO               0x0910
 114
 115 #define CMN_DTM_NUM_COUNTERS            4
 116 /* Want more local counters? Why not replicate the whole DTM! Ugh... */
 117 #define CMN_DTM_OFFSET(n)               ((n) * 0x200)
 118
 119 /* The DTC node is where the magic happens */
 120 #define CMN_DT_DTC_CTL                  0x0a00
 121 #define CMN_DT_DTC_CTL_DT_EN            BIT(0)
 122
 123 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
 124 #define _CMN_DT_CNT_REG(n)              ((((n) / 2) * 4 + (n) % 2) * 4)
 125 #define CMN_DT_PMEVCNT(n)               (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
 126 #define CMN_DT_PMCCNTR                  (CMN_PMU_OFFSET + 0x40)
 127
 128 #define CMN_DT_PMEVCNTSR(n)             (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
 129 #define CMN_DT_PMCCNTRSR                (CMN_PMU_OFFSET + 0x90)
 130
 131 #define CMN_DT_PMCR                     (CMN_PMU_OFFSET + 0x100)
 132 #define CMN_DT_PMCR_PMU_EN              BIT(0)
 133 #define CMN_DT_PMCR_CNTR_RST            BIT(5)
 134 #define CMN_DT_PMCR_OVFL_INTR_EN        BIT(6)
 135
 136 #define CMN_DT_PMOVSR                   (CMN_PMU_OFFSET + 0x118)
 137 #define CMN_DT_PMOVSR_CLR               (CMN_PMU_OFFSET + 0x120)
 138
 139 #define CMN_DT_PMSSR                    (CMN_PMU_OFFSET + 0x128)
 140 #define CMN_DT_PMSSR_SS_STATUS(n)       BIT(n)
 141
 142 #define CMN_DT_PMSRR                    (CMN_PMU_OFFSET + 0x130)
 143 #define CMN_DT_PMSRR_SS_REQ             BIT(0)
 144
 145 #define CMN_DT_NUM_COUNTERS             8
 146 #define CMN_MAX_DTCS                    4
 147
 148 /*
 149  * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
 150  * so throwing away one bit to make overflow handling easy is no big deal.
 151  */
 152 #define CMN_COUNTER_INIT                0x80000000
 153 /* Similarly for the 40-bit cycle counter */
 154 #define CMN_CC_INIT                     0x8000000000ULL
 155
 156
 157 /* Event attributes */
 158 #define CMN_CONFIG_TYPE                 GENMASK_ULL(15, 0)
 159 #define CMN_CONFIG_EVENTID              GENMASK_ULL(26, 16)
 160 #define CMN_CONFIG_OCCUPID              GENMASK_ULL(30, 27)
 161 #define CMN_CONFIG_BYNODEID             BIT_ULL(31)
 162 #define CMN_CONFIG_NODEID               GENMASK_ULL(47, 32)
 163
 164 #define CMN_EVENT_TYPE(event)           FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
 165 #define CMN_EVENT_EVENTID(event)        FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
 166 #define CMN_EVENT_OCCUPID(event)        FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
 167 #define CMN_EVENT_BYNODEID(event)       FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
 168 #define CMN_EVENT_NODEID(event)         FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
 169
 170 #define CMN_CONFIG_WP_COMBINE           GENMASK_ULL(30, 27)
 171 #define CMN_CONFIG_WP_DEV_SEL           GENMASK_ULL(50, 48)
 172 #define CMN_CONFIG_WP_CHN_SEL           GENMASK_ULL(55, 51)
 173 /* Note that we don't yet support the tertiary match group on newer IPs */
 174 #define CMN_CONFIG_WP_GRP               BIT_ULL(56)
 175 #define CMN_CONFIG_WP_EXCLUSIVE         BIT_ULL(57)
 176 #define CMN_CONFIG1_WP_VAL              GENMASK_ULL(63, 0)
 177 #define CMN_CONFIG2_WP_MASK             GENMASK_ULL(63, 0)
 178
 179 #define CMN_EVENT_WP_COMBINE(event)     FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
 180 #define CMN_EVENT_WP_DEV_SEL(event)     FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
 181 #define CMN_EVENT_WP_CHN_SEL(event)     FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
 182 #define CMN_EVENT_WP_GRP(event)         FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
 183 #define CMN_EVENT_WP_EXCLUSIVE(event)   FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
 184 #define CMN_EVENT_WP_VAL(event)         FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
 185 #define CMN_EVENT_WP_MASK(event)        FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
 186
 187 /* Made-up event IDs for watchpoint direction */
 188 #define CMN_WP_UP                       0
 189 #define CMN_WP_DOWN                     2
 190
 191
 192 /* Internal values for encoding event support */
 193 enum cmn_model {
 194         CMN600 = 1,
 195         CMN650 = 2,
 196         CMN700 = 4,
 197         CI700 = 8,
 198         /* ...and then we can use bitmap tricks for commonality */
 199         CMN_ANY = -1,
 200         NOT_CMN600 = -2,
 201         CMN_650ON = CMN650 | CMN700,
 202 };
 203
 204 /* Actual part numbers and revision IDs defined by the hardware */
 205 enum cmn_part {
 206         PART_CMN600 = 0x434,
 207         PART_CMN650 = 0x436,
 208         PART_CMN700 = 0x43c,
 209         PART_CI700 = 0x43a,
 210 };
 211
 212 /* CMN-600 r0px shouldn't exist in silicon, thankfully */
 213 enum cmn_revision {
 214         REV_CMN600_R1P0,
 215         REV_CMN600_R1P1,
 216         REV_CMN600_R1P2,
 217         REV_CMN600_R1P3,
 218         REV_CMN600_R2P0,
 219         REV_CMN600_R3P0,
 220         REV_CMN600_R3P1,
 221         REV_CMN650_R0P0 = 0,
 222         REV_CMN650_R1P0,
 223         REV_CMN650_R1P1,
 224         REV_CMN650_R2P0,
 225         REV_CMN650_R1P2,
 226         REV_CMN700_R0P0 = 0,
 227         REV_CMN700_R1P0,
 228         REV_CMN700_R2P0,
 229         REV_CI700_R0P0 = 0,
 230         REV_CI700_R1P0,
 231         REV_CI700_R2P0,
 232 };
 233
 234 enum cmn_node_type {
 235         CMN_TYPE_INVALID,
 236         CMN_TYPE_DVM,
 237         CMN_TYPE_CFG,
 238         CMN_TYPE_DTC,
 239         CMN_TYPE_HNI,
 240         CMN_TYPE_HNF,
 241         CMN_TYPE_XP,
 242         CMN_TYPE_SBSX,
 243         CMN_TYPE_MPAM_S,
 244         CMN_TYPE_MPAM_NS,
 245         CMN_TYPE_RNI,
 246         CMN_TYPE_RND = 0xd,
 247         CMN_TYPE_RNSAM = 0xf,
 248         CMN_TYPE_MTSX,
 249         CMN_TYPE_HNP,
 250         CMN_TYPE_CXRA = 0x100,
 251         CMN_TYPE_CXHA,
 252         CMN_TYPE_CXLA,
 253         CMN_TYPE_CCRA,
 254         CMN_TYPE_CCHA,
 255         CMN_TYPE_CCLA,
 256         CMN_TYPE_CCLA_RNI,
 257         /* Not a real node type */
 258         CMN_TYPE_WP = 0x7770
 259 };
 260
 261 enum cmn_filter_select {
 262         SEL_NONE = -1,
 263         SEL_OCCUP1ID,
 264         SEL_CLASS_OCCUP_ID,
 265         SEL_CBUSY_SNTHROTTLE_SEL,
 266         SEL_MAX
 267 };
 268
 269 struct arm_cmn_node {
 270         void __iomem *pmu_base;
 271         u16 id, logid;
 272         enum cmn_node_type type;
 273
 274         int dtm;
 275         union {
 276                 /* DN/HN-F/CXHA */
 277                 struct {
 278                         u8 val : 4;
 279                         u8 count : 4;
 280                 } occupid[SEL_MAX];
 281                 /* XP */
 282                 u8 dtc;
 283         };
 284         union {
 285                 u8 event[4];
 286                 __le32 event_sel;
 287                 u16 event_w[4];
 288                 __le64 event_sel_w;
 289         };
 290 };
 291
 292 struct arm_cmn_dtm {
 293         void __iomem *base;
 294         u32 pmu_config_low;
 295         union {
 296                 u8 input_sel[4];
 297                 __le32 pmu_config_high;
 298         };
 299         s8 wp_event[4];
 300 };
 301
 302 struct arm_cmn_dtc {
 303         void __iomem *base;
 304         int irq;
 305         int irq_friend;
 306         bool cc_active;
 307
 308         struct perf_event *counters[CMN_DT_NUM_COUNTERS];
 309         struct perf_event *cycles;
 310 };
 311
 312 #define CMN_STATE_DISABLED      BIT(0)
 313 #define CMN_STATE_TXN           BIT(1)
 314
 315 struct arm_cmn {
 316         struct device *dev;
 317         void __iomem *base;
 318         unsigned int state;
 319
 320         enum cmn_revision rev;
 321         enum cmn_part part;
 322         u8 mesh_x;
 323         u8 mesh_y;
 324         u16 num_xps;
 325         u16 num_dns;
 326         bool multi_dtm;
 327         u8 ports_used;
 328         struct {
 329                 unsigned int rsp_vc_num : 2;
 330                 unsigned int dat_vc_num : 2;
 331                 unsigned int snp_vc_num : 2;
 332                 unsigned int req_vc_num : 2;
 333         };
 334
 335         struct arm_cmn_node *xps;
 336         struct arm_cmn_node *dns;
 337
 338         struct arm_cmn_dtm *dtms;
 339         struct arm_cmn_dtc *dtc;
 340         unsigned int num_dtcs;
 341
 342         int cpu;
 343         struct hlist_node cpuhp_node;
 344
 345         struct pmu pmu;
 346         struct dentry *debug;
 347 };
 348
 349 #define to_cmn(p)       container_of(p, struct arm_cmn, pmu)
 350
 351 static int arm_cmn_hp_state;
 352
 353 struct arm_cmn_nodeid {
 354         u8 x;
 355         u8 y;
 356         u8 port;
 357         u8 dev;
 358 };
 359
 360 static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
 361 {
 362         return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2);
 363 }
 364
 365 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id)
 366 {
 367         struct arm_cmn_nodeid nid;
 368
 369         if (cmn->num_xps == 1) {
 370                 nid.x = 0;
 371                 nid.y = 0;
 372                 nid.port = CMN_NODEID_1x1_PID(id);
 373                 nid.dev = CMN_NODEID_DEVID(id);
 374         } else {
 375                 int bits = arm_cmn_xyidbits(cmn);
 376
 377                 nid.x = CMN_NODEID_X(id, bits);
 378                 nid.y = CMN_NODEID_Y(id, bits);
 379                 if (cmn->ports_used & 0xc) {
 380                         nid.port = CMN_NODEID_EXT_PID(id);
 381                         nid.dev = CMN_NODEID_EXT_DEVID(id);
 382                 } else {
 383                         nid.port = CMN_NODEID_PID(id);
 384                         nid.dev = CMN_NODEID_DEVID(id);
 385                 }
 386         }
 387         return nid;
 388 }
 389
 390 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,
 391                                                const struct arm_cmn_node *dn)
 392 {
 393         struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
 394         int xp_idx = cmn->mesh_x * nid.y + nid.x;
 395
 396         return cmn->xps + xp_idx;
 397 }
 398 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
 399                                          enum cmn_node_type type)
 400 {
 401         struct arm_cmn_node *dn;
 402
 403         for (dn = cmn->dns; dn->type; dn++)
 404                 if (dn->type == type)
 405                         return dn;
 406         return NULL;
 407 }
 408
 409 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)
 410 {
 411         switch (cmn->part) {
 412         case PART_CMN600:
 413                 return CMN600;
 414         case PART_CMN650:
 415                 return CMN650;
 416         case PART_CMN700:
 417                 return CMN700;
 418         case PART_CI700:
 419                 return CI700;
 420         default:
 421                 return 0;
 422         };
 423 }
 424
 425 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,
 426                                        const struct arm_cmn_node *xp, int port)
 427 {
 428         int offset = CMN_MXP__CONNECT_INFO(port);
 429
 430         if (port >= 2) {
 431                 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)
 432                         return 0;
 433                 /*
 434                  * CI-700 may have extra ports, but still has the
 435                  * mesh_port_connect_info registers in the way.
 436                  */
 437                 if (cmn->part == PART_CI700)
 438                         offset += CI700_CONNECT_INFO_P2_5_OFFSET;
 439         }
 440
 441         return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset);
 442 }
 443
 444 static struct dentry *arm_cmn_debugfs;
 445
 446 #ifdef CONFIG_DEBUG_FS
 447 static const char *arm_cmn_device_type(u8 type)
 448 {
 449         switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {
 450                 case 0x00: return "        |";
 451                 case 0x01: return "  RN-I  |";
 452                 case 0x02: return "  RN-D  |";
 453                 case 0x04: return " RN-F_B |";
 454                 case 0x05: return "RN-F_B_E|";
 455                 case 0x06: return " RN-F_A |";
 456                 case 0x07: return "RN-F_A_E|";
 457                 case 0x08: return "  HN-T  |";
 458                 case 0x09: return "  HN-I  |";
 459                 case 0x0a: return "  HN-D  |";
 460                 case 0x0b: return "  HN-P  |";
 461                 case 0x0c: return "  SN-F  |";
 462                 case 0x0d: return "  SBSX  |";
 463                 case 0x0e: return "  HN-F  |";
 464                 case 0x0f: return " SN-F_E |";
 465                 case 0x10: return " SN-F_D |";
 466                 case 0x11: return "  CXHA  |";
 467                 case 0x12: return "  CXRA  |";
 468                 case 0x13: return "  CXRH  |";
 469                 case 0x14: return " RN-F_D |";
 470                 case 0x15: return "RN-F_D_E|";
 471                 case 0x16: return " RN-F_C |";
 472                 case 0x17: return "RN-F_C_E|";
 473                 case 0x18: return " RN-F_E |";
 474                 case 0x19: return "RN-F_E_E|";
 475                 case 0x1c: return "  MTSX  |";
 476                 case 0x1d: return "  HN-V  |";
 477                 case 0x1e: return "  CCG   |";
 478                 default:   return "  ????  |";
 479         }
 480 }
 481
 482 static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d)
 483 {
 484         struct arm_cmn *cmn = s->private;
 485         struct arm_cmn_node *dn;
 486
 487         for (dn = cmn->dns; dn->type; dn++) {
 488                 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
 489
 490                 if (dn->type == CMN_TYPE_XP)
 491                         continue;
 492                 /* Ignore the extra components that will overlap on some ports */
 493                 if (dn->type < CMN_TYPE_HNI)
 494                         continue;
 495
 496                 if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d)
 497                         continue;
 498
 499                 seq_printf(s, "   #%-2d  |", dn->logid);
 500                 return;
 501         }
 502         seq_puts(s, "        |");
 503 }
 504
 505 static int arm_cmn_map_show(struct seq_file *s, void *data)
 506 {
 507         struct arm_cmn *cmn = s->private;
 508         int x, y, p, pmax = fls(cmn->ports_used);
 509
 510         seq_puts(s, "     X");
 511         for (x = 0; x < cmn->mesh_x; x++)
 512                 seq_printf(s, "    %d    ", x);
 513         seq_puts(s, "\nY P D+");
 514         y = cmn->mesh_y;
 515         while (y--) {
 516                 int xp_base = cmn->mesh_x * y;
 517                 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION];
 518
 519                 for (x = 0; x < cmn->mesh_x; x++)
 520                         seq_puts(s, "--------+");
 521
 522                 seq_printf(s, "\n%d    |", y);
 523                 for (x = 0; x < cmn->mesh_x; x++) {
 524                         struct arm_cmn_node *xp = cmn->xps + xp_base + x;
 525
 526                         for (p = 0; p < CMN_MAX_PORTS; p++)
 527                                 port[p][x] = arm_cmn_device_connect_info(cmn, xp, p);
 528                         seq_printf(s, " XP #%-2d |", xp_base + x);
 529                 }
 530
 531                 seq_puts(s, "\n     |");
 532                 for (x = 0; x < cmn->mesh_x; x++) {
 533                         u8 dtc = cmn->xps[xp_base + x].dtc;
 534
 535                         if (dtc & (dtc - 1))
 536                                 seq_puts(s, " DTC ?? |");
 537                         else
 538                                 seq_printf(s, " DTC %ld  |", __ffs(dtc));
 539                 }
 540                 seq_puts(s, "\n     |");
 541                 for (x = 0; x < cmn->mesh_x; x++)
 542                         seq_puts(s, "........|");
 543
 544                 for (p = 0; p < pmax; p++) {
 545                         seq_printf(s, "\n  %d  |", p);
 546                         for (x = 0; x < cmn->mesh_x; x++)
 547                                 seq_puts(s, arm_cmn_device_type(port[p][x]));
 548                         seq_puts(s, "\n    0|");
 549                         for (x = 0; x < cmn->mesh_x; x++)
 550                                 arm_cmn_show_logid(s, x, y, p, 0);
 551                         seq_puts(s, "\n    1|");
 552                         for (x = 0; x < cmn->mesh_x; x++)
 553                                 arm_cmn_show_logid(s, x, y, p, 1);
 554                 }
 555                 seq_puts(s, "\n-----+");
 556         }
 557         for (x = 0; x < cmn->mesh_x; x++)
 558                 seq_puts(s, "--------+");
 559         seq_puts(s, "\n");
 560         return 0;
 561 }
 562 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map);
 563
 564 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)
 565 {
 566         const char *name  = "map";
 567
 568         if (id > 0)
 569                 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id);
 570         if (!name)
 571                 return;
 572
 573         cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops);
 574 }
 575 #else
 576 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}
 577 #endif
 578
 579 struct arm_cmn_hw_event {
 580         struct arm_cmn_node *dn;
 581         u64 dtm_idx[4];
 582         unsigned int dtc_idx;
 583         u8 dtcs_used;
 584         u8 num_dns;
 585         u8 dtm_offset;
 586         bool wide_sel;
 587         enum cmn_filter_select filter_sel;
 588 };
 589
 590 #define for_each_hw_dn(hw, dn, i) \
 591         for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
 592
 593 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
 594 {
 595         BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
 596         return (struct arm_cmn_hw_event *)&event->hw;
 597 }
 598
 599 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
 600 {
 601         x[pos / 32] |= (u64)val << ((pos % 32) * 2);
 602 }
 603
 604 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
 605 {
 606         return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
 607 }
 608
 609 struct arm_cmn_event_attr {
 610         struct device_attribute attr;
 611         enum cmn_model model;
 612         enum cmn_node_type type;
 613         enum cmn_filter_select fsel;
 614         u16 eventid;
 615         u8 occupid;
 616 };
 617
 618 struct arm_cmn_format_attr {
 619         struct device_attribute attr;
 620         u64 field;
 621         int config;
 622 };
 623
 624 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\
 625         (&((struct arm_cmn_event_attr[]) {{                             \
 626                 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL),  \
 627                 .model = _model,                                        \
 628                 .type = _type,                                          \
 629                 .eventid = _eventid,                                    \
 630                 .occupid = _occupid,                                    \
 631                 .fsel = _fsel,                                          \
 632         }})[0].attr.attr)
 633 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid)                  \
 634         _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE)
 635
 636 static ssize_t arm_cmn_event_show(struct device *dev,
 637                                   struct device_attribute *attr, char *buf)
 638 {
 639         struct arm_cmn_event_attr *eattr;
 640
 641         eattr = container_of(attr, typeof(*eattr), attr);
 642
 643         if (eattr->type == CMN_TYPE_DTC)
 644                 return sysfs_emit(buf, "type=0x%x\n", eattr->type);
 645
 646         if (eattr->type == CMN_TYPE_WP)
 647                 return sysfs_emit(buf,
 648                                   "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
 649                                   eattr->type, eattr->eventid);
 650
 651         if (eattr->fsel > SEL_NONE)
 652                 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
 653                                   eattr->type, eattr->eventid, eattr->occupid);
 654
 655         return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type,
 656                           eattr->eventid);
 657 }
 658
 659 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
 660                                              struct attribute *attr,
 661                                              int unused)
 662 {
 663         struct device *dev = kobj_to_dev(kobj);
 664         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
 665         struct arm_cmn_event_attr *eattr;
 666         enum cmn_node_type type;
 667         u16 eventid;
 668
 669         eattr = container_of(attr, typeof(*eattr), attr.attr);
 670
 671         if (!(eattr->model & arm_cmn_model(cmn)))
 672                 return 0;
 673
 674         type = eattr->type;
 675         eventid = eattr->eventid;
 676
 677         /* Watchpoints aren't nodes, so avoid confusion */
 678         if (type == CMN_TYPE_WP)
 679                 return attr->mode;
 680
 681         /* Hide XP events for unused interfaces/channels */
 682         if (type == CMN_TYPE_XP) {
 683                 unsigned int intf = (eventid >> 2) & 7;
 684                 unsigned int chan = eventid >> 5;
 685
 686                 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
 687                         return 0;
 688
 689                 if (chan == 4 && cmn->part == PART_CMN600)
 690                         return 0;
 691
 692                 if ((chan == 5 && cmn->rsp_vc_num < 2) ||
 693                     (chan == 6 && cmn->dat_vc_num < 2) ||
 694                     (chan == 7 && cmn->snp_vc_num < 2) ||
 695                     (chan == 8 && cmn->req_vc_num < 2))
 696                         return 0;
 697         }
 698
 699         /* Revision-specific differences */
 700         if (cmn->part == PART_CMN600) {
 701                 if (cmn->rev < REV_CMN600_R1P3) {
 702                         if (type == CMN_TYPE_CXRA && eventid > 0x10)
 703                                 return 0;
 704                 }
 705                 if (cmn->rev < REV_CMN600_R1P2) {
 706                         if (type == CMN_TYPE_HNF && eventid == 0x1b)
 707                                 return 0;
 708                         if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)
 709                                 return 0;
 710                 }
 711         } else if (cmn->part == PART_CMN650) {
 712                 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {
 713                         if (type == CMN_TYPE_HNF && eventid > 0x22)
 714                                 return 0;
 715                         if (type == CMN_TYPE_SBSX && eventid == 0x17)
 716                                 return 0;
 717                         if (type == CMN_TYPE_RNI && eventid > 0x10)
 718                                 return 0;
 719                 }
 720         } else if (cmn->part == PART_CMN700) {
 721                 if (cmn->rev < REV_CMN700_R2P0) {
 722                         if (type == CMN_TYPE_HNF && eventid > 0x2c)
 723                                 return 0;
 724                         if (type == CMN_TYPE_CCHA && eventid > 0x74)
 725                                 return 0;
 726                         if (type == CMN_TYPE_CCLA && eventid > 0x27)
 727                                 return 0;
 728                 }
 729                 if (cmn->rev < REV_CMN700_R1P0) {
 730                         if (type == CMN_TYPE_HNF && eventid > 0x2b)
 731                                 return 0;
 732                 }
 733         }
 734
 735         if (!arm_cmn_node(cmn, type))
 736                 return 0;
 737
 738         return attr->mode;
 739 }
 740
 741 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel)    \
 742         _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel)
 743 #define CMN_EVENT_DTC(_name)                                    \
 744         CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0)
 745 #define _CMN_EVENT_HNF(_model, _name, _event, _occup, _fsel)            \
 746         _CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event, _occup, _fsel)
 747 #define CMN_EVENT_HNI(_name, _event)                            \
 748         CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event)
 749 #define CMN_EVENT_HNP(_name, _event)                            \
 750         CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event)
 751 #define __CMN_EVENT_XP(_name, _event)                           \
 752         CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event)
 753 #define CMN_EVENT_SBSX(_model, _name, _event)                   \
 754         CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event)
 755 #define CMN_EVENT_RNID(_model, _name, _event)                   \
 756         CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event)
 757 #define CMN_EVENT_MTSX(_name, _event)                           \
 758         CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event)
 759 #define CMN_EVENT_CXRA(_model, _name, _event)                           \
 760         CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event)
 761 #define CMN_EVENT_CXHA(_name, _event)                           \
 762         CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event)
 763 #define CMN_EVENT_CCRA(_name, _event)                           \
 764         CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event)
 765 #define CMN_EVENT_CCHA(_name, _event)                           \
 766         CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event)
 767 #define CMN_EVENT_CCLA(_name, _event)                           \
 768         CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event)
 769 #define CMN_EVENT_CCLA_RNI(_name, _event)                               \
 770         CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event)
 771
 772 #define CMN_EVENT_DVM(_model, _name, _event)                    \
 773         _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE)
 774 #define CMN_EVENT_DVM_OCC(_model, _name, _event)                        \
 775         _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID),   \
 776         _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \
 777         _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID)
 778 #define CMN_EVENT_HNF(_model, _name, _event)                    \
 779         _CMN_EVENT_HNF(_model, _name, _event, 0, SEL_NONE)
 780 #define CMN_EVENT_HNF_CLS(_model, _name, _event)                        \
 781         _CMN_EVENT_HNF(_model, _name##_class0, _event, 0, SEL_CLASS_OCCUP_ID), \
 782         _CMN_EVENT_HNF(_model, _name##_class1, _event, 1, SEL_CLASS_OCCUP_ID), \
 783         _CMN_EVENT_HNF(_model, _name##_class2, _event, 2, SEL_CLASS_OCCUP_ID), \
 784         _CMN_EVENT_HNF(_model, _name##_class3, _event, 3, SEL_CLASS_OCCUP_ID)
 785 #define CMN_EVENT_HNF_SNT(_model, _name, _event)                        \
 786         _CMN_EVENT_HNF(_model, _name##_all, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \
 787         _CMN_EVENT_HNF(_model, _name##_group0_read, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \
 788         _CMN_EVENT_HNF(_model, _name##_group0_write, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \
 789         _CMN_EVENT_HNF(_model, _name##_group1_read, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \
 790         _CMN_EVENT_HNF(_model, _name##_group1_write, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \
 791         _CMN_EVENT_HNF(_model, _name##_read, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \
 792         _CMN_EVENT_HNF(_model, _name##_write, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL)
 793
 794 #define _CMN_EVENT_XP(_name, _event)                            \
 795         __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)),         \
 796         __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)),         \
 797         __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)),         \
 798         __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)),         \
 799         __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)),        \
 800         __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)),        \
 801         __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)),        \
 802         __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2))
 803
 804 /* Good thing there are only 3 fundamental XP events... */
 805 #define CMN_EVENT_XP(_name, _event)                             \
 806         _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)),        \
 807         _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)),        \
 808         _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)),        \
 809         _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)),        \
 810         _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)),        \
 811         _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)),       \
 812         _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)),       \
 813         _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)),       \
 814         _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5))
 815
 816
 817 static struct attribute *arm_cmn_event_attrs[] = {
 818         CMN_EVENT_DTC(cycles),
 819
 820         /*
 821          * DVM node events conflict with HN-I events in the equivalent PMU
 822          * slot, but our lazy short-cut of using the DTM counter index for
 823          * the PMU index as well happens to avoid that by construction.
 824          */
 825         CMN_EVENT_DVM(CMN600, rxreq_dvmop,              0x01),
 826         CMN_EVENT_DVM(CMN600, rxreq_dvmsync,            0x02),
 827         CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03),
 828         CMN_EVENT_DVM(CMN600, rxreq_retried,            0x04),
 829         CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy,  0x05),
 830         CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi,           0x01),
 831         CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi,            0x02),
 832         CMN_EVENT_DVM(NOT_CMN600, dvmop_pici,           0x03),
 833         CMN_EVENT_DVM(NOT_CMN600, dvmop_vici,           0x04),
 834         CMN_EVENT_DVM(NOT_CMN600, dvmsync,              0x05),
 835         CMN_EVENT_DVM(NOT_CMN600, vmid_filtered,        0x06),
 836         CMN_EVENT_DVM(NOT_CMN600, rndop_filtered,       0x07),
 837         CMN_EVENT_DVM(NOT_CMN600, retry,                0x08),
 838         CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv,          0x09),
 839         CMN_EVENT_DVM(NOT_CMN600, txsnp_stall,          0x0a),
 840         CMN_EVENT_DVM(NOT_CMN600, trkfull,              0x0b),
 841         CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy,    0x0c),
 842         CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha,   0x0d),
 843         CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn,    0x0e),
 844         CMN_EVENT_DVM(CMN700, trk_alloc,                0x0f),
 845         CMN_EVENT_DVM(CMN700, trk_cxha_alloc,           0x10),
 846         CMN_EVENT_DVM(CMN700, trk_pdn_alloc,            0x11),
 847         CMN_EVENT_DVM(CMN700, txsnp_stall_limit,        0x12),
 848         CMN_EVENT_DVM(CMN700, rxsnp_stall_starv,        0x13),
 849         CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op,      0x14),
 850
 851         CMN_EVENT_HNF(CMN_ANY, cache_miss,              0x01),
 852         CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access,     0x02),
 853         CMN_EVENT_HNF(CMN_ANY, cache_fill,              0x03),
 854         CMN_EVENT_HNF(CMN_ANY, pocq_retry,              0x04),
 855         CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd,         0x05),
 856         CMN_EVENT_HNF(CMN_ANY, sf_hit,                  0x06),
 857         CMN_EVENT_HNF(CMN_ANY, sf_evictions,            0x07),
 858         CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent,         0x08),
 859         CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent,         0x09),
 860         CMN_EVENT_HNF(CMN_ANY, slc_eviction,            0x0a),
 861         CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way,    0x0b),
 862         CMN_EVENT_HNF(CMN_ANY, mc_retries,              0x0c),
 863         CMN_EVENT_HNF(CMN_ANY, mc_reqs,                 0x0d),
 864         CMN_EVENT_HNF(CMN_ANY, qos_hh_retry,            0x0e),
 865         _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_all, 0x0f, 0, SEL_OCCUP1ID),
 866         _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_read, 0x0f, 1, SEL_OCCUP1ID),
 867         _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_write, 0x0f, 2, SEL_OCCUP1ID),
 868         _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_atomic, 0x0f, 3, SEL_OCCUP1ID),
 869         _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_stash, 0x0f, 4, SEL_OCCUP1ID),
 870         CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz,            0x10),
 871         CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz,     0x11),
 872         CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full,      0x12),
 873         CMN_EVENT_HNF(CMN_ANY, cmp_adq_full,            0x13),
 874         CMN_EVENT_HNF(CMN_ANY, txdat_stall,             0x14),
 875         CMN_EVENT_HNF(CMN_ANY, txrsp_stall,             0x15),
 876         CMN_EVENT_HNF(CMN_ANY, seq_full,                0x16),
 877         CMN_EVENT_HNF(CMN_ANY, seq_hit,                 0x17),
 878         CMN_EVENT_HNF(CMN_ANY, snp_sent,                0x18),
 879         CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent,       0x19),
 880         CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent,       0x1a),
 881         CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk,          0x1b),
 882         CMN_EVENT_HNF(CMN_ANY, intv_dirty,              0x1c),
 883         CMN_EVENT_HNF(CMN_ANY, stash_snp_sent,          0x1d),
 884         CMN_EVENT_HNF(CMN_ANY, stash_data_pull,         0x1e),
 885         CMN_EVENT_HNF(CMN_ANY, snp_fwded,               0x1f),
 886         CMN_EVENT_HNF(NOT_CMN600, atomic_fwd,           0x20),
 887         CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim,         0x21),
 888         CMN_EVENT_HNF(NOT_CMN600, mpam_softlim,         0x22),
 889         CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster,      0x23),
 890         CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict,    0x24),
 891         CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line,  0x25),
 892         CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup,     0x26),
 893         CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry,     0x27),
 894         CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs,        0x28),
 895         CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin,      0x29),
 896         CMN_EVENT_HNF_SNT(CMN700, sn_throttle,          0x2a),
 897         CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min,      0x2b),
 898         CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise,  0x2c),
 899         CMN_EVENT_HNF(CMN700, snp_intv_cln,             0x2d),
 900         CMN_EVENT_HNF(CMN700, nc_excl,                  0x2e),
 901         CMN_EVENT_HNF(CMN700, excl_mon_ovfl,            0x2f),
 902
 903         CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl,              0x20),
 904         CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl,              0x21),
 905         CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl,              0x22),
 906         CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl,              0x23),
 907         CMN_EVENT_HNI(wdb_occ_cnt_ovfl,                 0x24),
 908         CMN_EVENT_HNI(rrt_rd_alloc,                     0x25),
 909         CMN_EVENT_HNI(rrt_wr_alloc,                     0x26),
 910         CMN_EVENT_HNI(rdt_rd_alloc,                     0x27),
 911         CMN_EVENT_HNI(rdt_wr_alloc,                     0x28),
 912         CMN_EVENT_HNI(wdb_alloc,                        0x29),
 913         CMN_EVENT_HNI(txrsp_retryack,                   0x2a),
 914         CMN_EVENT_HNI(arvalid_no_arready,               0x2b),
 915         CMN_EVENT_HNI(arready_no_arvalid,               0x2c),
 916         CMN_EVENT_HNI(awvalid_no_awready,               0x2d),
 917         CMN_EVENT_HNI(awready_no_awvalid,               0x2e),
 918         CMN_EVENT_HNI(wvalid_no_wready,                 0x2f),
 919         CMN_EVENT_HNI(txdat_stall,                      0x30),
 920         CMN_EVENT_HNI(nonpcie_serialization,            0x31),
 921         CMN_EVENT_HNI(pcie_serialization,               0x32),
 922
 923         /*
 924          * HN-P events squat on top of the HN-I similarly to DVM events, except
 925          * for being crammed into the same physical node as well. And of course
 926          * where would the fun be if the same events were in the same order...
 927          */
 928         CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl,              0x01),
 929         CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl,              0x02),
 930         CMN_EVENT_HNP(wdb_occ_cnt_ovfl,                 0x03),
 931         CMN_EVENT_HNP(rrt_wr_alloc,                     0x04),
 932         CMN_EVENT_HNP(rdt_wr_alloc,                     0x05),
 933         CMN_EVENT_HNP(wdb_alloc,                        0x06),
 934         CMN_EVENT_HNP(awvalid_no_awready,               0x07),
 935         CMN_EVENT_HNP(awready_no_awvalid,               0x08),
 936         CMN_EVENT_HNP(wvalid_no_wready,                 0x09),
 937         CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl,              0x11),
 938         CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl,              0x12),
 939         CMN_EVENT_HNP(rrt_rd_alloc,                     0x13),
 940         CMN_EVENT_HNP(rdt_rd_alloc,                     0x14),
 941         CMN_EVENT_HNP(arvalid_no_arready,               0x15),
 942         CMN_EVENT_HNP(arready_no_arvalid,               0x16),
 943
 944         CMN_EVENT_XP(txflit_valid,                      0x01),
 945         CMN_EVENT_XP(txflit_stall,                      0x02),
 946         CMN_EVENT_XP(partial_dat_flit,                  0x03),
 947         /* We treat watchpoints as a special made-up class of XP events */
 948         CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP),
 949         CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN),
 950
 951         CMN_EVENT_SBSX(CMN_ANY, rd_req,                 0x01),
 952         CMN_EVENT_SBSX(CMN_ANY, wr_req,                 0x02),
 953         CMN_EVENT_SBSX(CMN_ANY, cmo_req,                0x03),
 954         CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack,         0x04),
 955         CMN_EVENT_SBSX(CMN_ANY, txdat_flitv,            0x05),
 956         CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv,            0x06),
 957         CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11),
 958         CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12),
 959         CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13),
 960         CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl,       0x14),
 961         CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15),
 962         CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16),
 963         CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl,    0x17),
 964         CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready,     0x21),
 965         CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready,     0x22),
 966         CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready,       0x23),
 967         CMN_EVENT_SBSX(CMN_ANY, txdat_stall,            0x24),
 968         CMN_EVENT_SBSX(CMN_ANY, txrsp_stall,            0x25),
 969
 970         CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats,         0x01),
 971         CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats,         0x02),
 972         CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats,         0x03),
 973         CMN_EVENT_RNID(CMN_ANY, rxdat_flits,            0x04),
 974         CMN_EVENT_RNID(CMN_ANY, txdat_flits,            0x05),
 975         CMN_EVENT_RNID(CMN_ANY, txreq_flits_total,      0x06),
 976         CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried,    0x07),
 977         CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl,           0x08),
 978         CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl,           0x09),
 979         CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed,   0x0a),
 980         CMN_EVENT_RNID(CMN_ANY, wrcancel_sent,          0x0b),
 981         CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats,         0x0c),
 982         CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats,         0x0d),
 983         CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats,         0x0e),
 984         CMN_EVENT_RNID(CMN_ANY, rrt_alloc,              0x0f),
 985         CMN_EVENT_RNID(CMN_ANY, wrt_alloc,              0x10),
 986         CMN_EVENT_RNID(CMN600, rdb_unord,               0x11),
 987         CMN_EVENT_RNID(CMN600, rdb_replay,              0x12),
 988         CMN_EVENT_RNID(CMN600, rdb_hybrid,              0x13),
 989         CMN_EVENT_RNID(CMN600, rdb_ord,                 0x14),
 990         CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl,       0x11),
 991         CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl,       0x12),
 992         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13),
 993         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14),
 994         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15),
 995         CMN_EVENT_RNID(NOT_CMN600, wrt_throttled,       0x16),
 996         CMN_EVENT_RNID(CMN700, ldb_full,                0x17),
 997         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18),
 998         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19),
 999         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a),
1000         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b),
1001         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c),
1002         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d),
1003         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e),
1004         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f),
1005         CMN_EVENT_RNID(CMN700, rrt_burst_alloc,         0x20),
1006         CMN_EVENT_RNID(CMN700, awid_hash,               0x21),
1007         CMN_EVENT_RNID(CMN700, atomic_alloc,            0x22),
1008         CMN_EVENT_RNID(CMN700, atomic_occ_ovfl,         0x23),
1009
1010         CMN_EVENT_MTSX(tc_lookup,                       0x01),
1011         CMN_EVENT_MTSX(tc_fill,                         0x02),
1012         CMN_EVENT_MTSX(tc_miss,                         0x03),
1013         CMN_EVENT_MTSX(tdb_forward,                     0x04),
1014         CMN_EVENT_MTSX(tcq_hazard,                      0x05),
1015         CMN_EVENT_MTSX(tcq_rd_alloc,                    0x06),
1016         CMN_EVENT_MTSX(tcq_wr_alloc,                    0x07),
1017         CMN_EVENT_MTSX(tcq_cmo_alloc,                   0x08),
1018         CMN_EVENT_MTSX(axi_rd_req,                      0x09),
1019         CMN_EVENT_MTSX(axi_wr_req,                      0x0a),
1020         CMN_EVENT_MTSX(tcq_occ_cnt_ovfl,                0x0b),
1021         CMN_EVENT_MTSX(tdb_occ_cnt_ovfl,                0x0c),
1022
1023         CMN_EVENT_CXRA(CMN_ANY, rht_occ,                0x01),
1024         CMN_EVENT_CXRA(CMN_ANY, sht_occ,                0x02),
1025         CMN_EVENT_CXRA(CMN_ANY, rdb_occ,                0x03),
1026         CMN_EVENT_CXRA(CMN_ANY, wdb_occ,                0x04),
1027         CMN_EVENT_CXRA(CMN_ANY, ssb_occ,                0x05),
1028         CMN_EVENT_CXRA(CMN_ANY, snp_bcasts,             0x06),
1029         CMN_EVENT_CXRA(CMN_ANY, req_chains,             0x07),
1030         CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen,       0x08),
1031         CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls,          0x09),
1032         CMN_EVENT_CXRA(CMN_ANY, chidat_stalls,          0x0a),
1033         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b),
1034         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c),
1035         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d),
1036         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e),
1037         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f),
1038         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10),
1039         CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11),
1040         CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12),
1041         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13),
1042         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14),
1043         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15),
1044
1045         CMN_EVENT_CXHA(rddatbyp,                        0x21),
1046         CMN_EVENT_CXHA(chirsp_up_stall,                 0x22),
1047         CMN_EVENT_CXHA(chidat_up_stall,                 0x23),
1048         CMN_EVENT_CXHA(snppcrd_link0_stall,             0x24),
1049         CMN_EVENT_CXHA(snppcrd_link1_stall,             0x25),
1050         CMN_EVENT_CXHA(snppcrd_link2_stall,             0x26),
1051         CMN_EVENT_CXHA(reqtrk_occ,                      0x27),
1052         CMN_EVENT_CXHA(rdb_occ,                         0x28),
1053         CMN_EVENT_CXHA(rdbyp_occ,                       0x29),
1054         CMN_EVENT_CXHA(wdb_occ,                         0x2a),
1055         CMN_EVENT_CXHA(snptrk_occ,                      0x2b),
1056         CMN_EVENT_CXHA(sdb_occ,                         0x2c),
1057         CMN_EVENT_CXHA(snphaz_occ,                      0x2d),
1058
1059         CMN_EVENT_CCRA(rht_occ,                         0x41),
1060         CMN_EVENT_CCRA(sht_occ,                         0x42),
1061         CMN_EVENT_CCRA(rdb_occ,                         0x43),
1062         CMN_EVENT_CCRA(wdb_occ,                         0x44),
1063         CMN_EVENT_CCRA(ssb_occ,                         0x45),
1064         CMN_EVENT_CCRA(snp_bcasts,                      0x46),
1065         CMN_EVENT_CCRA(req_chains,                      0x47),
1066         CMN_EVENT_CCRA(req_chain_avglen,                0x48),
1067         CMN_EVENT_CCRA(chirsp_stalls,                   0x49),
1068         CMN_EVENT_CCRA(chidat_stalls,                   0x4a),
1069         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0,         0x4b),
1070         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1,         0x4c),
1071         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2,         0x4d),
1072         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0,         0x4e),
1073         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1,         0x4f),
1074         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2,         0x50),
1075         CMN_EVENT_CCRA(external_chirsp_stalls,          0x51),
1076         CMN_EVENT_CCRA(external_chidat_stalls,          0x52),
1077         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0,        0x53),
1078         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1,        0x54),
1079         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2,        0x55),
1080         CMN_EVENT_CCRA(rht_alloc,                       0x56),
1081         CMN_EVENT_CCRA(sht_alloc,                       0x57),
1082         CMN_EVENT_CCRA(rdb_alloc,                       0x58),
1083         CMN_EVENT_CCRA(wdb_alloc,                       0x59),
1084         CMN_EVENT_CCRA(ssb_alloc,                       0x5a),
1085
1086         CMN_EVENT_CCHA(rddatbyp,                        0x61),
1087         CMN_EVENT_CCHA(chirsp_up_stall,                 0x62),
1088         CMN_EVENT_CCHA(chidat_up_stall,                 0x63),
1089         CMN_EVENT_CCHA(snppcrd_link0_stall,             0x64),
1090         CMN_EVENT_CCHA(snppcrd_link1_stall,             0x65),
1091         CMN_EVENT_CCHA(snppcrd_link2_stall,             0x66),
1092         CMN_EVENT_CCHA(reqtrk_occ,                      0x67),
1093         CMN_EVENT_CCHA(rdb_occ,                         0x68),
1094         CMN_EVENT_CCHA(rdbyp_occ,                       0x69),
1095         CMN_EVENT_CCHA(wdb_occ,                         0x6a),
1096         CMN_EVENT_CCHA(snptrk_occ,                      0x6b),
1097         CMN_EVENT_CCHA(sdb_occ,                         0x6c),
1098         CMN_EVENT_CCHA(snphaz_occ,                      0x6d),
1099         CMN_EVENT_CCHA(reqtrk_alloc,                    0x6e),
1100         CMN_EVENT_CCHA(rdb_alloc,                       0x6f),
1101         CMN_EVENT_CCHA(rdbyp_alloc,                     0x70),
1102         CMN_EVENT_CCHA(wdb_alloc,                       0x71),
1103         CMN_EVENT_CCHA(snptrk_alloc,                    0x72),
1104         CMN_EVENT_CCHA(sdb_alloc,                       0x73),
1105         CMN_EVENT_CCHA(snphaz_alloc,                    0x74),
1106         CMN_EVENT_CCHA(pb_rhu_req_occ,                  0x75),
1107         CMN_EVENT_CCHA(pb_rhu_req_alloc,                0x76),
1108         CMN_EVENT_CCHA(pb_rhu_pcie_req_occ,             0x77),
1109         CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc,           0x78),
1110         CMN_EVENT_CCHA(pb_pcie_wr_req_occ,              0x79),
1111         CMN_EVENT_CCHA(pb_pcie_wr_req_alloc,            0x7a),
1112         CMN_EVENT_CCHA(pb_pcie_reg_req_occ,             0x7b),
1113         CMN_EVENT_CCHA(pb_pcie_reg_req_alloc,           0x7c),
1114         CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ,            0x7d),
1115         CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc,          0x7e),
1116         CMN_EVENT_CCHA(pb_rhu_dat_occ,                  0x7f),
1117         CMN_EVENT_CCHA(pb_rhu_dat_alloc,                0x80),
1118         CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ,             0x81),
1119         CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc,           0x82),
1120         CMN_EVENT_CCHA(pb_pcie_wr_dat_occ,              0x83),
1121         CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc,            0x84),
1122
1123         CMN_EVENT_CCLA(rx_cxs,                          0x21),
1124         CMN_EVENT_CCLA(tx_cxs,                          0x22),
1125         CMN_EVENT_CCLA(rx_cxs_avg_size,                 0x23),
1126         CMN_EVENT_CCLA(tx_cxs_avg_size,                 0x24),
1127         CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure,        0x25),
1128         CMN_EVENT_CCLA(link_crdbuf_occ,                 0x26),
1129         CMN_EVENT_CCLA(link_crdbuf_alloc,               0x27),
1130         CMN_EVENT_CCLA(pfwd_rcvr_cxs,                   0x28),
1131         CMN_EVENT_CCLA(pfwd_sndr_num_flits,             0x29),
1132         CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd,     0x2a),
1133         CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd,    0x2b),
1134
1135         NULL
1136 };
1137
1138 static const struct attribute_group arm_cmn_event_attrs_group = {
1139         .name = "events",
1140         .attrs = arm_cmn_event_attrs,
1141         .is_visible = arm_cmn_event_attr_is_visible,
1142 };
1143
1144 static ssize_t arm_cmn_format_show(struct device *dev,
1145                                    struct device_attribute *attr, char *buf)
1146 {
1147         struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
1148         int lo = __ffs(fmt->field), hi = __fls(fmt->field);
1149
1150         if (lo == hi)
1151                 return sysfs_emit(buf, "config:%d\n", lo);
1152
1153         if (!fmt->config)
1154                 return sysfs_emit(buf, "config:%d-%d\n", lo, hi);
1155
1156         return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi);
1157 }
1158
1159 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld)                             \
1160         (&((struct arm_cmn_format_attr[]) {{                            \
1161                 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
1162                 .config = _cfg,                                         \
1163                 .field = _fld,                                          \
1164         }})[0].attr.attr)
1165 #define CMN_FORMAT_ATTR(_name, _fld)    _CMN_FORMAT_ATTR(_name, 0, _fld)
1166
1167 static struct attribute *arm_cmn_format_attrs[] = {
1168         CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
1169         CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
1170         CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
1171         CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
1172         CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
1173
1174         CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
1175         CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
1176         CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
1177         CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
1178         CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
1179
1180         _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
1181         _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
1182
1183         NULL
1184 };
1185
1186 static const struct attribute_group arm_cmn_format_attrs_group = {
1187         .name = "format",
1188         .attrs = arm_cmn_format_attrs,
1189 };
1190
1191 static ssize_t arm_cmn_cpumask_show(struct device *dev,
1192                                     struct device_attribute *attr, char *buf)
1193 {
1194         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1195
1196         return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
1197 }
1198
1199 static struct device_attribute arm_cmn_cpumask_attr =
1200                 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
1201
1202 static struct attribute *arm_cmn_cpumask_attrs[] = {
1203         &arm_cmn_cpumask_attr.attr,
1204         NULL,
1205 };
1206
1207 static const struct attribute_group arm_cmn_cpumask_attr_group = {
1208         .attrs = arm_cmn_cpumask_attrs,
1209 };
1210
1211 static const struct attribute_group *arm_cmn_attr_groups[] = {
1212         &arm_cmn_event_attrs_group,
1213         &arm_cmn_format_attrs_group,
1214         &arm_cmn_cpumask_attr_group,
1215         NULL
1216 };
1217
1218 static int arm_cmn_wp_idx(struct perf_event *event)
1219 {
1220         return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
1221 }
1222
1223 static u32 arm_cmn_wp_config(struct perf_event *event)
1224 {
1225         u32 config;
1226         u32 dev = CMN_EVENT_WP_DEV_SEL(event);
1227         u32 chn = CMN_EVENT_WP_CHN_SEL(event);
1228         u32 grp = CMN_EVENT_WP_GRP(event);
1229         u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
1230         u32 combine = CMN_EVENT_WP_COMBINE(event);
1231         bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;
1232
1233         config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
1234                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
1235                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
1236                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
1237         if (exc)
1238                 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
1239                                       CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
1240         if (combine && !grp)
1241                 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
1242                                       CMN_DTM_WPn_CONFIG_WP_COMBINE;
1243         return config;
1244 }
1245
1246 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
1247 {
1248         if (!cmn->state)
1249                 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
1250         cmn->state |= state;
1251 }
1252
1253 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
1254 {
1255         cmn->state &= ~state;
1256         if (!cmn->state)
1257                 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
1258                                cmn->dtc[0].base + CMN_DT_PMCR);
1259 }
1260
1261 static void arm_cmn_pmu_enable(struct pmu *pmu)
1262 {
1263         arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
1264 }
1265
1266 static void arm_cmn_pmu_disable(struct pmu *pmu)
1267 {
1268         arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
1269 }
1270
1271 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
1272                             bool snapshot)
1273 {
1274         struct arm_cmn_dtm *dtm = NULL;
1275         struct arm_cmn_node *dn;
1276         unsigned int i, offset, dtm_idx;
1277         u64 reg, count = 0;
1278
1279         offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
1280         for_each_hw_dn(hw, dn, i) {
1281                 if (dtm != &cmn->dtms[dn->dtm]) {
1282                         dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1283                         reg = readq_relaxed(dtm->base + offset);
1284                 }
1285                 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1286                 count += (u16)(reg >> (dtm_idx * 16));
1287         }
1288         return count;
1289 }
1290
1291 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
1292 {
1293         u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
1294
1295         writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1296         return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
1297 }
1298
1299 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
1300 {
1301         u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
1302
1303         val = readl_relaxed(dtc->base + pmevcnt);
1304         writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
1305         return val - CMN_COUNTER_INIT;
1306 }
1307
1308 static void arm_cmn_init_counter(struct perf_event *event)
1309 {
1310         struct arm_cmn *cmn = to_cmn(event->pmu);
1311         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1312         unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx);
1313         u64 count;
1314
1315         for (i = 0; hw->dtcs_used & (1U << i); i++) {
1316                 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt);
1317                 cmn->dtc[i].counters[hw->dtc_idx] = event;
1318         }
1319
1320         count = arm_cmn_read_dtm(cmn, hw, false);
1321         local64_set(&event->hw.prev_count, count);
1322 }
1323
1324 static void arm_cmn_event_read(struct perf_event *event)
1325 {
1326         struct arm_cmn *cmn = to_cmn(event->pmu);
1327         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1328         u64 delta, new, prev;
1329         unsigned long flags;
1330         unsigned int i;
1331
1332         if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) {
1333                 i = __ffs(hw->dtcs_used);
1334                 delta = arm_cmn_read_cc(cmn->dtc + i);
1335                 local64_add(delta, &event->count);
1336                 return;
1337         }
1338         new = arm_cmn_read_dtm(cmn, hw, false);
1339         prev = local64_xchg(&event->hw.prev_count, new);
1340
1341         delta = new - prev;
1342
1343         local_irq_save(flags);
1344         for (i = 0; hw->dtcs_used & (1U << i); i++) {
1345                 new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx);
1346                 delta += new << 16;
1347         }
1348         local_irq_restore(flags);
1349         local64_add(delta, &event->count);
1350 }
1351
1352 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,
1353                                     enum cmn_filter_select fsel, u8 occupid)
1354 {
1355         u64 reg;
1356
1357         if (fsel == SEL_NONE)
1358                 return 0;
1359
1360         if (!dn->occupid[fsel].count) {
1361                 dn->occupid[fsel].val = occupid;
1362                 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL,
1363                                  dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) |
1364                       FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID,
1365                                  dn->occupid[SEL_CLASS_OCCUP_ID].val) |
1366                       FIELD_PREP(CMN__PMU_OCCUP1_ID,
1367                                  dn->occupid[SEL_OCCUP1ID].val);
1368                 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
1369         } else if (dn->occupid[fsel].val != occupid) {
1370                 return -EBUSY;
1371         }
1372         dn->occupid[fsel].count++;
1373         return 0;
1374 }
1375
1376 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,
1377                                      int eventid, bool wide_sel)
1378 {
1379         if (wide_sel) {
1380                 dn->event_w[dtm_idx] = eventid;
1381                 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
1382         } else {
1383                 dn->event[dtm_idx] = eventid;
1384                 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
1385         }
1386 }
1387
1388 static void arm_cmn_event_start(struct perf_event *event, int flags)
1389 {
1390         struct arm_cmn *cmn = to_cmn(event->pmu);
1391         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1392         struct arm_cmn_node *dn;
1393         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1394         int i;
1395
1396         if (type == CMN_TYPE_DTC) {
1397                 i = __ffs(hw->dtcs_used);
1398                 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1399                 cmn->dtc[i].cc_active = true;
1400         } else if (type == CMN_TYPE_WP) {
1401                 int wp_idx = arm_cmn_wp_idx(event);
1402                 u64 val = CMN_EVENT_WP_VAL(event);
1403                 u64 mask = CMN_EVENT_WP_MASK(event);
1404
1405                 for_each_hw_dn(hw, dn, i) {
1406                         void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1407
1408                         writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1409                         writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1410                 }
1411         } else for_each_hw_dn(hw, dn, i) {
1412                 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1413
1414                 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event),
1415                                          hw->wide_sel);
1416         }
1417 }
1418
1419 static void arm_cmn_event_stop(struct perf_event *event, int flags)
1420 {
1421         struct arm_cmn *cmn = to_cmn(event->pmu);
1422         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1423         struct arm_cmn_node *dn;
1424         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1425         int i;
1426
1427         if (type == CMN_TYPE_DTC) {
1428                 i = __ffs(hw->dtcs_used);
1429                 cmn->dtc[i].cc_active = false;
1430         } else if (type == CMN_TYPE_WP) {
1431                 int wp_idx = arm_cmn_wp_idx(event);
1432
1433                 for_each_hw_dn(hw, dn, i) {
1434                         void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1435
1436                         writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1437                         writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1438                 }
1439         } else for_each_hw_dn(hw, dn, i) {
1440                 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1441
1442                 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel);
1443         }
1444
1445         arm_cmn_event_read(event);
1446 }
1447
1448 struct arm_cmn_val {
1449         u8 dtm_count[CMN_MAX_DTMS];
1450         u8 occupid[CMN_MAX_DTMS][SEL_MAX];
1451         u8 wp[CMN_MAX_DTMS][4];
1452         int dtc_count;
1453         bool cycles;
1454 };
1455
1456 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,
1457                                   struct perf_event *event)
1458 {
1459         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1460         struct arm_cmn_node *dn;
1461         enum cmn_node_type type;
1462         int i;
1463
1464         if (is_software_event(event))
1465                 return;
1466
1467         type = CMN_EVENT_TYPE(event);
1468         if (type == CMN_TYPE_DTC) {
1469                 val->cycles = true;
1470                 return;
1471         }
1472
1473         val->dtc_count++;
1474
1475         for_each_hw_dn(hw, dn, i) {
1476                 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1477
1478                 val->dtm_count[dtm]++;
1479
1480                 if (sel > SEL_NONE)
1481                         val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;
1482
1483                 if (type != CMN_TYPE_WP)
1484                         continue;
1485
1486                 wp_idx = arm_cmn_wp_idx(event);
1487                 val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
1488         }
1489 }
1490
1491 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)
1492 {
1493         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1494         struct arm_cmn_node *dn;
1495         struct perf_event *sibling, *leader = event->group_leader;
1496         enum cmn_node_type type;
1497         struct arm_cmn_val *val;
1498         int i, ret = -EINVAL;
1499
1500         if (leader == event)
1501                 return 0;
1502
1503         if (event->pmu != leader->pmu && !is_software_event(leader))
1504                 return -EINVAL;
1505
1506         val = kzalloc(sizeof(*val), GFP_KERNEL);
1507         if (!val)
1508                 return -ENOMEM;
1509
1510         arm_cmn_val_add_event(cmn, val, leader);
1511         for_each_sibling_event(sibling, leader)
1512                 arm_cmn_val_add_event(cmn, val, sibling);
1513
1514         type = CMN_EVENT_TYPE(event);
1515         if (type == CMN_TYPE_DTC) {
1516                 ret = val->cycles ? -EINVAL : 0;
1517                 goto done;
1518         }
1519
1520         if (val->dtc_count == CMN_DT_NUM_COUNTERS)
1521                 goto done;
1522
1523         for_each_hw_dn(hw, dn, i) {
1524                 int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel;
1525
1526                 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)
1527                         goto done;
1528
1529                 if (sel > SEL_NONE && val->occupid[dtm][sel] &&
1530                     val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)
1531                         goto done;
1532
1533                 if (type != CMN_TYPE_WP)
1534                         continue;
1535
1536                 wp_idx = arm_cmn_wp_idx(event);
1537                 if (val->wp[dtm][wp_idx])
1538                         goto done;
1539
1540                 wp_cmb = val->wp[dtm][wp_idx ^ 1];
1541                 if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1)
1542                         goto done;
1543         }
1544
1545         ret = 0;
1546 done:
1547         kfree(val);
1548         return ret;
1549 }
1550
1551 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,
1552                                                  enum cmn_node_type type,
1553                                                  unsigned int eventid)
1554 {
1555         struct arm_cmn_event_attr *e;
1556         enum cmn_model model = arm_cmn_model(cmn);
1557
1558         for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) {
1559                 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr);
1560                 if (e->model & model && e->type == type && e->eventid == eventid)
1561                         return e->fsel;
1562         }
1563         return SEL_NONE;
1564 }
1565
1566
1567 static int arm_cmn_event_init(struct perf_event *event)
1568 {
1569         struct arm_cmn *cmn = to_cmn(event->pmu);
1570         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1571         struct arm_cmn_node *dn;
1572         enum cmn_node_type type;
1573         bool bynodeid;
1574         u16 nodeid, eventid;
1575
1576         if (event->attr.type != event->pmu->type)
1577                 return -ENOENT;
1578
1579         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
1580                 return -EINVAL;
1581
1582         event->cpu = cmn->cpu;
1583         if (event->cpu < 0)
1584                 return -EINVAL;
1585
1586         type = CMN_EVENT_TYPE(event);
1587         /* DTC events (i.e. cycles) already have everything they need */
1588         if (type == CMN_TYPE_DTC)
1589                 return 0;
1590
1591         eventid = CMN_EVENT_EVENTID(event);
1592         /* For watchpoints we need the actual XP node here */
1593         if (type == CMN_TYPE_WP) {
1594                 type = CMN_TYPE_XP;
1595                 /* ...and we need a "real" direction */
1596                 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
1597                         return -EINVAL;
1598                 /* ...but the DTM may depend on which port we're watching */
1599                 if (cmn->multi_dtm)
1600                         hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2;
1601         } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) {
1602                 hw->wide_sel = true;
1603         }
1604
1605         /* This is sufficiently annoying to recalculate, so cache it */
1606         hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid);
1607
1608         bynodeid = CMN_EVENT_BYNODEID(event);
1609         nodeid = CMN_EVENT_NODEID(event);
1610
1611         hw->dn = arm_cmn_node(cmn, type);
1612         if (!hw->dn)
1613                 return -EINVAL;
1614         for (dn = hw->dn; dn->type == type; dn++) {
1615                 if (bynodeid && dn->id != nodeid) {
1616                         hw->dn++;
1617                         continue;
1618                 }
1619                 hw->num_dns++;
1620                 if (bynodeid)
1621                         break;
1622         }
1623
1624         if (!hw->num_dns) {
1625                 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid);
1626
1627                 dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
1628                         nodeid, nid.x, nid.y, nid.port, nid.dev, type);
1629                 return -EINVAL;
1630         }
1631         /*
1632          * Keep assuming non-cycles events count in all DTC domains; turns out
1633          * it's hard to make a worthwhile optimisation around this, short of
1634          * going all-in with domain-local counter allocation as well.
1635          */
1636         hw->dtcs_used = (1U << cmn->num_dtcs) - 1;
1637
1638         return arm_cmn_validate_group(cmn, event);
1639 }
1640
1641 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
1642                                 int i)
1643 {
1644         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1645         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1646
1647         while (i--) {
1648                 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;
1649                 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1650
1651                 if (type == CMN_TYPE_WP)
1652                         dtm->wp_event[arm_cmn_wp_idx(event)] = -1;
1653
1654                 if (hw->filter_sel > SEL_NONE)
1655                         hw->dn[i].occupid[hw->filter_sel].count--;
1656
1657                 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
1658                 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
1659         }
1660         memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
1661
1662         for (i = 0; hw->dtcs_used & (1U << i); i++)
1663                 cmn->dtc[i].counters[hw->dtc_idx] = NULL;
1664 }
1665
1666 static int arm_cmn_event_add(struct perf_event *event, int flags)
1667 {
1668         struct arm_cmn *cmn = to_cmn(event->pmu);
1669         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1670         struct arm_cmn_dtc *dtc = &cmn->dtc[0];
1671         struct arm_cmn_node *dn;
1672         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1673         unsigned int i, dtc_idx, input_sel;
1674
1675         if (type == CMN_TYPE_DTC) {
1676                 i = 0;
1677                 while (cmn->dtc[i].cycles)
1678                         if (++i == cmn->num_dtcs)
1679                                 return -ENOSPC;
1680
1681                 cmn->dtc[i].cycles = event;
1682                 hw->dtc_idx = CMN_DT_NUM_COUNTERS;
1683                 hw->dtcs_used = 1U << i;
1684
1685                 if (flags & PERF_EF_START)
1686                         arm_cmn_event_start(event, 0);
1687                 return 0;
1688         }
1689
1690         /* Grab a free global counter first... */
1691         dtc_idx = 0;
1692         while (dtc->counters[dtc_idx])
1693                 if (++dtc_idx == CMN_DT_NUM_COUNTERS)
1694                         return -ENOSPC;
1695
1696         hw->dtc_idx = dtc_idx;
1697
1698         /* ...then the local counters to feed it. */
1699         for_each_hw_dn(hw, dn, i) {
1700                 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1701                 unsigned int dtm_idx, shift;
1702                 u64 reg;
1703
1704                 dtm_idx = 0;
1705                 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
1706                         if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
1707                                 goto free_dtms;
1708
1709                 if (type == CMN_TYPE_XP) {
1710                         input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
1711                 } else if (type == CMN_TYPE_WP) {
1712                         int tmp, wp_idx = arm_cmn_wp_idx(event);
1713                         u32 cfg = arm_cmn_wp_config(event);
1714
1715                         if (dtm->wp_event[wp_idx] >= 0)
1716                                 goto free_dtms;
1717
1718                         tmp = dtm->wp_event[wp_idx ^ 1];
1719                         if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
1720                                         CMN_EVENT_WP_COMBINE(dtc->counters[tmp]))
1721                                 goto free_dtms;
1722
1723                         input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
1724                         dtm->wp_event[wp_idx] = dtc_idx;
1725                         writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
1726                 } else {
1727                         struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
1728
1729                         if (cmn->multi_dtm)
1730                                 nid.port %= 2;
1731
1732                         input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
1733                                     (nid.port << 4) + (nid.dev << 2);
1734
1735                         if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))
1736                                 goto free_dtms;
1737                 }
1738
1739                 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
1740
1741                 dtm->input_sel[dtm_idx] = input_sel;
1742                 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
1743                 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
1744                 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;
1745                 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
1746                 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;
1747                 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
1748         }
1749
1750         /* Go go go! */
1751         arm_cmn_init_counter(event);
1752
1753         if (flags & PERF_EF_START)
1754                 arm_cmn_event_start(event, 0);
1755
1756         return 0;
1757
1758 free_dtms:
1759         arm_cmn_event_clear(cmn, event, i);
1760         return -ENOSPC;
1761 }
1762
1763 static void arm_cmn_event_del(struct perf_event *event, int flags)
1764 {
1765         struct arm_cmn *cmn = to_cmn(event->pmu);
1766         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1767         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1768
1769         arm_cmn_event_stop(event, PERF_EF_UPDATE);
1770
1771         if (type == CMN_TYPE_DTC)
1772                 cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL;
1773         else
1774                 arm_cmn_event_clear(cmn, event, hw->num_dns);
1775 }
1776
1777 /*
1778  * We stop the PMU for both add and read, to avoid skew across DTM counters.
1779  * In theory we could use snapshots to read without stopping, but then it
1780  * becomes a lot trickier to deal with overlow and racing against interrupts,
1781  * plus it seems they don't work properly on some hardware anyway :(
1782  */
1783 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
1784 {
1785         arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
1786 }
1787
1788 static void arm_cmn_end_txn(struct pmu *pmu)
1789 {
1790         arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
1791 }
1792
1793 static int arm_cmn_commit_txn(struct pmu *pmu)
1794 {
1795         arm_cmn_end_txn(pmu);
1796         return 0;
1797 }
1798
1799 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)
1800 {
1801         unsigned int i;
1802
1803         perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu);
1804         for (i = 0; i < cmn->num_dtcs; i++)
1805                 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
1806         cmn->cpu = cpu;
1807 }
1808
1809 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
1810 {
1811         struct arm_cmn *cmn;
1812         int node;
1813
1814         cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
1815         node = dev_to_node(cmn->dev);
1816         if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)
1817                 arm_cmn_migrate(cmn, cpu);
1818         return 0;
1819 }
1820
1821 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
1822 {
1823         struct arm_cmn *cmn;
1824         unsigned int target;
1825         int node;
1826         cpumask_t mask;
1827
1828         cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
1829         if (cpu != cmn->cpu)
1830                 return 0;
1831
1832         node = dev_to_node(cmn->dev);
1833         if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) &&
1834             cpumask_andnot(&mask, &mask, cpumask_of(cpu)))
1835                 target = cpumask_any(&mask);
1836         else
1837                 target = cpumask_any_but(cpu_online_mask, cpu);
1838         if (target < nr_cpu_ids)
1839                 arm_cmn_migrate(cmn, target);
1840         return 0;
1841 }
1842
1843 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
1844 {
1845         struct arm_cmn_dtc *dtc = dev_id;
1846         irqreturn_t ret = IRQ_NONE;
1847
1848         for (;;) {
1849                 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
1850                 u64 delta;
1851                 int i;
1852
1853                 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
1854                         if (status & (1U << i)) {
1855                                 ret = IRQ_HANDLED;
1856                                 if (WARN_ON(!dtc->counters[i]))
1857                                         continue;
1858                                 delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
1859                                 local64_add(delta, &dtc->counters[i]->count);
1860                         }
1861                 }
1862
1863                 if (status & (1U << CMN_DT_NUM_COUNTERS)) {
1864                         ret = IRQ_HANDLED;
1865                         if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
1866                                 delta = arm_cmn_read_cc(dtc);
1867                                 local64_add(delta, &dtc->cycles->count);
1868                         }
1869                 }
1870
1871                 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
1872
1873                 if (!dtc->irq_friend)
1874                         return ret;
1875                 dtc += dtc->irq_friend;
1876         }
1877 }
1878
1879 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
1880 static int arm_cmn_init_irqs(struct arm_cmn *cmn)
1881 {
1882         int i, j, irq, err;
1883
1884         for (i = 0; i < cmn->num_dtcs; i++) {
1885                 irq = cmn->dtc[i].irq;
1886                 for (j = i; j--; ) {
1887                         if (cmn->dtc[j].irq == irq) {
1888                                 cmn->dtc[j].irq_friend = i - j;
1889                                 goto next;
1890                         }
1891                 }
1892                 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
1893                                        IRQF_NOBALANCING | IRQF_NO_THREAD,
1894                                        dev_name(cmn->dev), &cmn->dtc[i]);
1895                 if (err)
1896                         return err;
1897
1898                 err = irq_set_affinity(irq, cpumask_of(cmn->cpu));
1899                 if (err)
1900                         return err;
1901         next:
1902                 ; /* isn't C great? */
1903         }
1904         return 0;
1905 }
1906
1907 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)
1908 {
1909         int i;
1910
1911         dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
1912         dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
1913         for (i = 0; i < 4; i++) {
1914                 dtm->wp_event[i] = -1;
1915                 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
1916                 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
1917         }
1918 }
1919
1920 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
1921 {
1922         struct arm_cmn_dtc *dtc = cmn->dtc + idx;
1923
1924         dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
1925         dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
1926         if (dtc->irq < 0)
1927                 return dtc->irq;
1928
1929         writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
1930         writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
1931         writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
1932         writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
1933
1934         return 0;
1935 }
1936
1937 static int arm_cmn_node_cmp(const void *a, const void *b)
1938 {
1939         const struct arm_cmn_node *dna = a, *dnb = b;
1940         int cmp;
1941
1942         cmp = dna->type - dnb->type;
1943         if (!cmp)
1944                 cmp = dna->logid - dnb->logid;
1945         return cmp;
1946 }
1947
1948 static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
1949 {
1950         struct arm_cmn_node *dn, *xp;
1951         int dtc_idx = 0;
1952         u8 dtcs_present = (1 << cmn->num_dtcs) - 1;
1953
1954         cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
1955         if (!cmn->dtc)
1956                 return -ENOMEM;
1957
1958         sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
1959
1960         cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
1961
1962         for (dn = cmn->dns; dn->type; dn++) {
1963                 if (dn->type == CMN_TYPE_XP) {
1964                         dn->dtc &= dtcs_present;
1965                         continue;
1966                 }
1967
1968                 xp = arm_cmn_node_to_xp(cmn, dn);
1969                 dn->dtm = xp->dtm;
1970                 if (cmn->multi_dtm)
1971                         dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2;
1972
1973                 if (dn->type == CMN_TYPE_DTC) {
1974                         int err;
1975                         /* We do at least know that a DTC's XP must be in that DTC's domain */
1976                         if (xp->dtc == 0xf)
1977                                 xp->dtc = 1 << dtc_idx;
1978                         err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);
1979                         if (err)
1980                                 return err;
1981                 }
1982
1983                 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
1984                 if (dn->type == CMN_TYPE_RND)
1985                         dn->type = CMN_TYPE_RNI;
1986
1987                 /* We split the RN-I off already, so let the CCLA part match CCLA events */
1988                 if (dn->type == CMN_TYPE_CCLA_RNI)
1989                         dn->type = CMN_TYPE_CCLA;
1990         }
1991
1992         arm_cmn_set_state(cmn, CMN_STATE_DISABLED);
1993
1994         return 0;
1995 }
1996
1997 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
1998 {
1999         int level;
2000         u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
2001
2002         node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
2003         node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
2004         node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
2005
2006         node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
2007
2008         if (node->type == CMN_TYPE_CFG)
2009                 level = 0;
2010         else if (node->type == CMN_TYPE_XP)
2011                 level = 1;
2012         else
2013                 level = 2;
2014
2015         dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
2016                         (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
2017                         node->type, node->logid, offset);
2018 }
2019
2020 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)
2021 {
2022         switch (type) {
2023         case CMN_TYPE_HNP:
2024                 return CMN_TYPE_HNI;
2025         case CMN_TYPE_CCLA_RNI:
2026                 return CMN_TYPE_RNI;
2027         default:
2028                 return CMN_TYPE_INVALID;
2029         }
2030 }
2031
2032 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
2033 {
2034         void __iomem *cfg_region;
2035         struct arm_cmn_node cfg, *dn;
2036         struct arm_cmn_dtm *dtm;
2037         enum cmn_part part;
2038         u16 child_count, child_poff;
2039         u32 xp_offset[CMN_MAX_XPS];
2040         u64 reg;
2041         int i, j;
2042         size_t sz;
2043
2044         arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
2045         if (cfg.type != CMN_TYPE_CFG)
2046                 return -ENODEV;
2047
2048         cfg_region = cmn->base + rgn_offset;
2049
2050         reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
2051         part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
2052         part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
2053         if (cmn->part && cmn->part != part)
2054                 dev_warn(cmn->dev,
2055                          "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n",
2056                          cmn->part, part);
2057         cmn->part = part;
2058         if (!arm_cmn_model(cmn))
2059                 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part);
2060
2061         reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23);
2062         cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
2063
2064         reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
2065         cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;
2066         cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);
2067         cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);
2068
2069         reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
2070         cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);
2071         cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);
2072
2073         reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
2074         child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2075         child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2076
2077         cmn->num_xps = child_count;
2078         cmn->num_dns = cmn->num_xps;
2079
2080         /* Pass 1: visit the XPs, enumerate their children */
2081         for (i = 0; i < cmn->num_xps; i++) {
2082                 reg = readq_relaxed(cfg_region + child_poff + i * 8);
2083                 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
2084
2085                 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
2086                 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2087         }
2088
2089         /*
2090          * Some nodes effectively have two separate types, which we'll handle
2091          * by creating one of each internally. For a (very) safe initial upper
2092          * bound, account for double the number of non-XP nodes.
2093          */
2094         dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,
2095                           sizeof(*dn), GFP_KERNEL);
2096         if (!dn)
2097                 return -ENOMEM;
2098
2099         /* Initial safe upper bound on DTMs for any possible mesh layout */
2100         i = cmn->num_xps;
2101         if (cmn->multi_dtm)
2102                 i += cmn->num_xps + 1;
2103         dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);
2104         if (!dtm)
2105                 return -ENOMEM;
2106
2107         /* Pass 2: now we can actually populate the nodes */
2108         cmn->dns = dn;
2109         cmn->dtms = dtm;
2110         for (i = 0; i < cmn->num_xps; i++) {
2111                 void __iomem *xp_region = cmn->base + xp_offset[i];
2112                 struct arm_cmn_node *xp = dn++;
2113                 unsigned int xp_ports = 0;
2114
2115                 arm_cmn_init_node_info(cmn, xp_offset[i], xp);
2116                 /*
2117                  * Thanks to the order in which XP logical IDs seem to be
2118                  * assigned, we can handily infer the mesh X dimension by
2119                  * looking out for the XP at (0,1) without needing to know
2120                  * the exact node ID format, which we can later derive.
2121                  */
2122                 if (xp->id == (1 << 3))
2123                         cmn->mesh_x = xp->logid;
2124
2125                 if (cmn->part == PART_CMN600)
2126                         xp->dtc = 0xf;
2127                 else
2128                         xp->dtc = 1 << readl_relaxed(xp_region + CMN_DTM_UNIT_INFO);
2129
2130                 xp->dtm = dtm - cmn->dtms;
2131                 arm_cmn_init_dtm(dtm++, xp, 0);
2132                 /*
2133                  * Keeping track of connected ports will let us filter out
2134                  * unnecessary XP events easily. We can also reliably infer the
2135                  * "extra device ports" configuration for the node ID format
2136                  * from this, since in that case we will see at least one XP
2137                  * with port 2 connected, for the HN-D.
2138                  */
2139                 for (int p = 0; p < CMN_MAX_PORTS; p++)
2140                         if (arm_cmn_device_connect_info(cmn, xp, p))
2141                                 xp_ports |= BIT(p);
2142
2143                 if (cmn->multi_dtm && (xp_ports & 0xc))
2144                         arm_cmn_init_dtm(dtm++, xp, 1);
2145                 if (cmn->multi_dtm && (xp_ports & 0x30))
2146                         arm_cmn_init_dtm(dtm++, xp, 2);
2147
2148                 cmn->ports_used |= xp_ports;
2149
2150                 reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
2151                 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2152                 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2153
2154                 for (j = 0; j < child_count; j++) {
2155                         reg = readq_relaxed(xp_region + child_poff + j * 8);
2156                         /*
2157                          * Don't even try to touch anything external, since in general
2158                          * we haven't a clue how to power up arbitrary CHI requesters.
2159                          * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
2160                          * neither of which have any PMU events anyway.
2161                          * (Actually, CXLAs do seem to have grown some events in r1p2,
2162                          * but they don't go to regular XP DTMs, and they depend on
2163                          * secure configuration which we can't easily deal with)
2164                          */
2165                         if (reg & CMN_CHILD_NODE_EXTERNAL) {
2166                                 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
2167                                 continue;
2168                         }
2169
2170                         arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
2171
2172                         switch (dn->type) {
2173                         case CMN_TYPE_DTC:
2174                                 cmn->num_dtcs++;
2175                                 dn++;
2176                                 break;
2177                         /* These guys have PMU events */
2178                         case CMN_TYPE_DVM:
2179                         case CMN_TYPE_HNI:
2180                         case CMN_TYPE_HNF:
2181                         case CMN_TYPE_SBSX:
2182                         case CMN_TYPE_RNI:
2183                         case CMN_TYPE_RND:
2184                         case CMN_TYPE_MTSX:
2185                         case CMN_TYPE_CXRA:
2186                         case CMN_TYPE_CXHA:
2187                         case CMN_TYPE_CCRA:
2188                         case CMN_TYPE_CCHA:
2189                         case CMN_TYPE_CCLA:
2190                                 dn++;
2191                                 break;
2192                         /* Nothing to see here */
2193                         case CMN_TYPE_MPAM_S:
2194                         case CMN_TYPE_MPAM_NS:
2195                         case CMN_TYPE_RNSAM:
2196                         case CMN_TYPE_CXLA:
2197                                 break;
2198                         /*
2199                          * Split "optimised" combination nodes into separate
2200                          * types for the different event sets. Offsetting the
2201                          * base address lets us handle the second pmu_event_sel
2202                          * register via the normal mechanism later.
2203                          */
2204                         case CMN_TYPE_HNP:
2205                         case CMN_TYPE_CCLA_RNI:
2206                                 dn[1] = dn[0];
2207                                 dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL;
2208                                 dn[1].type = arm_cmn_subtype(dn->type);
2209                                 dn += 2;
2210                                 break;
2211                         /* Something has gone horribly wrong */
2212                         default:
2213                                 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
2214                                 return -ENODEV;
2215                         }
2216                 }
2217         }
2218
2219         /* Correct for any nodes we added or skipped */
2220         cmn->num_dns = dn - cmn->dns;
2221
2222         /* Cheeky +1 to help terminate pointer-based iteration later */
2223         sz = (void *)(dn + 1) - (void *)cmn->dns;
2224         dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);
2225         if (dn)
2226                 cmn->dns = dn;
2227
2228         sz = (void *)dtm - (void *)cmn->dtms;
2229         dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);
2230         if (dtm)
2231                 cmn->dtms = dtm;
2232
2233         /*
2234          * If mesh_x wasn't set during discovery then we never saw
2235          * an XP at (0,1), thus we must have an Nx1 configuration.
2236          */
2237         if (!cmn->mesh_x)
2238                 cmn->mesh_x = cmn->num_xps;
2239         cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
2240
2241         /* 1x1 config plays havoc with XP event encodings */
2242         if (cmn->num_xps == 1)
2243                 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
2244
2245         dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev);
2246         reg = cmn->ports_used;
2247         dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n",
2248                 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), &reg,
2249                 cmn->multi_dtm ? ", multi-DTM" : "");
2250
2251         return 0;
2252 }
2253
2254 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
2255 {
2256         struct resource *cfg, *root;
2257
2258         cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2259         if (!cfg)
2260                 return -EINVAL;
2261
2262         root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2263         if (!root)
2264                 return -EINVAL;
2265
2266         if (!resource_contains(cfg, root))
2267                 swap(cfg, root);
2268         /*
2269          * Note that devm_ioremap_resource() is dumb and won't let the platform
2270          * device claim cfg when the ACPI companion device has already claimed
2271          * root within it. But since they *are* already both claimed in the
2272          * appropriate name, we don't really need to do it again here anyway.
2273          */
2274         cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
2275         if (!cmn->base)
2276                 return -ENOMEM;
2277
2278         return root->start - cfg->start;
2279 }
2280
2281 static int arm_cmn600_of_probe(struct device_node *np)
2282 {
2283         u32 rootnode;
2284
2285         return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode;
2286 }
2287
2288 static int arm_cmn_probe(struct platform_device *pdev)
2289 {
2290         struct arm_cmn *cmn;
2291         const char *name;
2292         static atomic_t id;
2293         int err, rootnode, this_id;
2294
2295         cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
2296         if (!cmn)
2297                 return -ENOMEM;
2298
2299         cmn->dev = &pdev->dev;
2300         cmn->part = (unsigned long)device_get_match_data(cmn->dev);
2301         platform_set_drvdata(pdev, cmn);
2302
2303         if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {
2304                 rootnode = arm_cmn600_acpi_probe(pdev, cmn);
2305         } else {
2306                 rootnode = 0;
2307                 cmn->base = devm_platform_ioremap_resource(pdev, 0);
2308                 if (IS_ERR(cmn->base))
2309                         return PTR_ERR(cmn->base);
2310                 if (cmn->part == PART_CMN600)
2311                         rootnode = arm_cmn600_of_probe(pdev->dev.of_node);
2312         }
2313         if (rootnode < 0)
2314                 return rootnode;
2315
2316         err = arm_cmn_discover(cmn, rootnode);
2317         if (err)
2318                 return err;
2319
2320         err = arm_cmn_init_dtcs(cmn);
2321         if (err)
2322                 return err;
2323
2324         err = arm_cmn_init_irqs(cmn);
2325         if (err)
2326                 return err;
2327
2328         cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev));
2329         cmn->pmu = (struct pmu) {
2330                 .module = THIS_MODULE,
2331                 .attr_groups = arm_cmn_attr_groups,
2332                 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
2333                 .task_ctx_nr = perf_invalid_context,
2334                 .pmu_enable = arm_cmn_pmu_enable,
2335                 .pmu_disable = arm_cmn_pmu_disable,
2336                 .event_init = arm_cmn_event_init,
2337                 .add = arm_cmn_event_add,
2338                 .del = arm_cmn_event_del,
2339                 .start = arm_cmn_event_start,
2340                 .stop = arm_cmn_event_stop,
2341                 .read = arm_cmn_event_read,
2342                 .start_txn = arm_cmn_start_txn,
2343                 .commit_txn = arm_cmn_commit_txn,
2344                 .cancel_txn = arm_cmn_end_txn,
2345         };
2346
2347         this_id = atomic_fetch_inc(&id);
2348         name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id);
2349         if (!name)
2350                 return -ENOMEM;
2351
2352         err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
2353         if (err)
2354                 return err;
2355
2356         err = perf_pmu_register(&cmn->pmu, name, -1);
2357         if (err)
2358                 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2359         else
2360                 arm_cmn_debugfs_init(cmn, this_id);
2361
2362         return err;
2363 }
2364
2365 static int arm_cmn_remove(struct platform_device *pdev)
2366 {
2367         struct arm_cmn *cmn = platform_get_drvdata(pdev);
2368
2369         writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
2370
2371         perf_pmu_unregister(&cmn->pmu);
2372         cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2373         debugfs_remove(cmn->debug);
2374         return 0;
2375 }
2376
2377 #ifdef CONFIG_OF
2378 static const struct of_device_id arm_cmn_of_match[] = {
2379         { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 },
2380         { .compatible = "arm,cmn-650" },
2381         { .compatible = "arm,cmn-700" },
2382         { .compatible = "arm,ci-700" },
2383         {}
2384 };
2385 MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
2386 #endif
2387
2388 #ifdef CONFIG_ACPI
2389 static const struct acpi_device_id arm_cmn_acpi_match[] = {
2390         { "ARMHC600", PART_CMN600 },
2391         { "ARMHC650" },
2392         { "ARMHC700" },
2393         {}
2394 };
2395 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
2396 #endif
2397
2398 static struct platform_driver arm_cmn_driver = {
2399         .driver = {
2400                 .name = "arm-cmn",
2401                 .of_match_table = of_match_ptr(arm_cmn_of_match),
2402                 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
2403         },
2404         .probe = arm_cmn_probe,
2405         .remove = arm_cmn_remove,
2406 };
2407
2408 static int __init arm_cmn_init(void)
2409 {
2410         int ret;
2411
2412         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
2413                                       "perf/arm/cmn:online",
2414                                       arm_cmn_pmu_online_cpu,
2415                                       arm_cmn_pmu_offline_cpu);
2416         if (ret < 0)
2417                 return ret;
2418
2419         arm_cmn_hp_state = ret;
2420         arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL);
2421
2422         ret = platform_driver_register(&arm_cmn_driver);
2423         if (ret) {
2424                 cpuhp_remove_multi_state(arm_cmn_hp_state);
2425                 debugfs_remove(arm_cmn_debugfs);
2426         }
2427         return ret;
2428 }
2429
2430 static void __exit arm_cmn_exit(void)
2431 {
2432         platform_driver_unregister(&arm_cmn_driver);
2433         cpuhp_remove_multi_state(arm_cmn_hp_state);
2434         debugfs_remove(arm_cmn_debugfs);
2435 }
2436
2437 module_init(arm_cmn_init);
2438 module_exit(arm_cmn_exit);
2439
2440 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>");
2441 MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
2442 MODULE_LICENSE("GPL v2");