1 # SPDX-License-Identifier: GPL-2.0-only
3 # Performance Monitor Drivers
6 menu "Performance monitor support"
10 tristate "ARM CCI PMU driver"
11 depends on (ARM && CPU_V7) || ARM64
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
15 Interconnect) family of products.
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
22 depends on ARM_CCI_PMU
23 select ARM_CCI400_COMMON
25 CCI-400 provides 4 independent event counters counting events related
26 to the connected slave/master interfaces, plus a cycle counter.
29 bool "support CCI-500/CCI-550"
31 depends on ARM_CCI_PMU
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
34 count events pertaining to the slave/master interfaces as well as the
35 internal events to the CCI.
38 tristate "ARM CCN driver support"
39 depends on ARM || ARM64
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
46 depends on ARM64 || (COMPILE_TEST && 64BIT)
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 depends on ARM || ARM64
53 bool "ARM PMU framework"
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
64 Say y if you want to use CPU performance monitors on RISCV-based
65 systems. This provides the core PMU framework that abstracts common
66 PMU functionalities in a core library so that different PMU drivers
69 config RISCV_PMU_LEGACY
71 bool "RISC-V legacy PMU implementation"
74 Say y if you want to use the legacy CPU performance monitor
75 implementation on RISC-V based systems. This only allows counting
76 of cycle/instruction counter and doesn't support counter overflow,
77 or programmable counters. It will be removed in future.
80 depends on RISCV_PMU && RISCV_SBI
81 bool "RISC-V PMU based on SBI PMU extension"
84 Say y if you want to use the CPU performance monitor
85 using SBI PMU extension on RISC-V based systems. This option provides
86 full perf feature support i.e. counter overflow, privilege mode
87 filtering, counter configuration.
90 depends on ARM_PMU && ACPI
93 config ARM_SMMU_V3_PMU
94 tristate "ARM SMMUv3 Performance Monitors Extension"
95 depends on ARM64 && ACPI
97 Provides support for the ARM SMMUv3 Performance Monitor Counter
98 Groups (PMCG), which provide monitoring of transactions passing
99 through the SMMU and allow the resulting information to be filtered
100 based on the Stream ID of the corresponding master.
103 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
106 Provides support for performance monitor unit in ARM DynamIQ Shared
107 Unit (DSU). The DSU integrates one or more cores with an L3 memory
108 system, control logic. The PMU allows counting various events related
111 config FSL_IMX8_DDR_PMU
112 tristate "Freescale i.MX8 DDR perf monitor"
115 Provides support for the DDR performance monitor in i.MX8, which
116 can give information about memory throughput and other related
120 bool "Qualcomm Technologies L2-cache PMU"
121 depends on ARCH_QCOM && ARM64 && ACPI
122 select QCOM_KRYO_L2_ACCESSORS
124 Provides support for the L2 cache performance monitor unit (PMU)
125 in Qualcomm Technologies processors.
126 Adds the L2 cache PMU into the perf events subsystem for
127 monitoring L2 cache events.
130 bool "Qualcomm Technologies L3-cache PMU"
131 depends on ARCH_QCOM && ARM64 && ACPI
132 select QCOM_IRQ_COMBINER
134 Provides support for the L3 cache performance monitor unit (PMU)
135 in Qualcomm Technologies processors.
136 Adds the L3 cache PMU into the perf events subsystem for
137 monitoring L3 cache events.
140 tristate "Cavium ThunderX2 SoC PMU UNCORE"
141 depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
144 Provides support for ThunderX2 UNCORE events.
145 The SoC has PMU support in its L3 cache controller (L3C) and
146 in the DDR4 Memory Controller (DMC).
149 depends on ARCH_XGENE
150 bool "APM X-Gene SoC PMU"
153 Say y if you want to use APM X-Gene SoC performance monitors.
156 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
159 Enable perf support for the ARMv8.2 Statistical Profiling
160 Extension, which provides periodic sampling of operations in
161 the CPU pipeline and reports this via the perf AUX interface.
163 config ARM_DMC620_PMU
164 tristate "Enable PMU support for the ARM DMC-620 memory controller"
165 depends on (ARM64 && ACPI) || COMPILE_TEST
167 Support for PMU events monitoring on the ARM DMC-620 memory
170 source "drivers/perf/hisilicon/Kconfig"