1 # SPDX-License-Identifier: GPL-2.0-only
3 # Performance Monitor Drivers
6 menu "Performance monitor support"
10 tristate "ARM CCI PMU driver"
11 depends on (ARM && CPU_V7) || ARM64
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
15 Interconnect) family of products.
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
22 depends on ARM_CCI_PMU
23 select ARM_CCI400_COMMON
25 CCI-400 provides 4 independent event counters counting events related
26 to the connected slave/master interfaces, plus a cycle counter.
29 bool "support CCI-500/CCI-550"
31 depends on ARM_CCI_PMU
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
34 count events pertaining to the slave/master interfaces as well as the
35 internal events to the CCI.
38 tristate "ARM CCN driver support"
39 depends on ARM || ARM64
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
46 depends on ARM64 || (COMPILE_TEST && 64BIT)
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 depends on ARM || ARM64
53 bool "ARM PMU framework"
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
64 Say y if you want to use CPU performance monitors on RISCV-based
65 systems. This provides the core PMU framework that abstracts common
66 PMU functionalities in a core library so that different PMU drivers
70 depends on ARM_PMU && ACPI
73 config ARM_SMMU_V3_PMU
74 tristate "ARM SMMUv3 Performance Monitors Extension"
75 depends on ARM64 && ACPI
77 Provides support for the ARM SMMUv3 Performance Monitor Counter
78 Groups (PMCG), which provide monitoring of transactions passing
79 through the SMMU and allow the resulting information to be filtered
80 based on the Stream ID of the corresponding master.
83 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
86 Provides support for performance monitor unit in ARM DynamIQ Shared
87 Unit (DSU). The DSU integrates one or more cores with an L3 memory
88 system, control logic. The PMU allows counting various events related
91 config FSL_IMX8_DDR_PMU
92 tristate "Freescale i.MX8 DDR perf monitor"
95 Provides support for the DDR performance monitor in i.MX8, which
96 can give information about memory throughput and other related
100 bool "Qualcomm Technologies L2-cache PMU"
101 depends on ARCH_QCOM && ARM64 && ACPI
102 select QCOM_KRYO_L2_ACCESSORS
104 Provides support for the L2 cache performance monitor unit (PMU)
105 in Qualcomm Technologies processors.
106 Adds the L2 cache PMU into the perf events subsystem for
107 monitoring L2 cache events.
110 bool "Qualcomm Technologies L3-cache PMU"
111 depends on ARCH_QCOM && ARM64 && ACPI
112 select QCOM_IRQ_COMBINER
114 Provides support for the L3 cache performance monitor unit (PMU)
115 in Qualcomm Technologies processors.
116 Adds the L3 cache PMU into the perf events subsystem for
117 monitoring L3 cache events.
120 tristate "Cavium ThunderX2 SoC PMU UNCORE"
121 depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
124 Provides support for ThunderX2 UNCORE events.
125 The SoC has PMU support in its L3 cache controller (L3C) and
126 in the DDR4 Memory Controller (DMC).
129 depends on ARCH_XGENE
130 bool "APM X-Gene SoC PMU"
133 Say y if you want to use APM X-Gene SoC performance monitors.
136 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
139 Enable perf support for the ARMv8.2 Statistical Profiling
140 Extension, which provides periodic sampling of operations in
141 the CPU pipeline and reports this via the perf AUX interface.
143 config ARM_DMC620_PMU
144 tristate "Enable PMU support for the ARM DMC-620 memory controller"
145 depends on (ARM64 && ACPI) || COMPILE_TEST
147 Support for PMU events monitoring on the ARM DMC-620 memory
150 source "drivers/perf/hisilicon/Kconfig"