1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on Linux PCI-EP driver written by
6 * Kishon Vijay Abraham I <kishon@ti.com>
9 * Written by Ramon Fried <ramon.fried@gmail.com>
12 #define LOG_CATEGORY UCLASS_PCI_EP
17 #include <asm/global_data.h>
18 #include <linux/log2.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
25 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
27 if (!ops->write_header)
30 return ops->write_header(dev, fn, hdr);
33 int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
35 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
37 if (!ops->read_header)
40 return ops->read_header(dev, fn, hdr);
43 int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
45 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
46 int flags = ep_bar->flags;
48 /* Some basic bar validity checks */
49 if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
52 if ((ep_bar->barno == BAR_5 &&
53 (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
54 ((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
55 (flags & PCI_BASE_ADDRESS_IO_MASK)) ||
56 (upper_32_bits(ep_bar->size) &&
57 !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
63 return ops->set_bar(dev, func_no, ep_bar);
66 int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
69 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
71 /* Some basic bar validity checks */
72 if (barno > BAR_5 || barno < BAR_0)
78 return ops->read_bar(dev, func_no, ep_bar, barno);
81 int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar)
83 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
88 return ops->clear_bar(dev, func_num, bar);
91 int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr,
92 u64 pci_addr, size_t size)
94 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
99 return ops->map_addr(dev, func_no, addr, pci_addr, size);
102 int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr)
104 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
106 if (!ops->unmap_addr)
109 return ops->unmap_addr(dev, func_no, addr);
112 int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts)
114 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
123 /* MSI spec permits allocation of
124 * only 1, 2, 4, 8, 16, 32 interrupts
126 encode_int = order_base_2(interrupts);
128 return ops->set_msi(dev, func_no, encode_int);
131 int pci_ep_get_msi(struct udevice *dev, uint func_no)
133 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
139 interrupt = ops->get_msi(dev, func_no);
144 /* Translate back from order base 2*/
145 interrupt = 1 << interrupt;
150 int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts)
152 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
154 if (interrupts < 1 || interrupts > 2048)
160 return ops->set_msix(dev, func_no, interrupts - 1);
163 int pci_ep_get_msix(struct udevice *dev, uint func_no)
165 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
171 interrupt = ops->get_msix(dev, func_no);
176 return interrupt + 1;
179 int pci_ep_raise_irq(struct udevice *dev, uint func_no,
180 enum pci_ep_irq_type type, uint interrupt_num)
182 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
187 return ops->raise_irq(dev, func_no, type, interrupt_num);
190 int pci_ep_start(struct udevice *dev)
192 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
197 return ops->start(dev);
200 int pci_ep_stop(struct udevice *dev)
202 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
207 return ops->stop(dev);
210 UCLASS_DRIVER(pci_ep) = {
213 .flags = DM_UC_FLAG_SEQ_ALIAS,
216 int pci_ep_init(void)
220 for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
222 uclass_next_device_check(&dev)) {