2 * arch/ppc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
24 #define DEBUGF(x...) printf(x)
29 #define PCIAUTO_IDE_MODE_MASK 0x05
35 void pciauto_region_init(struct pci_region* res)
37 res->bus_lower = res->bus_start;
40 void pciauto_region_align(struct pci_region *res, unsigned long size)
42 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
45 int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
50 DEBUGF("No resource");
54 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
56 if (addr - res->bus_start + size > res->size) {
57 DEBUGF("No room in resource");
61 res->bus_lower = addr + size;
63 DEBUGF("address=0x%lx", addr);
77 void pciauto_setup_device(struct pci_controller *hose,
78 pci_dev_t dev, int bars_num,
79 struct pci_region *mem,
80 struct pci_region *io)
82 unsigned int bar_value, bar_response, bar_size;
83 unsigned int cmdstat = 0;
84 struct pci_region *bar_res;
88 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
89 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
91 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
92 /* Tickle the BAR and get the response */
93 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
94 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
96 /* If BAR is not implemented go to the next BAR */
102 /* Check the BAR type and set our address mask */
103 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
104 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
107 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
109 if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
110 PCI_BASE_ADDRESS_MEM_TYPE_64)
113 bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
116 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
119 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
120 /* Write it out and update our limit */
121 pci_hose_write_config_dword(hose, dev, bar, bar_value);
124 * If we are a 64-bit decoder then increment to the
125 * upper 32 bits of the bar and force it to locate
126 * in the lower 4GB of memory.
130 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
133 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
134 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
142 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
143 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
144 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
147 static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
148 pci_dev_t dev, int sub_bus)
150 struct pci_region *pci_mem = hose->pci_mem;
151 struct pci_region *pci_io = hose->pci_io;
152 unsigned int cmdstat;
154 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
156 /* Configure bus number registers */
157 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
158 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
159 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
162 /* Round memory allocator to 1MB boundary */
163 pciauto_region_align(pci_mem, 0x100000);
165 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
166 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
167 (pci_mem->bus_lower & 0xfff00000) >> 16);
169 cmdstat |= PCI_COMMAND_MEMORY;
173 /* Round I/O allocator to 4KB boundary */
174 pciauto_region_align(pci_io, 0x1000);
176 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
177 (pci_io->bus_lower & 0x0000f000) >> 8);
178 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
179 (pci_io->bus_lower & 0xffff0000) >> 16);
181 cmdstat |= PCI_COMMAND_IO;
184 /* We don't support prefetchable memory for now, so disable */
185 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
186 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
188 /* Enable memory and I/O accesses, enable bus master */
189 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
192 static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
193 pci_dev_t dev, int sub_bus)
195 struct pci_region *pci_mem = hose->pci_mem;
196 struct pci_region *pci_io = hose->pci_io;
198 /* Configure bus number registers */
199 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
202 /* Round memory allocator to 1MB boundary */
203 pciauto_region_align(pci_mem, 0x100000);
205 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
206 (pci_mem->bus_lower-1) >> 16);
210 /* Round I/O allocator to 4KB boundary */
211 pciauto_region_align(pci_io, 0x1000);
213 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
214 ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
215 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
216 ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
224 void pciauto_config_init(struct pci_controller *hose)
228 hose->pci_io = hose->pci_mem = NULL;
230 for (i=0; i<hose->region_count; i++) {
231 switch(hose->regions[i].flags) {
234 hose->pci_io->size < hose->regions[i].size)
235 hose->pci_io = hose->regions + i;
238 if (!hose->pci_mem ||
239 hose->pci_mem->size < hose->regions[i].size)
240 hose->pci_mem = hose->regions + i;
247 pciauto_region_init(hose->pci_mem);
249 DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
250 hose->pci_mem->bus_start,
251 hose->pci_mem->bus_start + hose->pci_mem->size - 1);
255 pciauto_region_init(hose->pci_io);
257 DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
258 hose->pci_io->bus_start,
259 hose->pci_io->bus_start + hose->pci_io->size - 1);
263 /* HJF: Changed this to return int. I think this is required
264 * to get the correct result when scanning bridges
266 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
268 unsigned int sub_bus = PCI_BUS(dev);
269 unsigned short class;
270 unsigned char prg_iface;
273 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
276 case PCI_CLASS_BRIDGE_PCI:
277 hose->current_busno++;
278 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
280 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
282 /* Passing in current_busno allows for sibling P2P bridges */
283 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
285 * need to figure out if this is a subordinate bridge on the bus
286 * to be able to properly set the pri/sec/sub bridge registers.
288 n = pci_hose_scan_bus(hose, hose->current_busno);
290 /* figure out the deepest we've gone for this leg */
291 sub_bus = max(n, sub_bus);
292 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
294 sub_bus = hose->current_busno;
297 case PCI_CLASS_STORAGE_IDE:
298 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
299 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
300 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
304 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
307 case PCI_CLASS_BRIDGE_CARDBUS:
308 /* just do a minimal setup of the bridge, let the OS take care of the rest */
309 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
311 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
313 hose->current_busno++;
316 #ifdef CONFIG_MPC5200
317 case PCI_CLASS_BRIDGE_OTHER:
318 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
324 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
331 #endif /* CONFIG_PCI */