2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * SPDX-License-Identifier: GPL-2.0+
9 * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
10 * write protection (for flash) in function 0 of the chip.
11 * Enabling function 1 (IDE controller of the chip.
22 #define out8(addr,val) do { \
23 out_8((u8*) (addr),(val)); udelay(1); \
25 #define out16(addr,val) do { \
26 out_be16((u16*) (addr),(val)); udelay(1); \
29 extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
31 void initialise_pic(void);
32 void initialise_dma(void);
34 void initialise_w83c553f(void)
41 devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
44 printf("Error: Cannot find W83C553F controller on any PCI bus.");
48 pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
49 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
50 pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
52 pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8);
53 /* 16 MB ISA memory space */
54 reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
55 reg8 &= ~IPADCR_MBE512;
56 pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
58 pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8);
59 /* switch off BIOS write protection */
60 reg8 |= CSCR_UBIOSCSE;
62 pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
72 pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
73 pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
76 * Read IDE bus offsets from function 1 device.
77 * We must unmask the LSB indicating that ist is an IO address.
79 devbusfn |= PCI_BDF(0,0,1);
82 * Switch off legacy IRQ for IDE and IDE port 1.
84 pci_write_config_byte(devbusfn, 0x09, 0x8F);
86 pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32);
87 reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
88 pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
90 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
91 ide_bus_offset[0] &= ~1;
92 #if CONFIG_SYS_IDE_MAXBUS > 1
93 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
94 ide_bus_offset[1] &= ~1;
98 * Enable function 1, IDE -> busmastering and IO space access
100 pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
101 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
102 pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
105 * Initialise ISA interrupt controller
110 * Initialise DMA controller
115 void initialise_pic(void)
117 out8(W83C553F_PIC1_ICW1, 0x11);
118 out8(W83C553F_PIC1_ICW2, 0x08);
119 out8(W83C553F_PIC1_ICW3, 0x04);
120 out8(W83C553F_PIC1_ICW4, 0x01);
121 out8(W83C553F_PIC1_OCW1, 0xfb);
122 out8(W83C553F_PIC1_ELC, 0x20);
124 out8(W83C553F_PIC2_ICW1, 0x11);
125 out8(W83C553F_PIC2_ICW2, 0x08);
126 out8(W83C553F_PIC2_ICW3, 0x02);
127 out8(W83C553F_PIC2_ICW4, 0x01);
128 out8(W83C553F_PIC2_OCW1, 0xff);
129 out8(W83C553F_PIC2_ELC, 0xce);
131 out8(W83C553F_TMR1_CMOD, 0x74);
133 out8(W83C553F_PIC2_OCW1, 0x20);
134 out8(W83C553F_PIC1_OCW1, 0x20);
136 out8(W83C553F_PIC2_OCW1, 0x2b);
137 out8(W83C553F_PIC1_OCW1, 0x2b);
140 void initialise_dma(void)
142 unsigned int channel;
143 unsigned int rvalue1, rvalue2;
145 /* perform a H/W reset of the devices */
147 out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
148 out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
150 /* initialise all channels to a sane state */
152 for (channel = 0; channel < 4; channel++) {
154 * dependent upon the channel, setup the specifics:
158 * autoinitialize-disable
164 rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
165 rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
168 rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
169 rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
172 rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
173 rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
176 rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
177 rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
185 /* write to write mode registers */
187 out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
188 out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
191 /* enable all channels */
193 out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
194 out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
196 * initialize the global DMA configuration
201 * channel group enable
204 out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
205 out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);