2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
28 static void pci_std_update_resource(struct pci_dev *dev, int resno)
30 struct pci_bus_region region;
35 enum pci_bar_type type;
36 struct resource *res = dev->resource + resno;
38 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
43 * Ignore resources for unimplemented BARs and unused resource slots
49 if (res->flags & IORESOURCE_UNSET)
53 * Ignore non-moveable resources. This might be legacy resources for
54 * which no functional BAR register exists or another important
55 * system resource we shouldn't move around.
57 if (res->flags & IORESOURCE_PCI_FIXED)
60 pcibios_resource_to_bus(dev->bus, ®ion, res);
63 if (res->flags & IORESOURCE_IO) {
64 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
65 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
66 } else if (resno == PCI_ROM_RESOURCE) {
67 mask = (u32)PCI_ROM_ADDRESS_MASK;
69 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
70 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
73 reg = pci_resource_bar(dev, resno, &type);
76 if (type != pci_bar_unknown) {
77 if (!(res->flags & IORESOURCE_ROM_ENABLE))
79 new |= PCI_ROM_ADDRESS_ENABLE;
83 * We can't update a 64-bit BAR atomically, so when possible,
84 * disable decoding so that a half-updated BAR won't conflict
85 * with another device.
87 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
89 pci_read_config_word(dev, PCI_COMMAND, &cmd);
90 pci_write_config_word(dev, PCI_COMMAND,
91 cmd & ~PCI_COMMAND_MEMORY);
94 pci_write_config_dword(dev, reg, new);
95 pci_read_config_dword(dev, reg, &check);
97 if ((new ^ check) & mask) {
98 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
102 if (res->flags & IORESOURCE_MEM_64) {
103 new = region.start >> 16 >> 16;
104 pci_write_config_dword(dev, reg + 4, new);
105 pci_read_config_dword(dev, reg + 4, &check);
107 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
113 pci_write_config_word(dev, PCI_COMMAND, cmd);
116 void pci_update_resource(struct pci_dev *dev, int resno)
118 if (resno <= PCI_ROM_RESOURCE)
119 pci_std_update_resource(dev, resno);
120 #ifdef CONFIG_PCI_IOV
121 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
122 pci_iov_update_resource(dev, resno);
126 int pci_claim_resource(struct pci_dev *dev, int resource)
128 struct resource *res = &dev->resource[resource];
129 struct resource *root, *conflict;
131 if (res->flags & IORESOURCE_UNSET) {
132 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
137 root = pci_find_parent_resource(dev, res);
139 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
141 res->flags |= IORESOURCE_UNSET;
145 conflict = request_resource_conflict(root, res);
147 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
148 resource, res, conflict->name, conflict);
149 res->flags |= IORESOURCE_UNSET;
155 EXPORT_SYMBOL(pci_claim_resource);
157 void pci_disable_bridge_window(struct pci_dev *dev)
159 dev_info(&dev->dev, "disabling bridge mem windows\n");
161 /* MMIO Base/Limit */
162 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
164 /* Prefetchable MMIO Base/Limit */
165 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
166 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
167 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
171 * Generic function that returns a value indicating that the device's
172 * original BIOS BAR address was not saved and so is not available for
175 * Can be over-ridden by architecture specific code that implements
176 * reinstatement functionality rather than leaving it disabled when
177 * normal allocation attempts fail.
179 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
184 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
185 int resno, resource_size_t size)
187 struct resource *root, *conflict;
188 resource_size_t fw_addr, start, end;
190 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
196 res->start = fw_addr;
197 res->end = res->start + size - 1;
198 res->flags &= ~IORESOURCE_UNSET;
200 root = pci_find_parent_resource(dev, res);
202 if (res->flags & IORESOURCE_IO)
203 root = &ioport_resource;
205 root = &iomem_resource;
208 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
210 conflict = request_resource_conflict(root, res);
212 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
213 resno, res, conflict->name, conflict);
216 res->flags |= IORESOURCE_UNSET;
222 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
223 int resno, resource_size_t size, resource_size_t align)
225 struct resource *res = dev->resource + resno;
229 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
232 * First, try exact prefetching match. Even if a 64-bit
233 * prefetchable bridge window is below 4GB, we can't put a 32-bit
234 * prefetchable resource in it because pbus_size_mem() assumes a
235 * 64-bit window will contain no 32-bit resources. If we assign
236 * things differently than they were sized, not everything will fit.
238 ret = pci_bus_alloc_resource(bus, res, size, align, min,
239 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
240 pcibios_align_resource, dev);
245 * If the prefetchable window is only 32 bits wide, we can put
246 * 64-bit prefetchable resources in it.
248 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
249 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
250 ret = pci_bus_alloc_resource(bus, res, size, align, min,
252 pcibios_align_resource, dev);
258 * If we didn't find a better match, we can put any memory resource
259 * in a non-prefetchable window. If this resource is 32 bits and
260 * non-prefetchable, the first call already tried the only possibility
261 * so we don't need to try again.
263 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
264 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
265 pcibios_align_resource, dev);
270 static int _pci_assign_resource(struct pci_dev *dev, int resno,
271 resource_size_t size, resource_size_t min_align)
277 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
278 if (!bus->parent || !bus->self->transparent)
286 int pci_assign_resource(struct pci_dev *dev, int resno)
288 struct resource *res = dev->resource + resno;
289 resource_size_t align, size;
292 if (res->flags & IORESOURCE_PCI_FIXED)
295 res->flags |= IORESOURCE_UNSET;
296 align = pci_resource_alignment(dev, res);
298 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
303 size = resource_size(res);
304 ret = _pci_assign_resource(dev, resno, size, align);
307 * If we failed to assign anything, let's try the address
308 * where firmware left it. That at least has a chance of
309 * working, which is better than just leaving it disabled.
312 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
313 ret = pci_revert_fw_address(res, dev, resno, size);
317 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
322 res->flags &= ~IORESOURCE_UNSET;
323 res->flags &= ~IORESOURCE_STARTALIGN;
324 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
325 if (resno < PCI_BRIDGE_RESOURCES)
326 pci_update_resource(dev, resno);
330 EXPORT_SYMBOL(pci_assign_resource);
332 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
333 resource_size_t min_align)
335 struct resource *res = dev->resource + resno;
337 resource_size_t new_size;
340 if (res->flags & IORESOURCE_PCI_FIXED)
344 res->flags |= IORESOURCE_UNSET;
346 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
351 /* already aligned with min_align */
352 new_size = resource_size(res) + addsize;
353 ret = _pci_assign_resource(dev, resno, new_size, min_align);
356 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
357 resno, res, (unsigned long long) addsize);
361 res->flags &= ~IORESOURCE_UNSET;
362 res->flags &= ~IORESOURCE_STARTALIGN;
363 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
364 resno, res, (unsigned long long) addsize);
365 if (resno < PCI_BRIDGE_RESOURCES)
366 pci_update_resource(dev, resno);
371 int pci_enable_resources(struct pci_dev *dev, int mask)
377 pci_read_config_word(dev, PCI_COMMAND, &cmd);
380 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
381 if (!(mask & (1 << i)))
384 r = &dev->resource[i];
386 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
388 if ((i == PCI_ROM_RESOURCE) &&
389 (!(r->flags & IORESOURCE_ROM_ENABLE)))
392 if (r->flags & IORESOURCE_UNSET) {
393 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
399 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
404 if (r->flags & IORESOURCE_IO)
405 cmd |= PCI_COMMAND_IO;
406 if (r->flags & IORESOURCE_MEM)
407 cmd |= PCI_COMMAND_MEMORY;
410 if (cmd != old_cmd) {
411 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
413 pci_write_config_word(dev, PCI_COMMAND, cmd);