2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
37 static void quirk_mmio_always_on(struct pci_dev *dev)
39 dev->mmio_always_on = 1;
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
48 static void quirk_mellanox_tavor(struct pci_dev *dev)
50 dev->broken_parity_status = 1; /* This device gives false positives */
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev *dev)
59 struct pci_dev *d = NULL;
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
69 pci_write_config_byte(d, 0x82, dlc);
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
80 This appears to be BIOS not version dependent. So presumably there is a
83 static void quirk_isa_dma_hangs(struct pci_dev *dev)
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy=1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123 * Chipsets where PCI->PCI transfers vanish or hang
125 static void quirk_nopcipci(struct pci_dev *dev)
127 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
135 static void quirk_nopciamd(struct pci_dev *dev)
138 pci_read_config_byte(dev, 0x08, &rev);
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148 * Triton requires workarounds to be used by the drivers
150 static void quirk_triton(struct pci_dev *dev)
152 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * and http://www.georgebreese.com/net/software/#PCI
167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
168 * the info on which Mr Breese based his work.
170 * Updated based on further information from the site and also on
171 * information provided by VIA
173 static void quirk_vialatency(struct pci_dev *dev)
177 /* Ok we have a potential problem chipset here. Now see if we have
178 a buggy southbridge */
180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
183 /* Check for buggy part revisions */
184 if (p->revision < 0x40 || p->revision > 0x42)
187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
188 if (p==NULL) /* No problem parts */
190 /* Check for buggy part revisions */
191 if (p->revision < 0x10 || p->revision > 0x12)
196 * Ok we have the problem. Now set the PCI master grant to
197 * occur every master grant. The apparent bug is that under high
198 * PCI load (quite common in Linux of course) you can get data
199 * loss when the CPU is held off the bus for 3 bus master requests
200 * This happens to include the IDE controllers....
202 * VIA only apply this fix when an SB Live! is present but under
203 * both Linux and Windows this isn't enough, and we have seen
204 * corruption without SB Live! but with things like 3 UDMA IDE
205 * controllers. So we ignore that bit of the VIA recommendation..
208 pci_read_config_byte(dev, 0x76, &busarb);
209 /* Set bit 4 and bi 5 of byte 76 to 0x01
210 "Master priority rotation on every PCI master grant */
213 pci_write_config_byte(dev, 0x76, busarb);
214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
221 /* Must restore this on a resume from RAM */
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
227 * VIA Apollo VP3 needs ETBF on BT848/878
229 static void quirk_viaetbf(struct pci_dev *dev)
231 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
233 pci_pci_problems |= PCIPCI_VIAETBF;
236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
238 static void quirk_vsfx(struct pci_dev *dev)
240 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
242 pci_pci_problems |= PCIPCI_VSFX;
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
248 * Ali Magik requires workarounds to be used by the drivers
249 * that DMA to AGP space. Latency must be set to 0xA and triton
250 * workaround applied too
251 * [Info kindly provided by ALi]
253 static void quirk_alimagik(struct pci_dev *dev)
255 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
264 * Natoma has some interesting boundary conditions with Zoran stuff
267 static void quirk_natoma(struct pci_dev *dev)
269 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
271 pci_pci_problems |= PCIPCI_NATOMA;
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
282 * This chip can cause PCI parity errors if config register 0xA0 is read
283 * while DMAs are occurring.
285 static void quirk_citrine(struct pci_dev *dev)
287 dev->cfg_size = 0xA0;
289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
291 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
292 static void quirk_extend_bar_to_page(struct pci_dev *dev)
296 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
297 struct resource *r = &dev->resource[i];
299 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
300 r->end = PAGE_SIZE - 1;
302 r->flags |= IORESOURCE_UNSET;
303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
312 * If it's needed, re-allocate the region.
314 static void quirk_s3_64M(struct pci_dev *dev)
316 struct resource *r = &dev->resource[0];
318 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
327 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
328 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
329 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
330 * (which conflicts w/ BAR1's memory range).
332 static void quirk_cs5536_vsa(struct pci_dev *dev)
334 if (pci_resource_len(dev, 0) != 8) {
335 struct resource *res = &dev->resource[0];
336 res->end = res->start + 8 - 1;
337 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
338 "(incorrect header); workaround applied.\n");
341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
343 static void quirk_io_region(struct pci_dev *dev, int port,
344 unsigned size, int nr, const char *name)
347 struct pci_bus_region bus_region;
348 struct resource *res = dev->resource + nr;
350 pci_read_config_word(dev, port, ®ion);
351 region &= ~(size - 1);
356 res->name = pci_name(dev);
357 res->flags = IORESOURCE_IO;
359 /* Convert from PCI bus to resource space */
360 bus_region.start = region;
361 bus_region.end = region + size - 1;
362 pcibios_bus_to_resource(dev->bus, res, &bus_region);
364 if (!pci_claim_resource(dev, nr))
365 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
369 * ATI Northbridge setups MCE the processor if you even
370 * read somewhere between 0x3b0->0x3bb or read 0x3d3
372 static void quirk_ati_exploding_mce(struct pci_dev *dev)
374 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
375 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
376 request_region(0x3b0, 0x0C, "RadeonIGP");
377 request_region(0x3d3, 0x01, "RadeonIGP");
379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
382 * Let's make the southbridge information explicit instead
383 * of having to worry about people probing the ACPI areas,
384 * for example.. (Yes, it happens, and if you read the wrong
385 * ACPI register it will put the machine to sleep with no
386 * way of waking it up again. Bummer).
388 * ALI M7101: Two IO regions pointed to by words at
389 * 0xE0 (64 bytes of ACPI registers)
390 * 0xE2 (32 bytes of SMB registers)
392 static void quirk_ali7101_acpi(struct pci_dev *dev)
394 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
395 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
399 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
402 u32 mask, size, base;
404 pci_read_config_dword(dev, port, &devres);
405 if ((devres & enable) != enable)
407 mask = (devres >> 16) & 15;
408 base = devres & 0xffff;
411 unsigned bit = size >> 1;
412 if ((bit & mask) == bit)
417 * For now we only print it out. Eventually we'll want to
418 * reserve it (at least if it's in the 0x1000+ range), but
419 * let's get enough confirmation reports first.
422 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
425 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
428 u32 mask, size, base;
430 pci_read_config_dword(dev, port, &devres);
431 if ((devres & enable) != enable)
433 base = devres & 0xffff0000;
434 mask = (devres & 0x3f) << 16;
437 unsigned bit = size >> 1;
438 if ((bit & mask) == bit)
443 * For now we only print it out. Eventually we'll want to
444 * reserve it, but let's get enough confirmation reports first.
447 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
451 * PIIX4 ACPI: Two IO regions pointed to by longwords at
452 * 0x40 (64 bytes of ACPI registers)
453 * 0x90 (16 bytes of SMB registers)
454 * and a few strange programmable PIIX4 device resources.
456 static void quirk_piix4_acpi(struct pci_dev *dev)
460 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
461 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
463 /* Device resource A has enables for some of the other ones */
464 pci_read_config_dword(dev, 0x5c, &res_a);
466 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
467 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
469 /* Device resource D is just bitfields for static resources */
471 /* Device 12 enabled? */
472 if (res_a & (1 << 29)) {
473 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
474 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
476 /* Device 13 enabled? */
477 if (res_a & (1 << 30)) {
478 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
479 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
481 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
482 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
487 #define ICH_PMBASE 0x40
488 #define ICH_ACPI_CNTL 0x44
489 #define ICH4_ACPI_EN 0x10
490 #define ICH6_ACPI_EN 0x80
491 #define ICH4_GPIOBASE 0x58
492 #define ICH4_GPIO_CNTL 0x5c
493 #define ICH4_GPIO_EN 0x10
494 #define ICH6_GPIOBASE 0x48
495 #define ICH6_GPIO_CNTL 0x4c
496 #define ICH6_GPIO_EN 0x10
499 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
500 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
501 * 0x58 (64 bytes of GPIO I/O space)
503 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
508 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
509 * with low legacy (and fixed) ports. We don't know the decoding
510 * priority and can't tell whether the legacy device or the one created
511 * here is really at that address. This happens on boards with broken
515 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
516 if (enable & ICH4_ACPI_EN)
517 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
518 "ICH4 ACPI/GPIO/TCO");
520 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
521 if (enable & ICH4_GPIO_EN)
522 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
536 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
540 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
541 if (enable & ICH6_ACPI_EN)
542 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
543 "ICH6 ACPI/GPIO/TCO");
545 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
546 if (enable & ICH6_GPIO_EN)
547 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
551 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
556 pci_read_config_dword(dev, reg, &val);
564 * This is not correct. It is 16, 32 or 64 bytes depending on
565 * register D31:F0:ADh bits 5:4.
567 * But this gets us at least _part_ of it.
575 /* Just print it out for now. We should reserve it after more debugging */
576 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
579 static void quirk_ich6_lpc(struct pci_dev *dev)
581 /* Shared ACPI/GPIO decode with all ICH6+ */
582 ich6_lpc_acpi_gpio(dev);
584 /* ICH6-specific generic IO decode */
585 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
586 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
591 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
596 pci_read_config_dword(dev, reg, &val);
603 * IO base in bits 15:2, mask in bits 23:18, both
607 mask = (val >> 16) & 0xfc;
610 /* Just print it out for now. We should reserve it after more debugging */
611 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
614 /* ICH7-10 has the same common LPC generic IO decode registers */
615 static void quirk_ich7_lpc(struct pci_dev *dev)
617 /* We share the common ACPI/GPIO decode with ICH6 */
618 ich6_lpc_acpi_gpio(dev);
620 /* And have 4 ICH7+ generic decodes */
621 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
622 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
623 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
624 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
641 * VIA ACPI: One IO region pointed to by longword at
642 * 0x48 or 0x20 (256 bytes of ACPI registers)
644 static void quirk_vt82c586_acpi(struct pci_dev *dev)
646 if (dev->revision & 0x10)
647 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
653 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
654 * 0x48 (256 bytes of ACPI registers)
655 * 0x70 (128 bytes of hardware monitoring register)
656 * 0x90 (16 bytes of SMB registers)
658 static void quirk_vt82c686_acpi(struct pci_dev *dev)
660 quirk_vt82c586_acpi(dev);
662 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
665 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
670 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
671 * 0x88 (128 bytes of power management registers)
672 * 0xd0 (16 bytes of SMB registers)
674 static void quirk_vt8235_acpi(struct pci_dev *dev)
676 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
677 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
682 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
683 * Disable fast back-to-back on the secondary bus segment
685 static void quirk_xio2000a(struct pci_dev *dev)
687 struct pci_dev *pdev;
690 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
691 "secondary bus fast back-to-back transfers disabled\n");
692 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
693 pci_read_config_word(pdev, PCI_COMMAND, &command);
694 if (command & PCI_COMMAND_FAST_BACK)
695 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
701 #ifdef CONFIG_X86_IO_APIC
703 #include <asm/io_apic.h>
706 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
707 * devices to the external APIC.
709 * TODO: When we have device-specific interrupt routers,
710 * this code will go away from quirks.
712 static void quirk_via_ioapic(struct pci_dev *dev)
717 tmp = 0; /* nothing routed to external APIC */
719 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
721 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
722 tmp == 0 ? "Disa" : "Ena");
724 /* Offset 0x58: External APIC IRQ output control */
725 pci_write_config_byte (dev, 0x58, tmp);
727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
728 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
731 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
732 * This leads to doubled level interrupt rates.
733 * Set this bit to get rid of cycle wastage.
734 * Otherwise uncritical.
736 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
739 #define BYPASS_APIC_DEASSERT 8
741 pci_read_config_byte(dev, 0x5B, &misc_control2);
742 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
743 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
744 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
751 * The AMD io apic can hang the box when an apic irq is masked.
752 * We check all revs >= B0 (yet not in the pre production!) as the bug
753 * is currently marked NoFix
755 * We have multiple reports of hangs with this chipset that went away with
756 * noapic specified. For the moment we assume it's the erratum. We may be wrong
757 * of course. However the advice is demonstrably good even if so..
759 static void quirk_amd_ioapic(struct pci_dev *dev)
761 if (dev->revision >= 0x02) {
762 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
763 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
768 static void quirk_ioapic_rmw(struct pci_dev *dev)
770 if (dev->devfn == 0 && dev->bus->number == 0)
773 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
774 #endif /* CONFIG_X86_IO_APIC */
777 * Some settings of MMRBC can lead to data corruption so block changes.
778 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
780 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
782 if (dev->subordinate && dev->revision <= 0x12) {
783 dev_info(&dev->dev, "AMD8131 rev %x detected; "
784 "disabling PCI-X MMRBC\n", dev->revision);
785 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
791 * FIXME: it is questionable that quirk_via_acpi
792 * is needed. It shows up as an ISA bridge, and does not
793 * support the PCI_INTERRUPT_LINE register at all. Therefore
794 * it seems like setting the pci_dev's 'irq' to the
795 * value of the ACPI SCI interrupt is only done for convenience.
798 static void quirk_via_acpi(struct pci_dev *d)
801 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
804 pci_read_config_byte(d, 0x42, &irq);
806 if (irq && (irq != 2))
809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
814 * VIA bridges which have VLink
817 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
819 static void quirk_via_bridge(struct pci_dev *dev)
821 /* See what bridge we have and find the device ranges */
822 switch (dev->device) {
823 case PCI_DEVICE_ID_VIA_82C686:
824 /* The VT82C686 is special, it attaches to PCI and can have
825 any device number. All its subdevices are functions of
826 that single device. */
827 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
828 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
830 case PCI_DEVICE_ID_VIA_8237:
831 case PCI_DEVICE_ID_VIA_8237A:
832 via_vlink_dev_lo = 15;
834 case PCI_DEVICE_ID_VIA_8235:
835 via_vlink_dev_lo = 16;
837 case PCI_DEVICE_ID_VIA_8231:
838 case PCI_DEVICE_ID_VIA_8233_0:
839 case PCI_DEVICE_ID_VIA_8233A:
840 case PCI_DEVICE_ID_VIA_8233C_0:
841 via_vlink_dev_lo = 17;
845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
855 * quirk_via_vlink - VIA VLink IRQ number update
858 * If the device we are dealing with is on a PIC IRQ we need to
859 * ensure that the IRQ line register which usually is not relevant
860 * for PCI cards, is actually written so that interrupts get sent
861 * to the right place.
862 * We only do this on systems where a VIA south bridge was detected,
863 * and only for VIA devices on the motherboard (see quirk_via_bridge
867 static void quirk_via_vlink(struct pci_dev *dev)
871 /* Check if we have VLink at all */
872 if (via_vlink_dev_lo == -1)
877 /* Don't quirk interrupts outside the legacy IRQ range */
878 if (!new_irq || new_irq > 15)
881 /* Internal device ? */
882 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
883 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
886 /* This is an internal VLink device on a PIC interrupt. The BIOS
887 ought to have set this but may not have, so we redo it */
889 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
890 if (new_irq != irq) {
891 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
893 udelay(15); /* unknown if delay really needed */
894 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
897 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
900 * VIA VT82C598 has its device ID settable and many BIOSes
901 * set it to the ID of VT82C597 for backward compatibility.
902 * We need to switch it off to be able to recognize the real
905 static void quirk_vt82c598_id(struct pci_dev *dev)
907 pci_write_config_byte(dev, 0xfc, 0);
908 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
913 * CardBus controllers have a legacy base address that enables them
914 * to respond as i82365 pcmcia controllers. We don't want them to
915 * do this even if the Linux CardBus driver is not loaded, because
916 * the Linux i82365 driver does not (and should not) handle CardBus.
918 static void quirk_cardbus_legacy(struct pci_dev *dev)
920 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
922 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
923 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
924 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
925 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
928 * Following the PCI ordering rules is optional on the AMD762. I'm not
929 * sure what the designers were smoking but let's not inhale...
931 * To be fair to AMD, it follows the spec by default, its BIOS people
934 static void quirk_amd_ordering(struct pci_dev *dev)
937 pci_read_config_dword(dev, 0x4C, &pcic);
940 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
941 pci_write_config_dword(dev, 0x4C, pcic);
942 pci_read_config_dword(dev, 0x84, &pcic);
943 pcic |= (1<<23); /* Required in this mode */
944 pci_write_config_dword(dev, 0x84, pcic);
947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
948 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
951 * DreamWorks provided workaround for Dunord I-3000 problem
953 * This card decodes and responds to addresses not apparently
954 * assigned to it. We force a larger allocation to ensure that
955 * nothing gets put too close to it.
957 static void quirk_dunord(struct pci_dev *dev)
959 struct resource *r = &dev->resource [1];
963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
966 * i82380FB mobile docking controller: its PCI-to-PCI bridge
967 * is subtractive decoding (transparent), and does indicate this
968 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
971 static void quirk_transparent_bridge(struct pci_dev *dev)
973 dev->transparent = 1;
975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
979 * Common misconfiguration of the MediaGX/Geode PCI master that will
980 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
981 * datasheets found at http://www.national.com/analog for info on what
982 * these bits do. <christer@weinigel.se>
984 static void quirk_mediagx_master(struct pci_dev *dev)
987 pci_read_config_byte(dev, 0x41, ®);
990 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
991 pci_write_config_byte(dev, 0x41, reg);
994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
995 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
998 * Ensure C0 rev restreaming is off. This is normally done by
999 * the BIOS but in the odd case it is not the results are corruption
1000 * hence the presence of a Linux check
1002 static void quirk_disable_pxb(struct pci_dev *pdev)
1006 if (pdev->revision != 0x04) /* Only C0 requires this */
1008 pci_read_config_word(pdev, 0x40, &config);
1009 if (config & (1<<6)) {
1011 pci_write_config_word(pdev, 0x40, config);
1012 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1016 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1018 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1020 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1023 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1025 pci_read_config_byte(pdev, 0x40, &tmp);
1026 pci_write_config_byte(pdev, 0x40, tmp|1);
1027 pci_write_config_byte(pdev, 0x9, 1);
1028 pci_write_config_byte(pdev, 0xa, 6);
1029 pci_write_config_byte(pdev, 0x40, tmp);
1031 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1032 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1035 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1036 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1038 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1040 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1041 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1042 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1045 * Serverworks CSB5 IDE does not fully support native mode
1047 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1050 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1054 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1055 /* PCI layer will sort out resources */
1058 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1061 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1063 static void quirk_ide_samemode(struct pci_dev *pdev)
1067 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1069 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1070 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1073 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1076 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1079 * Some ATA devices break if put into D3
1082 static void quirk_no_ata_d3(struct pci_dev *pdev)
1084 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1086 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1088 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1090 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1091 /* ALi loses some register settings that we cannot then restore */
1092 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1093 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1094 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1095 occur when mode detecting */
1096 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1097 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1099 /* This was originally an Alpha specific thing, but it really fits here.
1100 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1102 static void quirk_eisa_bridge(struct pci_dev *dev)
1104 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1110 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1111 * is not activated. The myth is that Asus said that they do not want the
1112 * users to be irritated by just another PCI Device in the Win98 device
1113 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1114 * package 2.7.0 for details)
1116 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1117 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1118 * becomes necessary to do this tweak in two steps -- the chosen trigger
1119 * is either the Host bridge (preferred) or on-board VGA controller.
1121 * Note that we used to unhide the SMBus that way on Toshiba laptops
1122 * (Satellite A40 and Tecra M2) but then found that the thermal management
1123 * was done by SMM code, which could cause unsynchronized concurrent
1124 * accesses to the SMBus registers, with potentially bad effects. Thus you
1125 * should be very careful when adding new entries: if SMM is accessing the
1126 * Intel SMBus, this is a very good reason to leave it hidden.
1128 * Likewise, many recent laptops use ACPI for thermal management. If the
1129 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1130 * natively, and keeping the SMBus hidden is the right thing to do. If you
1131 * are about to add an entry in the table below, please first disassemble
1132 * the DSDT and double-check that there is no code accessing the SMBus.
1134 static int asus_hides_smbus;
1136 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1138 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1139 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1140 switch(dev->subsystem_device) {
1141 case 0x8025: /* P4B-LX */
1142 case 0x8070: /* P4B */
1143 case 0x8088: /* P4B533 */
1144 case 0x1626: /* L3C notebook */
1145 asus_hides_smbus = 1;
1147 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1148 switch(dev->subsystem_device) {
1149 case 0x80b1: /* P4GE-V */
1150 case 0x80b2: /* P4PE */
1151 case 0x8093: /* P4B533-V */
1152 asus_hides_smbus = 1;
1154 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1155 switch(dev->subsystem_device) {
1156 case 0x8030: /* P4T533 */
1157 asus_hides_smbus = 1;
1159 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1160 switch (dev->subsystem_device) {
1161 case 0x8070: /* P4G8X Deluxe */
1162 asus_hides_smbus = 1;
1164 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1165 switch (dev->subsystem_device) {
1166 case 0x80c9: /* PU-DLS */
1167 asus_hides_smbus = 1;
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1170 switch (dev->subsystem_device) {
1171 case 0x1751: /* M2N notebook */
1172 case 0x1821: /* M5N notebook */
1173 case 0x1897: /* A6L notebook */
1174 asus_hides_smbus = 1;
1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1177 switch (dev->subsystem_device) {
1178 case 0x184b: /* W1N notebook */
1179 case 0x186a: /* M6Ne notebook */
1180 asus_hides_smbus = 1;
1182 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1183 switch (dev->subsystem_device) {
1184 case 0x80f2: /* P4P800-X */
1185 asus_hides_smbus = 1;
1187 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1188 switch (dev->subsystem_device) {
1189 case 0x1882: /* M6V notebook */
1190 case 0x1977: /* A6VA notebook */
1191 asus_hides_smbus = 1;
1193 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1194 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1195 switch(dev->subsystem_device) {
1196 case 0x088C: /* HP Compaq nc8000 */
1197 case 0x0890: /* HP Compaq nc6000 */
1198 asus_hides_smbus = 1;
1200 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1201 switch (dev->subsystem_device) {
1202 case 0x12bc: /* HP D330L */
1203 case 0x12bd: /* HP D530 */
1204 case 0x006a: /* HP Compaq nx9500 */
1205 asus_hides_smbus = 1;
1207 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1208 switch (dev->subsystem_device) {
1209 case 0x12bf: /* HP xw4100 */
1210 asus_hides_smbus = 1;
1212 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1213 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1214 switch(dev->subsystem_device) {
1215 case 0xC00C: /* Samsung P35 notebook */
1216 asus_hides_smbus = 1;
1218 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1219 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1220 switch(dev->subsystem_device) {
1221 case 0x0058: /* Compaq Evo N620c */
1222 asus_hides_smbus = 1;
1224 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1225 switch(dev->subsystem_device) {
1226 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1227 /* Motherboard doesn't have Host bridge
1228 * subvendor/subdevice IDs, therefore checking
1229 * its on-board VGA controller */
1230 asus_hides_smbus = 1;
1232 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1233 switch(dev->subsystem_device) {
1234 case 0x00b8: /* Compaq Evo D510 CMT */
1235 case 0x00b9: /* Compaq Evo D510 SFF */
1236 case 0x00ba: /* Compaq Evo D510 USDT */
1237 /* Motherboard doesn't have Host bridge
1238 * subvendor/subdevice IDs and on-board VGA
1239 * controller is disabled if an AGP card is
1240 * inserted, therefore checking USB UHCI
1242 asus_hides_smbus = 1;
1244 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1245 switch (dev->subsystem_device) {
1246 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1247 /* Motherboard doesn't have host bridge
1248 * subvendor/subdevice IDs, therefore checking
1249 * its on-board VGA controller */
1250 asus_hides_smbus = 1;
1254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1269 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1273 if (likely(!asus_hides_smbus))
1276 pci_read_config_word(dev, 0xF2, &val);
1278 pci_write_config_word(dev, 0xF2, val & (~0x8));
1279 pci_read_config_word(dev, 0xF2, &val);
1281 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1283 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1293 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1294 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1295 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1296 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1297 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1298 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1301 /* It appears we just have one such device. If not, we have a warning */
1302 static void __iomem *asus_rcba_base;
1303 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1307 if (likely(!asus_hides_smbus))
1309 WARN_ON(asus_rcba_base);
1311 pci_read_config_dword(dev, 0xF0, &rcba);
1312 /* use bits 31:14, 16 kB aligned */
1313 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1314 if (asus_rcba_base == NULL)
1318 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1322 if (likely(!asus_hides_smbus || !asus_rcba_base))
1324 /* read the Function Disable register, dword mode only */
1325 val = readl(asus_rcba_base + 0x3418);
1326 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1329 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1331 if (likely(!asus_hides_smbus || !asus_rcba_base))
1333 iounmap(asus_rcba_base);
1334 asus_rcba_base = NULL;
1335 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1338 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1340 asus_hides_smbus_lpc_ich6_suspend(dev);
1341 asus_hides_smbus_lpc_ich6_resume_early(dev);
1342 asus_hides_smbus_lpc_ich6_resume(dev);
1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1345 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1346 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1350 * SiS 96x south bridge: BIOS typically hides SMBus device...
1352 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1355 pci_read_config_byte(dev, 0x77, &val);
1357 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1358 pci_write_config_byte(dev, 0x77, val & ~0x10);
1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1365 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1366 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1367 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1368 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1371 * ... This is further complicated by the fact that some SiS96x south
1372 * bridges pretend to be 85C503/5513 instead. In that case see if we
1373 * spotted a compatible north bridge to make sure.
1374 * (pci_find_device doesn't work yet)
1376 * We can also enable the sis96x bit in the discovery register..
1378 #define SIS_DETECT_REGISTER 0x40
1380 static void quirk_sis_503(struct pci_dev *dev)
1385 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1386 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1387 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1388 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1389 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1394 * Ok, it now shows up as a 96x.. run the 96x quirk by
1395 * hand in case it has already been processed.
1396 * (depends on link order, which is apparently not guaranteed)
1398 dev->device = devid;
1399 quirk_sis_96x_smbus(dev);
1401 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1402 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1406 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1407 * and MC97 modem controller are disabled when a second PCI soundcard is
1408 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1411 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1414 int asus_hides_ac97 = 0;
1416 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1417 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1418 asus_hides_ac97 = 1;
1421 if (!asus_hides_ac97)
1424 pci_read_config_byte(dev, 0x50, &val);
1426 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1427 pci_read_config_byte(dev, 0x50, &val);
1429 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1431 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1435 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1437 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1440 * If we are using libata we can drive this chip properly but must
1441 * do this early on to make the additional device appear during
1444 static void quirk_jmicron_ata(struct pci_dev *pdev)
1446 u32 conf1, conf5, class;
1449 /* Only poke fn 0 */
1450 if (PCI_FUNC(pdev->devfn))
1453 pci_read_config_dword(pdev, 0x40, &conf1);
1454 pci_read_config_dword(pdev, 0x80, &conf5);
1456 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1457 conf5 &= ~(1 << 24); /* Clear bit 24 */
1459 switch (pdev->device) {
1460 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1461 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1462 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1463 /* The controller should be in single function ahci mode */
1464 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1467 case PCI_DEVICE_ID_JMICRON_JMB365:
1468 case PCI_DEVICE_ID_JMICRON_JMB366:
1469 /* Redirect IDE second PATA port to the right spot */
1472 case PCI_DEVICE_ID_JMICRON_JMB361:
1473 case PCI_DEVICE_ID_JMICRON_JMB363:
1474 case PCI_DEVICE_ID_JMICRON_JMB369:
1475 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1476 /* Set the class codes correctly and then direct IDE 0 */
1477 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1480 case PCI_DEVICE_ID_JMICRON_JMB368:
1481 /* The controller should be in single function IDE mode */
1482 conf1 |= 0x00C00000; /* Set 22, 23 */
1486 pci_write_config_dword(pdev, 0x40, conf1);
1487 pci_write_config_dword(pdev, 0x80, conf5);
1489 /* Update pdev accordingly */
1490 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1491 pdev->hdr_type = hdr & 0x7f;
1492 pdev->multifunction = !!(hdr & 0x80);
1494 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1495 pdev->class = class >> 8;
1497 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1500 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1502 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1503 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1504 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1505 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1506 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1507 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1508 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1509 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1510 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1511 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1512 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1514 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1518 #ifdef CONFIG_X86_IO_APIC
1519 static void quirk_alder_ioapic(struct pci_dev *pdev)
1523 if ((pdev->class >> 8) != 0xff00)
1526 /* the first BAR is the location of the IO APIC...we must
1527 * not touch this (and it's already covered by the fixmap), so
1528 * forcibly insert it into the resource tree */
1529 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1530 insert_resource(&iomem_resource, &pdev->resource[0]);
1532 /* The next five BARs all seem to be rubbish, so just clean
1534 for (i=1; i < 6; i++) {
1535 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1542 static void quirk_pcie_mch(struct pci_dev *pdev)
1547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1553 * It's possible for the MSI to get corrupted if shpc and acpi
1554 * are used together on certain PXH-based systems.
1556 static void quirk_pcie_pxh(struct pci_dev *dev)
1560 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1569 * Some Intel PCI Express chipsets have trouble with downstream
1570 * device power management.
1572 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1574 pci_pm_d3_delay = 120;
1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1600 #ifdef CONFIG_X86_IO_APIC
1602 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1603 * remap the original interrupt in the linux kernel to the boot interrupt, so
1604 * that a PCI device's interrupt handler is installed on the boot interrupt
1607 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1609 if (noioapicquirk || noioapicreroute)
1612 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1613 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1614 dev->vendor, dev->device);
1616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1624 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1625 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1626 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1627 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1628 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1629 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1630 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1631 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1634 * On some chipsets we can disable the generation of legacy INTx boot
1639 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1640 * 300641-004US, section 5.7.3.
1642 #define INTEL_6300_IOAPIC_ABAR 0x40
1643 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1645 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1647 u16 pci_config_word;
1652 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1653 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1654 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1656 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1657 dev->vendor, dev->device);
1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1660 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1663 * disable boot interrupts on HT-1000
1665 #define BC_HT1000_FEATURE_REG 0x64
1666 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1667 #define BC_HT1000_MAP_IDX 0xC00
1668 #define BC_HT1000_MAP_DATA 0xC01
1670 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1672 u32 pci_config_dword;
1678 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1679 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1680 BC_HT1000_PIC_REGS_ENABLE);
1682 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1683 outb(irq, BC_HT1000_MAP_IDX);
1684 outb(0x00, BC_HT1000_MAP_DATA);
1687 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1689 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1690 dev->vendor, dev->device);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1693 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1696 * disable boot interrupts on AMD and ATI chipsets
1699 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1700 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1701 * (due to an erratum).
1703 #define AMD_813X_MISC 0x40
1704 #define AMD_813X_NOIOAMODE (1<<0)
1705 #define AMD_813X_REV_B1 0x12
1706 #define AMD_813X_REV_B2 0x13
1708 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1710 u32 pci_config_dword;
1714 if ((dev->revision == AMD_813X_REV_B1) ||
1715 (dev->revision == AMD_813X_REV_B2))
1718 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1719 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1720 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1722 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1723 dev->vendor, dev->device);
1725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1726 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1728 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1730 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1732 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1734 u16 pci_config_word;
1739 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1740 if (!pci_config_word) {
1741 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1742 "already disabled\n", dev->vendor, dev->device);
1745 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1746 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1747 dev->vendor, dev->device);
1749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1751 #endif /* CONFIG_X86_IO_APIC */
1754 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1755 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1756 * Re-allocate the region if needed...
1758 static void quirk_tc86c001_ide(struct pci_dev *dev)
1760 struct resource *r = &dev->resource[0];
1762 if (r->start & 0x8) {
1767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1768 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1769 quirk_tc86c001_ide);
1772 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1773 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1774 * being read correctly if bit 7 of the base address is set.
1775 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1776 * Re-allocate the regions to a 256-byte boundary if necessary.
1778 static void quirk_plx_pci9050(struct pci_dev *dev)
1782 /* Fixed in revision 2 (PCI 9052). */
1783 if (dev->revision >= 2)
1785 for (bar = 0; bar <= 1; bar++)
1786 if (pci_resource_len(dev, bar) == 0x80 &&
1787 (pci_resource_start(dev, bar) & 0x80)) {
1788 struct resource *r = &dev->resource[bar];
1790 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1799 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1800 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1801 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1802 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1804 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1807 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1808 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1810 static void quirk_netmos(struct pci_dev *dev)
1812 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1813 unsigned int num_serial = dev->subsystem_device & 0xf;
1816 * These Netmos parts are multiport serial devices with optional
1817 * parallel ports. Even when parallel ports are present, they
1818 * are identified as class SERIAL, which means the serial driver
1819 * will claim them. To prevent this, mark them as class OTHER.
1820 * These combo devices should be claimed by parport_serial.
1822 * The subdevice ID is of the form 0x00PS, where <P> is the number
1823 * of parallel ports and <S> is the number of serial ports.
1825 switch (dev->device) {
1826 case PCI_DEVICE_ID_NETMOS_9835:
1827 /* Well, this rule doesn't hold for the following 9835 device */
1828 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1829 dev->subsystem_device == 0x0299)
1831 case PCI_DEVICE_ID_NETMOS_9735:
1832 case PCI_DEVICE_ID_NETMOS_9745:
1833 case PCI_DEVICE_ID_NETMOS_9845:
1834 case PCI_DEVICE_ID_NETMOS_9855:
1836 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1837 "%u serial); changing class SERIAL to OTHER "
1838 "(use parport_serial)\n",
1839 dev->device, num_parallel, num_serial);
1840 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1841 (dev->class & 0xff);
1845 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1846 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1848 static void quirk_e100_interrupt(struct pci_dev *dev)
1854 switch (dev->device) {
1855 /* PCI IDs taken from drivers/net/e100.c */
1857 case 0x1030 ... 0x1034:
1858 case 0x1038 ... 0x103E:
1859 case 0x1050 ... 0x1057:
1861 case 0x1064 ... 0x106B:
1862 case 0x1091 ... 0x1095:
1875 * Some firmware hands off the e100 with interrupts enabled,
1876 * which can cause a flood of interrupts if packets are
1877 * received before the driver attaches to the device. So
1878 * disable all e100 interrupts here. The driver will
1879 * re-enable them when it's ready.
1881 pci_read_config_word(dev, PCI_COMMAND, &command);
1883 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1887 * Check that the device is in the D0 power state. If it's not,
1888 * there is no point to look any further.
1891 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1892 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1896 /* Convert from PCI bus to resource space. */
1897 csr = ioremap(pci_resource_start(dev, 0), 8);
1899 dev_warn(&dev->dev, "Can't map e100 registers\n");
1903 cmd_hi = readb(csr + 3);
1905 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1912 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1913 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1916 * The 82575 and 82598 may experience data corruption issues when transitioning
1917 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1919 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1921 dev_info(&dev->dev, "Disabling L0s\n");
1922 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1928 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1934 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1937 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1939 static void fixup_rev1_53c810(struct pci_dev *dev)
1941 /* rev 1 ncr53c810 chips don't set the class at all which means
1942 * they don't get their resources remapped. Fix that here.
1945 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1946 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1947 dev->class = PCI_CLASS_STORAGE_SCSI;
1950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1952 /* Enable 1k I/O space granularity on the Intel P64H2 */
1953 static void quirk_p64h2_1k_io(struct pci_dev *dev)
1957 pci_read_config_word(dev, 0x40, &en1k);
1960 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1961 dev->io_window_1k = 1;
1964 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1966 /* Under some circumstances, AER is not linked with extended capabilities.
1967 * Force it to be linked by setting the corresponding control bit in the
1970 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1973 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1975 pci_write_config_byte(dev, 0xf41, b | 0x20);
1977 "Linking AER extended capability\n");
1981 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1982 quirk_nvidia_ck804_pcie_aer_ext_cap);
1983 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1984 quirk_nvidia_ck804_pcie_aer_ext_cap);
1986 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1989 * Disable PCI Bus Parking and PCI Master read caching on CX700
1990 * which causes unspecified timing errors with a VT6212L on the PCI
1991 * bus leading to USB2.0 packet loss.
1993 * This quirk is only enabled if a second (on the external PCI bus)
1994 * VT6212L is found -- the CX700 core itself also contains a USB
1995 * host controller with the same PCI ID as the VT6212L.
1998 /* Count VT6212L instances */
1999 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2000 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2003 /* p should contain the first (internal) VT6212L -- see if we have
2004 an external one by searching again */
2005 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2010 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2012 /* Turn off PCI Bus Parking */
2013 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2016 "Disabling VIA CX700 PCI parking\n");
2020 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2022 /* Turn off PCI Master read caching */
2023 pci_write_config_byte(dev, 0x72, 0x0);
2025 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2026 pci_write_config_byte(dev, 0x75, 0x1);
2028 /* Disable "Read FIFO Timer" */
2029 pci_write_config_byte(dev, 0x77, 0x0);
2032 "Disabling VIA CX700 PCI caching\n");
2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2039 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2040 * VPD end tag will hang the device. This problem was initially
2041 * observed when a vpd entry was created in sysfs
2042 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2043 * will dump 32k of data. Reading a full 32k will cause an access
2044 * beyond the VPD end tag causing the device to hang. Once the device
2045 * is hung, the bnx2 driver will not be able to reset the device.
2046 * We believe that it is legal to read beyond the end tag and
2047 * therefore the solution is to limit the read/write length.
2049 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2052 * Only disable the VPD capability for 5706, 5706S, 5708,
2053 * 5708S and 5709 rev. A
2055 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2056 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2057 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2058 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2059 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2060 (dev->revision & 0xf0) == 0x0)) {
2062 dev->vpd->len = 0x80;
2066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2067 PCI_DEVICE_ID_NX2_5706,
2068 quirk_brcm_570x_limit_vpd);
2069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2070 PCI_DEVICE_ID_NX2_5706S,
2071 quirk_brcm_570x_limit_vpd);
2072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2073 PCI_DEVICE_ID_NX2_5708,
2074 quirk_brcm_570x_limit_vpd);
2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2076 PCI_DEVICE_ID_NX2_5708S,
2077 quirk_brcm_570x_limit_vpd);
2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2079 PCI_DEVICE_ID_NX2_5709,
2080 quirk_brcm_570x_limit_vpd);
2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2082 PCI_DEVICE_ID_NX2_5709S,
2083 quirk_brcm_570x_limit_vpd);
2085 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2089 pci_read_config_dword(dev, 0xf4, &rev);
2091 /* Only CAP the MRRS if the device is a 5719 A0 */
2092 if (rev == 0x05719000) {
2093 int readrq = pcie_get_readrq(dev);
2095 pcie_set_readrq(dev, 2048);
2099 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2100 PCI_DEVICE_ID_TIGON3_5719,
2101 quirk_brcm_5719_limit_mrrs);
2103 /* Originally in EDAC sources for i82875P:
2104 * Intel tells BIOS developers to hide device 6 which
2105 * configures the overflow device access containing
2106 * the DRBs - this is where we expose device 6.
2107 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2109 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2113 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2114 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2115 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2119 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2120 quirk_unhide_mch_dev6);
2121 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2122 quirk_unhide_mch_dev6);
2124 #ifdef CONFIG_TILEPRO
2126 * The Tilera TILEmpower tilepro platform needs to set the link speed
2127 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2128 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2129 * capability register of the PEX8624 PCIe switch. The switch
2130 * supports link speed auto negotiation, but falsely sets
2131 * the link speed to 5GT/s.
2133 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2135 if (tile_plx_gen1) {
2136 pci_write_config_dword(dev, 0x98, 0x1);
2140 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2141 #endif /* CONFIG_TILEPRO */
2143 #ifdef CONFIG_PCI_MSI
2144 /* Some chipsets do not support MSI. We cannot easily rely on setting
2145 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2146 * some other buses controlled by the chipset even if Linux is not
2147 * aware of it. Instead of setting the flag on all buses in the
2148 * machine, simply disable MSI globally.
2150 static void quirk_disable_all_msi(struct pci_dev *dev)
2153 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2163 /* Disable MSI on chipsets that are known to not support it */
2164 static void quirk_disable_msi(struct pci_dev *dev)
2166 if (dev->subordinate) {
2167 dev_warn(&dev->dev, "MSI quirk detected; "
2168 "subordinate MSI disabled\n");
2169 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2177 * The APC bridge device in AMD 780 family northbridges has some random
2178 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2179 * we use the possible vendor/device IDs of the host bridge for the
2180 * declared quirk, and search for the APC bridge by slot number.
2182 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2184 struct pci_dev *apc_bridge;
2186 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2188 if (apc_bridge->device == 0x9602)
2189 quirk_disable_msi(apc_bridge);
2190 pci_dev_put(apc_bridge);
2193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2196 /* Go through the list of Hypertransport capabilities and
2197 * return 1 if a HT MSI capability is found and enabled */
2198 static int msi_ht_cap_enabled(struct pci_dev *dev)
2202 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2203 while (pos && ttl--) {
2206 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2209 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2210 flags & HT_MSI_FLAGS_ENABLE ?
2211 "enabled" : "disabled");
2212 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2215 pos = pci_find_next_ht_capability(dev, pos,
2216 HT_CAPTYPE_MSI_MAPPING);
2221 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2222 static void quirk_msi_ht_cap(struct pci_dev *dev)
2224 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2225 dev_warn(&dev->dev, "MSI quirk detected; "
2226 "subordinate MSI disabled\n");
2227 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2233 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2234 * MSI are supported if the MSI capability set in any of these mappings.
2236 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2238 struct pci_dev *pdev;
2240 if (!dev->subordinate)
2243 /* check HT MSI cap on this chipset and the root one.
2244 * a single one having MSI is enough to be sure that MSI are supported.
2246 pdev = pci_get_slot(dev->bus, 0);
2249 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2250 dev_warn(&dev->dev, "MSI quirk detected; "
2251 "subordinate MSI disabled\n");
2252 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2257 quirk_nvidia_ck804_msi_ht_cap);
2259 /* Force enable MSI mapping capability on HT bridges */
2260 static void ht_enable_msi_mapping(struct pci_dev *dev)
2264 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2265 while (pos && ttl--) {
2268 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2270 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2272 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2273 flags | HT_MSI_FLAGS_ENABLE);
2275 pos = pci_find_next_ht_capability(dev, pos,
2276 HT_CAPTYPE_MSI_MAPPING);
2279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2280 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2281 ht_enable_msi_mapping);
2283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2284 ht_enable_msi_mapping);
2286 /* The P5N32-SLI motherboards from Asus have a problem with msi
2287 * for the MCP55 NIC. It is not yet determined whether the msi problem
2288 * also affects other devices. As for now, turn off msi for this device.
2290 static void nvenet_msi_disable(struct pci_dev *dev)
2292 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2295 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2296 strstr(board_name, "P5N32-E SLI"))) {
2298 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2302 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2303 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2304 nvenet_msi_disable);
2307 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2308 * config register. This register controls the routing of legacy
2309 * interrupts from devices that route through the MCP55. If this register
2310 * is misprogrammed, interrupts are only sent to the BSP, unlike
2311 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2312 * having this register set properly prevents kdump from booting up
2313 * properly, so let's make sure that we have it set correctly.
2314 * Note that this is an undocumented register.
2316 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2320 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2323 pci_read_config_dword(dev, 0x74, &cfg);
2325 if (cfg & ((1 << 2) | (1 << 15))) {
2326 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2327 cfg &= ~((1 << 2) | (1 << 15));
2328 pci_write_config_dword(dev, 0x74, cfg);
2332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2333 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2334 nvbridge_check_legacy_irq_routing);
2336 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2337 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2338 nvbridge_check_legacy_irq_routing);
2340 static int ht_check_msi_mapping(struct pci_dev *dev)
2345 /* check if there is HT MSI cap or enabled on this device */
2346 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2347 while (pos && ttl--) {
2352 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2354 if (flags & HT_MSI_FLAGS_ENABLE) {
2361 pos = pci_find_next_ht_capability(dev, pos,
2362 HT_CAPTYPE_MSI_MAPPING);
2368 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2370 struct pci_dev *dev;
2375 dev_no = host_bridge->devfn >> 3;
2376 for (i = dev_no + 1; i < 0x20; i++) {
2377 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2381 /* found next host bridge ?*/
2382 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2388 if (ht_check_msi_mapping(dev)) {
2399 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2400 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2402 static int is_end_of_ht_chain(struct pci_dev *dev)
2408 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2413 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2415 ctrl_off = ((flags >> 10) & 1) ?
2416 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2417 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2419 if (ctrl & (1 << 6))
2426 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2428 struct pci_dev *host_bridge;
2433 dev_no = dev->devfn >> 3;
2434 for (i = dev_no; i >= 0; i--) {
2435 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2439 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2444 pci_dev_put(host_bridge);
2450 /* don't enable end_device/host_bridge with leaf directly here */
2451 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2452 host_bridge_with_leaf(host_bridge))
2455 /* root did that ! */
2456 if (msi_ht_cap_enabled(host_bridge))
2459 ht_enable_msi_mapping(dev);
2462 pci_dev_put(host_bridge);
2465 static void ht_disable_msi_mapping(struct pci_dev *dev)
2469 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2470 while (pos && ttl--) {
2473 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2475 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2477 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2478 flags & ~HT_MSI_FLAGS_ENABLE);
2480 pos = pci_find_next_ht_capability(dev, pos,
2481 HT_CAPTYPE_MSI_MAPPING);
2485 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2487 struct pci_dev *host_bridge;
2491 if (!pci_msi_enabled())
2494 /* check if there is HT MSI cap or enabled on this device */
2495 found = ht_check_msi_mapping(dev);
2502 * HT MSI mapping should be disabled on devices that are below
2503 * a non-Hypertransport host bridge. Locate the host bridge...
2505 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2506 if (host_bridge == NULL) {
2508 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2512 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2514 /* Host bridge is to HT */
2516 /* it is not enabled, try to enable it */
2518 ht_enable_msi_mapping(dev);
2520 nv_ht_enable_msi_mapping(dev);
2525 /* HT MSI is not enabled */
2529 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2530 ht_disable_msi_mapping(dev);
2533 pci_dev_put(host_bridge);
2536 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2538 return __nv_msi_ht_cap_quirk(dev, 1);
2541 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2543 return __nv_msi_ht_cap_quirk(dev, 0);
2546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2547 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2550 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2552 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2554 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2556 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2560 /* SB700 MSI issue will be fixed at HW level from revision A21,
2561 * we need check PCI REVISION ID of SMBus controller to get SB700
2564 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2569 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2570 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2573 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2575 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2576 if (dev->revision < 0x18) {
2577 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2578 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2582 PCI_DEVICE_ID_TIGON3_5780,
2583 quirk_msi_intx_disable_bug);
2584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2585 PCI_DEVICE_ID_TIGON3_5780S,
2586 quirk_msi_intx_disable_bug);
2587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2588 PCI_DEVICE_ID_TIGON3_5714,
2589 quirk_msi_intx_disable_bug);
2590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2591 PCI_DEVICE_ID_TIGON3_5714S,
2592 quirk_msi_intx_disable_bug);
2593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2594 PCI_DEVICE_ID_TIGON3_5715,
2595 quirk_msi_intx_disable_bug);
2596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2597 PCI_DEVICE_ID_TIGON3_5715S,
2598 quirk_msi_intx_disable_bug);
2600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2601 quirk_msi_intx_disable_ati_bug);
2602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2603 quirk_msi_intx_disable_ati_bug);
2604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2605 quirk_msi_intx_disable_ati_bug);
2606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2607 quirk_msi_intx_disable_ati_bug);
2608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2609 quirk_msi_intx_disable_ati_bug);
2611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2612 quirk_msi_intx_disable_bug);
2613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2614 quirk_msi_intx_disable_bug);
2615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2616 quirk_msi_intx_disable_bug);
2618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2619 quirk_msi_intx_disable_bug);
2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2621 quirk_msi_intx_disable_bug);
2622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2623 quirk_msi_intx_disable_bug);
2624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2625 quirk_msi_intx_disable_bug);
2626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2627 quirk_msi_intx_disable_bug);
2628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2629 quirk_msi_intx_disable_bug);
2630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2631 quirk_msi_intx_disable_qca_bug);
2632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2633 quirk_msi_intx_disable_qca_bug);
2634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2635 quirk_msi_intx_disable_qca_bug);
2636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2637 quirk_msi_intx_disable_qca_bug);
2638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2639 quirk_msi_intx_disable_qca_bug);
2640 #endif /* CONFIG_PCI_MSI */
2642 /* Allow manual resource allocation for PCI hotplug bridges
2643 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2644 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2645 * kernel fails to allocate resources when hotplug device is
2646 * inserted and PCI bus is rescanned.
2648 static void quirk_hotplug_bridge(struct pci_dev *dev)
2650 dev->is_hotplug_bridge = 1;
2653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2656 * This is a quirk for the Ricoh MMC controller found as a part of
2657 * some mulifunction chips.
2659 * This is very similar and based on the ricoh_mmc driver written by
2660 * Philip Langdale. Thank you for these magic sequences.
2662 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2663 * and one or both of cardbus or firewire.
2665 * It happens that they implement SD and MMC
2666 * support as separate controllers (and PCI functions). The linux SDHCI
2667 * driver supports MMC cards but the chip detects MMC cards in hardware
2668 * and directs them to the MMC controller - so the SDHCI driver never sees
2671 * To get around this, we must disable the useless MMC controller.
2672 * At that point, the SDHCI controller will start seeing them
2673 * It seems to be the case that the relevant PCI registers to deactivate the
2674 * MMC controller live on PCI function 0, which might be the cardbus controller
2675 * or the firewire controller, depending on the particular chip in question
2677 * This has to be done early, because as soon as we disable the MMC controller
2678 * other pci functions shift up one level, e.g. function #2 becomes function
2679 * #1, and this will confuse the pci core.
2682 #ifdef CONFIG_MMC_RICOH_MMC
2683 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2685 /* disable via cardbus interface */
2690 /* disable must be done via function #0 */
2691 if (PCI_FUNC(dev->devfn))
2694 pci_read_config_byte(dev, 0xB7, &disable);
2698 pci_read_config_byte(dev, 0x8E, &write_enable);
2699 pci_write_config_byte(dev, 0x8E, 0xAA);
2700 pci_read_config_byte(dev, 0x8D, &write_target);
2701 pci_write_config_byte(dev, 0x8D, 0xB7);
2702 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2703 pci_write_config_byte(dev, 0x8E, write_enable);
2704 pci_write_config_byte(dev, 0x8D, write_target);
2706 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2707 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2709 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2710 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2712 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2714 /* disable via firewire interface */
2718 /* disable must be done via function #0 */
2719 if (PCI_FUNC(dev->devfn))
2722 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2723 * certain types of SD/MMC cards. Lowering the SD base
2724 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2726 * 0x150 - SD2.0 mode enable for changing base clock
2727 * frequency to 50Mhz
2728 * 0xe1 - Base clock frequency
2729 * 0x32 - 50Mhz new clock frequency
2730 * 0xf9 - Key register for 0x150
2731 * 0xfc - key register for 0xe1
2733 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2734 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2735 pci_write_config_byte(dev, 0xf9, 0xfc);
2736 pci_write_config_byte(dev, 0x150, 0x10);
2737 pci_write_config_byte(dev, 0xf9, 0x00);
2738 pci_write_config_byte(dev, 0xfc, 0x01);
2739 pci_write_config_byte(dev, 0xe1, 0x32);
2740 pci_write_config_byte(dev, 0xfc, 0x00);
2742 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2745 pci_read_config_byte(dev, 0xCB, &disable);
2750 pci_read_config_byte(dev, 0xCA, &write_enable);
2751 pci_write_config_byte(dev, 0xCA, 0x57);
2752 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2753 pci_write_config_byte(dev, 0xCA, write_enable);
2755 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2756 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2760 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2762 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2764 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2765 #endif /*CONFIG_MMC_RICOH_MMC*/
2767 #ifdef CONFIG_DMAR_TABLE
2768 #define VTUNCERRMSK_REG 0x1ac
2769 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2771 * This is a quirk for masking vt-d spec defined errors to platform error
2772 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2773 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2774 * on the RAS config settings of the platform) when a vt-d fault happens.
2775 * The resulting SMI caused the system to hang.
2777 * VT-d spec related errors are already handled by the VT-d OS code, so no
2778 * need to report the same error through other channels.
2780 static void vtd_mask_spec_errors(struct pci_dev *dev)
2784 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2785 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2787 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2788 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2791 static void fixup_ti816x_class(struct pci_dev *dev)
2793 /* TI 816x devices do not have class code set when in PCIe boot mode */
2794 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2795 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2797 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2798 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2800 /* Some PCIe devices do not work reliably with the claimed maximum
2801 * payload size supported.
2803 static void fixup_mpss_256(struct pci_dev *dev)
2805 dev->pcie_mpss = 1; /* 256 bytes */
2807 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2808 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2810 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2812 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2814 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2815 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2816 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2817 * until all of the devices are discovered and buses walked, read completion
2818 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2819 * it is possible to hotplug a device with MPS of 256B.
2821 static void quirk_intel_mc_errata(struct pci_dev *dev)
2826 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2829 /* Intel errata specifies bits to change but does not say what they are.
2830 * Keeping them magical until such time as the registers and values can
2833 err = pci_read_config_word(dev, 0x48, &rcc);
2835 dev_err(&dev->dev, "Error attempting to read the read "
2836 "completion coalescing register.\n");
2840 if (!(rcc & (1 << 10)))
2845 err = pci_write_config_word(dev, 0x48, rcc);
2847 dev_err(&dev->dev, "Error attempting to write the read "
2848 "completion coalescing register.\n");
2852 pr_info_once("Read completion coalescing disabled due to hardware "
2853 "errata relating to 256B MPS.\n");
2855 /* Intel 5000 series memory controllers and ports 2-7 */
2856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2870 /* Intel 5100 series memory controllers and ports 2-7 */
2871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2885 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2886 * work around this, query the size it should be configured to by the device and
2887 * modify the resource end to correspond to this new size.
2889 static void quirk_intel_ntb(struct pci_dev *dev)
2894 rc = pci_read_config_byte(dev, 0x00D0, &val);
2898 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2900 rc = pci_read_config_byte(dev, 0x00D1, &val);
2904 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2909 static ktime_t fixup_debug_start(struct pci_dev *dev,
2910 void (*fn)(struct pci_dev *dev))
2912 ktime_t calltime = ktime_set(0, 0);
2914 dev_dbg(&dev->dev, "calling %pF\n", fn);
2915 if (initcall_debug) {
2916 pr_debug("calling %pF @ %i for %s\n",
2917 fn, task_pid_nr(current), dev_name(&dev->dev));
2918 calltime = ktime_get();
2924 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2925 void (*fn)(struct pci_dev *dev))
2927 ktime_t delta, rettime;
2928 unsigned long long duration;
2930 if (initcall_debug) {
2931 rettime = ktime_get();
2932 delta = ktime_sub(rettime, calltime);
2933 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2934 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2935 fn, duration, dev_name(&dev->dev));
2940 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2941 * even though no one is handling them (f.e. i915 driver is never loaded).
2942 * Additionally the interrupt destination is not set up properly
2943 * and the interrupt ends up -somewhere-.
2945 * These spurious interrupts are "sticky" and the kernel disables
2946 * the (shared) interrupt line after 100.000+ generated interrupts.
2948 * Fix it by disabling the still enabled interrupts.
2949 * This resolves crashes often seen on monitor unplug.
2951 #define I915_DEIER_REG 0x4400c
2952 static void disable_igfx_irq(struct pci_dev *dev)
2954 void __iomem *regs = pci_iomap(dev, 0, 0);
2956 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2960 /* Check if any interrupt line is still enabled */
2961 if (readl(regs + I915_DEIER_REG) != 0) {
2962 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2965 writel(0, regs + I915_DEIER_REG);
2968 pci_iounmap(dev, regs);
2970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
2975 * PCI devices which are on Intel chips can skip the 10ms delay
2976 * before entering D3 mode.
2978 static void quirk_remove_d3_delay(struct pci_dev *dev)
2982 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
2983 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
2984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
2985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
2986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
2987 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
2988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
2989 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
2990 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
2991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
2992 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
2993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
2994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
2995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
2998 * Some devices may pass our check in pci_intx_mask_supported if
2999 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3000 * support this feature.
3002 static void quirk_broken_intx_masking(struct pci_dev *dev)
3004 dev->broken_intx_masking = 1;
3006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3007 quirk_broken_intx_masking);
3008 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3009 quirk_broken_intx_masking);
3011 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3012 struct pci_fixup *end)
3016 for (; f < end; f++)
3017 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3018 f->class == (u32) PCI_ANY_ID) &&
3019 (f->vendor == dev->vendor ||
3020 f->vendor == (u16) PCI_ANY_ID) &&
3021 (f->device == dev->device ||
3022 f->device == (u16) PCI_ANY_ID)) {
3023 calltime = fixup_debug_start(dev, f->hook);
3025 fixup_debug_report(dev, calltime, f->hook);
3029 extern struct pci_fixup __start_pci_fixups_early[];
3030 extern struct pci_fixup __end_pci_fixups_early[];
3031 extern struct pci_fixup __start_pci_fixups_header[];
3032 extern struct pci_fixup __end_pci_fixups_header[];
3033 extern struct pci_fixup __start_pci_fixups_final[];
3034 extern struct pci_fixup __end_pci_fixups_final[];
3035 extern struct pci_fixup __start_pci_fixups_enable[];
3036 extern struct pci_fixup __end_pci_fixups_enable[];
3037 extern struct pci_fixup __start_pci_fixups_resume[];
3038 extern struct pci_fixup __end_pci_fixups_resume[];
3039 extern struct pci_fixup __start_pci_fixups_resume_early[];
3040 extern struct pci_fixup __end_pci_fixups_resume_early[];
3041 extern struct pci_fixup __start_pci_fixups_suspend[];
3042 extern struct pci_fixup __end_pci_fixups_suspend[];
3044 static bool pci_apply_fixup_final_quirks;
3046 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3048 struct pci_fixup *start, *end;
3051 case pci_fixup_early:
3052 start = __start_pci_fixups_early;
3053 end = __end_pci_fixups_early;
3056 case pci_fixup_header:
3057 start = __start_pci_fixups_header;
3058 end = __end_pci_fixups_header;
3061 case pci_fixup_final:
3062 if (!pci_apply_fixup_final_quirks)
3064 start = __start_pci_fixups_final;
3065 end = __end_pci_fixups_final;
3068 case pci_fixup_enable:
3069 start = __start_pci_fixups_enable;
3070 end = __end_pci_fixups_enable;
3073 case pci_fixup_resume:
3074 start = __start_pci_fixups_resume;
3075 end = __end_pci_fixups_resume;
3078 case pci_fixup_resume_early:
3079 start = __start_pci_fixups_resume_early;
3080 end = __end_pci_fixups_resume_early;
3083 case pci_fixup_suspend:
3084 start = __start_pci_fixups_suspend;
3085 end = __end_pci_fixups_suspend;
3089 /* stupid compiler warning, you would think with an enum... */
3092 pci_do_fixups(dev, start, end);
3094 EXPORT_SYMBOL(pci_fixup_device);
3097 static int __init pci_apply_final_quirks(void)
3099 struct pci_dev *dev = NULL;
3103 if (pci_cache_line_size)
3104 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3105 pci_cache_line_size << 2);
3107 pci_apply_fixup_final_quirks = true;
3108 for_each_pci_dev(dev) {
3109 pci_fixup_device(pci_fixup_final, dev);
3111 * If arch hasn't set it explicitly yet, use the CLS
3112 * value shared by all PCI devices. If there's a
3113 * mismatch, fall back to the default value.
3115 if (!pci_cache_line_size) {
3116 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3119 if (!tmp || cls == tmp)
3122 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3123 "using %u bytes\n", cls << 2, tmp << 2,
3124 pci_dfl_cache_line_size << 2);
3125 pci_cache_line_size = pci_dfl_cache_line_size;
3129 if (!pci_cache_line_size) {
3130 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3131 cls << 2, pci_dfl_cache_line_size << 2);
3132 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3138 fs_initcall_sync(pci_apply_final_quirks);
3141 * Followings are device-specific reset methods which can be used to
3142 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3145 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3149 /* only implement PCI_CLASS_SERIAL_USB at present */
3150 if (dev->class == PCI_CLASS_SERIAL_USB) {
3151 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3158 pci_write_config_byte(dev, pos + 0x4, 1);
3167 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3170 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3172 * The 82599 supports FLR on VFs, but FLR support is reported only
3173 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3174 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3180 if (!pci_wait_for_pending_transaction(dev))
3181 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3183 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3190 #include "../gpu/drm/i915/i915_reg.h"
3191 #define MSG_CTL 0x45010
3192 #define NSDE_PWR_STATE 0xd0100
3193 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3195 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3197 void __iomem *mmio_base;
3198 unsigned long timeout;
3204 mmio_base = pci_iomap(dev, 0, 0);
3208 iowrite32(0x00000002, mmio_base + MSG_CTL);
3211 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3212 * driver loaded sets the right bits. However, this's a reset and
3213 * the bits have been set by i915 previously, so we clobber
3214 * SOUTH_CHICKEN2 register directly here.
3216 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3218 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3219 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3221 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3223 val = ioread32(mmio_base + PCH_PP_STATUS);
3224 if ((val & 0xb0000000) == 0)
3225 goto reset_complete;
3227 } while (time_before(jiffies, timeout));
3228 dev_warn(&dev->dev, "timeout during reset\n");
3231 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3233 pci_iounmap(dev, mmio_base);
3238 * Device-specific reset method for Chelsio T4-based adapters.
3240 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3246 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3247 * that we have no device-specific reset method.
3249 if ((dev->device & 0xf000) != 0x4000)
3253 * If this is the "probe" phase, return 0 indicating that we can
3254 * reset this device.
3260 * T4 can wedge if there are DMAs in flight within the chip and Bus
3261 * Master has been disabled. We need to have it on till the Function
3262 * Level Reset completes. (BUS_MASTER is disabled in
3263 * pci_reset_function()).
3265 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3266 pci_write_config_word(dev, PCI_COMMAND,
3267 old_command | PCI_COMMAND_MASTER);
3270 * Perform the actual device function reset, saving and restoring
3271 * configuration information around the reset.
3273 pci_save_state(dev);
3276 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3277 * are disabled when an MSI-X interrupt message needs to be delivered.
3278 * So we briefly re-enable MSI-X interrupts for the duration of the
3279 * FLR. The pci_restore_state() below will restore the original
3282 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3283 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3284 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3286 PCI_MSIX_FLAGS_ENABLE |
3287 PCI_MSIX_FLAGS_MASKALL);
3290 * Start of pcie_flr() code sequence. This reset code is a copy of
3291 * the guts of pcie_flr() because that's not an exported function.
3294 if (!pci_wait_for_pending_transaction(dev))
3295 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3297 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3301 * End of pcie_flr() code sequence.
3305 * Restore the configuration information (BAR values, etc.) including
3306 * the original PCI Configuration Space Command word, and return
3309 pci_restore_state(dev);
3310 pci_write_config_word(dev, PCI_COMMAND, old_command);
3314 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3315 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3316 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3318 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3319 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3320 reset_intel_82599_sfp_virtfn },
3321 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3323 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3325 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3326 reset_intel_generic_dev },
3327 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3328 reset_chelsio_generic_dev },
3333 * These device-specific reset methods are here rather than in a driver
3334 * because when a host assigns a device to a guest VM, the host may need
3335 * to reset the device but probably doesn't have a driver for it.
3337 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3339 const struct pci_dev_reset_methods *i;
3341 for (i = pci_dev_reset_methods; i->reset; i++) {
3342 if ((i->vendor == dev->vendor ||
3343 i->vendor == (u16)PCI_ANY_ID) &&
3344 (i->device == dev->device ||
3345 i->device == (u16)PCI_ANY_ID))
3346 return i->reset(dev, probe);
3352 static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3354 if (!PCI_FUNC(dev->devfn))
3355 return pci_dev_get(dev);
3357 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3360 static const struct pci_dev_dma_source {
3363 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3364 } pci_dev_dma_source[] = {
3366 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3368 * Some Ricoh devices use the function 0 source ID for DMA on
3369 * other functions of a multifunction device. The DMA devices
3370 * is therefore function 0, which will have implications of the
3371 * iommu grouping of these devices.
3373 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3374 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3375 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3376 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3381 * IOMMUs with isolation capabilities need to be programmed with the
3382 * correct source ID of a device. In most cases, the source ID matches
3383 * the device doing the DMA, but sometimes hardware is broken and will
3384 * tag the DMA as being sourced from a different device. This function
3385 * allows that translation. Note that the reference count of the
3386 * returned device is incremented on all paths.
3388 struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3390 const struct pci_dev_dma_source *i;
3392 for (i = pci_dev_dma_source; i->dma_source; i++) {
3393 if ((i->vendor == dev->vendor ||
3394 i->vendor == (u16)PCI_ANY_ID) &&
3395 (i->device == dev->device ||
3396 i->device == (u16)PCI_ANY_ID))
3397 return i->dma_source(dev);
3400 return pci_dev_get(dev);
3404 * AMD has indicated that the devices below do not support peer-to-peer
3405 * in any system where they are found in the southbridge with an AMD
3406 * IOMMU in the system. Multifunction devices that do not support
3407 * peer-to-peer between functions can claim to support a subset of ACS.
3408 * Such devices effectively enable request redirect (RR) and completion
3409 * redirect (CR) since all transactions are redirected to the upstream
3412 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3413 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3414 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3416 * 1002:4385 SBx00 SMBus Controller
3417 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3418 * 1002:4383 SBx00 Azalia (Intel HDA)
3419 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3420 * 1002:4384 SBx00 PCI to PCI Bridge
3421 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3423 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3426 struct acpi_table_header *header = NULL;
3429 /* Targeting multifunction devices on the SB (appears on root bus) */
3430 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3433 /* The IVRS table describes the AMD IOMMU */
3434 status = acpi_get_table("IVRS", 0, &header);
3435 if (ACPI_FAILURE(status))
3438 /* Filter out flags not applicable to multifunction */
3439 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3441 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3447 static const struct pci_dev_acs_enabled {
3450 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3451 } pci_dev_acs_enabled[] = {
3452 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3453 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3454 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3455 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3456 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3457 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3461 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3463 const struct pci_dev_acs_enabled *i;
3467 * Allow devices that do not expose standard PCIe ACS capabilities
3468 * or control to indicate their support here. Multi-function express
3469 * devices which do not allow internal peer-to-peer between functions,
3470 * but do not implement PCIe ACS may wish to return true here.
3472 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3473 if ((i->vendor == dev->vendor ||
3474 i->vendor == (u16)PCI_ANY_ID) &&
3475 (i->device == dev->device ||
3476 i->device == (u16)PCI_ANY_ID)) {
3477 ret = i->acs_enabled(dev, acs_flags);