1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/ktime.h>
27 #include <linux/nvme.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/switchtec.h>
31 #include <asm/dma.h> /* isa_dma_bridge_buggy */
34 static ktime_t fixup_debug_start(struct pci_dev *dev,
35 void (*fn)(struct pci_dev *dev))
38 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
43 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
44 void (*fn)(struct pci_dev *dev))
46 ktime_t delta, rettime;
47 unsigned long long duration;
49 rettime = ktime_get();
50 delta = ktime_sub(rettime, calltime);
51 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
52 if (initcall_debug || duration > 10000)
53 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
56 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
57 struct pci_fixup *end)
62 if ((f->class == (u32) (dev->class >> f->class_shift) ||
63 f->class == (u32) PCI_ANY_ID) &&
64 (f->vendor == dev->vendor ||
65 f->vendor == (u16) PCI_ANY_ID) &&
66 (f->device == dev->device ||
67 f->device == (u16) PCI_ANY_ID)) {
68 void (*hook)(struct pci_dev *dev);
69 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
70 hook = offset_to_ptr(&f->hook_offset);
74 calltime = fixup_debug_start(dev, hook);
76 fixup_debug_report(dev, calltime, hook);
80 extern struct pci_fixup __start_pci_fixups_early[];
81 extern struct pci_fixup __end_pci_fixups_early[];
82 extern struct pci_fixup __start_pci_fixups_header[];
83 extern struct pci_fixup __end_pci_fixups_header[];
84 extern struct pci_fixup __start_pci_fixups_final[];
85 extern struct pci_fixup __end_pci_fixups_final[];
86 extern struct pci_fixup __start_pci_fixups_enable[];
87 extern struct pci_fixup __end_pci_fixups_enable[];
88 extern struct pci_fixup __start_pci_fixups_resume[];
89 extern struct pci_fixup __end_pci_fixups_resume[];
90 extern struct pci_fixup __start_pci_fixups_resume_early[];
91 extern struct pci_fixup __end_pci_fixups_resume_early[];
92 extern struct pci_fixup __start_pci_fixups_suspend[];
93 extern struct pci_fixup __end_pci_fixups_suspend[];
94 extern struct pci_fixup __start_pci_fixups_suspend_late[];
95 extern struct pci_fixup __end_pci_fixups_suspend_late[];
97 static bool pci_apply_fixup_final_quirks;
99 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
101 struct pci_fixup *start, *end;
104 case pci_fixup_early:
105 start = __start_pci_fixups_early;
106 end = __end_pci_fixups_early;
109 case pci_fixup_header:
110 start = __start_pci_fixups_header;
111 end = __end_pci_fixups_header;
114 case pci_fixup_final:
115 if (!pci_apply_fixup_final_quirks)
117 start = __start_pci_fixups_final;
118 end = __end_pci_fixups_final;
121 case pci_fixup_enable:
122 start = __start_pci_fixups_enable;
123 end = __end_pci_fixups_enable;
126 case pci_fixup_resume:
127 start = __start_pci_fixups_resume;
128 end = __end_pci_fixups_resume;
131 case pci_fixup_resume_early:
132 start = __start_pci_fixups_resume_early;
133 end = __end_pci_fixups_resume_early;
136 case pci_fixup_suspend:
137 start = __start_pci_fixups_suspend;
138 end = __end_pci_fixups_suspend;
141 case pci_fixup_suspend_late:
142 start = __start_pci_fixups_suspend_late;
143 end = __end_pci_fixups_suspend_late;
147 /* stupid compiler warning, you would think with an enum... */
150 pci_do_fixups(dev, start, end);
152 EXPORT_SYMBOL(pci_fixup_device);
154 static int __init pci_apply_final_quirks(void)
156 struct pci_dev *dev = NULL;
160 if (pci_cache_line_size)
161 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
163 pci_apply_fixup_final_quirks = true;
164 for_each_pci_dev(dev) {
165 pci_fixup_device(pci_fixup_final, dev);
167 * If arch hasn't set it explicitly yet, use the CLS
168 * value shared by all PCI devices. If there's a
169 * mismatch, fall back to the default value.
171 if (!pci_cache_line_size) {
172 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
175 if (!tmp || cls == tmp)
178 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
180 pci_dfl_cache_line_size << 2);
181 pci_cache_line_size = pci_dfl_cache_line_size;
185 if (!pci_cache_line_size) {
186 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
187 pci_dfl_cache_line_size << 2);
188 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
193 fs_initcall_sync(pci_apply_final_quirks);
196 * Decoding should be disabled for a PCI device during BAR sizing to avoid
197 * conflict. But doing so may cause problems on host bridge and perhaps other
198 * key system devices. For devices that need to have mmio decoding always-on,
199 * we need to set the dev->mmio_always_on bit.
201 static void quirk_mmio_always_on(struct pci_dev *dev)
203 dev->mmio_always_on = 1;
205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
206 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
209 * The Mellanox Tavor device gives false positive parity errors. Mark this
210 * device with a broken_parity_status to allow PCI scanning code to "skip"
211 * this now blacklisted device.
213 static void quirk_mellanox_tavor(struct pci_dev *dev)
215 dev->broken_parity_status = 1; /* This device gives false positives */
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
221 * Deal with broken BIOSes that neglect to enable passive release,
222 * which can cause problems in combination with the 82441FX/PPro MTRRs
224 static void quirk_passive_release(struct pci_dev *dev)
226 struct pci_dev *d = NULL;
230 * We have to make sure a particular bit is set in the PIIX3
231 * ISA bridge, so we have to go out and find it.
233 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
234 pci_read_config_byte(d, 0x82, &dlc);
236 pci_info(d, "PIIX3: Enabling Passive Release\n");
238 pci_write_config_byte(d, 0x82, dlc);
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
243 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
246 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
247 * workaround but VIA don't answer queries. If you happen to have good
248 * contacts at VIA ask them for me please -- Alan
250 * This appears to be BIOS not version dependent. So presumably there is a
253 static void quirk_isa_dma_hangs(struct pci_dev *dev)
255 if (!isa_dma_bridge_buggy) {
256 isa_dma_bridge_buggy = 1;
257 pci_info(dev, "Activating ISA DMA hang workarounds\n");
261 * It's not totally clear which chipsets are the problematic ones. We know
262 * 82C586 and 82C596 variants are affected.
264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
273 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
274 * for some HT machines to use C4 w/o hanging.
276 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
281 pci_read_config_dword(dev, 0x40, &pmbase);
282 pmbase = pmbase & 0xff80;
286 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
292 /* Chipsets where PCI->PCI transfers vanish or hang */
293 static void quirk_nopcipci(struct pci_dev *dev)
295 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
296 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
297 pci_pci_problems |= PCIPCI_FAIL;
300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
303 static void quirk_nopciamd(struct pci_dev *dev)
306 pci_read_config_byte(dev, 0x08, &rev);
309 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
310 pci_pci_problems |= PCIAGP_FAIL;
313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
315 /* Triton requires workarounds to be used by the drivers */
316 static void quirk_triton(struct pci_dev *dev)
318 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
319 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems |= PCIPCI_TRITON;
323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
329 * VIA Apollo KT133 needs PCI latency patch
330 * Made according to a Windows driver-based patch by George E. Breese;
331 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
332 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
333 * which Mr Breese based his work.
335 * Updated based on further information from the site and also on
336 * information provided by VIA
338 static void quirk_vialatency(struct pci_dev *dev)
344 * Ok, we have a potential problem chipset here. Now see if we have
345 * a buggy southbridge.
347 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
351 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
353 * Check for buggy part revisions
355 if (p->revision < 0x40 || p->revision > 0x42)
358 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
359 if (p == NULL) /* No problem parts */
362 /* Check for buggy part revisions */
363 if (p->revision < 0x10 || p->revision > 0x12)
368 * Ok we have the problem. Now set the PCI master grant to occur
369 * every master grant. The apparent bug is that under high PCI load
370 * (quite common in Linux of course) you can get data loss when the
371 * CPU is held off the bus for 3 bus master requests. This happens
372 * to include the IDE controllers....
374 * VIA only apply this fix when an SB Live! is present but under
375 * both Linux and Windows this isn't enough, and we have seen
376 * corruption without SB Live! but with things like 3 UDMA IDE
377 * controllers. So we ignore that bit of the VIA recommendation..
379 pci_read_config_byte(dev, 0x76, &busarb);
382 * Set bit 4 and bit 5 of byte 76 to 0x01
383 * "Master priority rotation on every PCI master grant"
387 pci_write_config_byte(dev, 0x76, busarb);
388 pci_info(dev, "Applying VIA southbridge workaround\n");
392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395 /* Must restore this on a resume from RAM */
396 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
397 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
400 /* VIA Apollo VP3 needs ETBF on BT848/878 */
401 static void quirk_viaetbf(struct pci_dev *dev)
403 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
404 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
405 pci_pci_problems |= PCIPCI_VIAETBF;
408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
410 static void quirk_vsfx(struct pci_dev *dev)
412 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
413 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
414 pci_pci_problems |= PCIPCI_VSFX;
417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
420 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
421 * space. Latency must be set to 0xA and Triton workaround applied too.
422 * [Info kindly provided by ALi]
424 static void quirk_alimagik(struct pci_dev *dev)
426 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
427 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
428 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
434 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
435 static void quirk_natoma(struct pci_dev *dev)
437 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
438 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
439 pci_pci_problems |= PCIPCI_NATOMA;
442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
450 * This chip can cause PCI parity errors if config register 0xA0 is read
451 * while DMAs are occurring.
453 static void quirk_citrine(struct pci_dev *dev)
455 dev->cfg_size = 0xA0;
457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
460 * This chip can cause bus lockups if config addresses above 0x600
461 * are read or written.
463 static void quirk_nfp6000(struct pci_dev *dev)
465 dev->cfg_size = 0x600;
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
472 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
473 static void quirk_extend_bar_to_page(struct pci_dev *dev)
477 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
478 struct resource *r = &dev->resource[i];
480 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
481 r->end = PAGE_SIZE - 1;
483 r->flags |= IORESOURCE_UNSET;
484 pci_info(dev, "expanded BAR %d to page size: %pR\n",
489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
492 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
493 * If it's needed, re-allocate the region.
495 static void quirk_s3_64M(struct pci_dev *dev)
497 struct resource *r = &dev->resource[0];
499 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
500 r->flags |= IORESOURCE_UNSET;
505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
508 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
512 struct pci_bus_region bus_region;
513 struct resource *res = dev->resource + pos;
515 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
520 res->name = pci_name(dev);
521 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
523 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
524 region &= ~(size - 1);
526 /* Convert from PCI bus to resource space */
527 bus_region.start = region;
528 bus_region.end = region + size - 1;
529 pcibios_bus_to_resource(dev->bus, res, &bus_region);
531 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
532 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
536 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
537 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
538 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
539 * (which conflicts w/ BAR1's memory range).
541 * CS553x's ISA PCI BARs may also be read-only (ref:
542 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
544 static void quirk_cs5536_vsa(struct pci_dev *dev)
546 static char *name = "CS5536 ISA bridge";
548 if (pci_resource_len(dev, 0) != 8) {
549 quirk_io(dev, 0, 8, name); /* SMB */
550 quirk_io(dev, 1, 256, name); /* GPIO */
551 quirk_io(dev, 2, 64, name); /* MFGPT */
552 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
558 static void quirk_io_region(struct pci_dev *dev, int port,
559 unsigned size, int nr, const char *name)
562 struct pci_bus_region bus_region;
563 struct resource *res = dev->resource + nr;
565 pci_read_config_word(dev, port, ®ion);
566 region &= ~(size - 1);
571 res->name = pci_name(dev);
572 res->flags = IORESOURCE_IO;
574 /* Convert from PCI bus to resource space */
575 bus_region.start = region;
576 bus_region.end = region + size - 1;
577 pcibios_bus_to_resource(dev->bus, res, &bus_region);
579 if (!pci_claim_resource(dev, nr))
580 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
584 * ATI Northbridge setups MCE the processor if you even read somewhere
585 * between 0x3b0->0x3bb or read 0x3d3
587 static void quirk_ati_exploding_mce(struct pci_dev *dev)
589 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
590 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
591 request_region(0x3b0, 0x0C, "RadeonIGP");
592 request_region(0x3d3, 0x01, "RadeonIGP");
594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
597 * In the AMD NL platform, this device ([1022:7912]) has a class code of
598 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
601 * But the dwc3 driver is a more specific driver for this device, and we'd
602 * prefer to use it instead of xhci. To prevent xhci from claiming the
603 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
604 * defines as "USB device (not host controller)". The dwc3 driver can then
605 * claim it based on its Vendor and Device ID.
607 static void quirk_amd_nl_class(struct pci_dev *pdev)
609 u32 class = pdev->class;
611 /* Use "USB Device (not host controller)" class */
612 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
613 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
620 * Synopsys USB 3.x host HAPS platform has a class code of
621 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
622 * devices should use dwc3-haps driver. Change these devices' class code to
623 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
626 static void quirk_synopsys_haps(struct pci_dev *pdev)
628 u32 class = pdev->class;
630 switch (pdev->device) {
631 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
632 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
633 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
634 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
635 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
640 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
641 PCI_CLASS_SERIAL_USB_XHCI, 0,
642 quirk_synopsys_haps);
645 * Let's make the southbridge information explicit instead of having to
646 * worry about people probing the ACPI areas, for example.. (Yes, it
647 * happens, and if you read the wrong ACPI register it will put the machine
648 * to sleep with no way of waking it up again. Bummer).
650 * ALI M7101: Two IO regions pointed to by words at
651 * 0xE0 (64 bytes of ACPI registers)
652 * 0xE2 (32 bytes of SMB registers)
654 static void quirk_ali7101_acpi(struct pci_dev *dev)
656 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
657 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
661 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
664 u32 mask, size, base;
666 pci_read_config_dword(dev, port, &devres);
667 if ((devres & enable) != enable)
669 mask = (devres >> 16) & 15;
670 base = devres & 0xffff;
673 unsigned bit = size >> 1;
674 if ((bit & mask) == bit)
679 * For now we only print it out. Eventually we'll want to
680 * reserve it (at least if it's in the 0x1000+ range), but
681 * let's get enough confirmation reports first.
684 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
687 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
690 u32 mask, size, base;
692 pci_read_config_dword(dev, port, &devres);
693 if ((devres & enable) != enable)
695 base = devres & 0xffff0000;
696 mask = (devres & 0x3f) << 16;
699 unsigned bit = size >> 1;
700 if ((bit & mask) == bit)
706 * For now we only print it out. Eventually we'll want to
707 * reserve it, but let's get enough confirmation reports first.
710 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
714 * PIIX4 ACPI: Two IO regions pointed to by longwords at
715 * 0x40 (64 bytes of ACPI registers)
716 * 0x90 (16 bytes of SMB registers)
717 * and a few strange programmable PIIX4 device resources.
719 static void quirk_piix4_acpi(struct pci_dev *dev)
723 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
724 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
726 /* Device resource A has enables for some of the other ones */
727 pci_read_config_dword(dev, 0x5c, &res_a);
729 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
730 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
732 /* Device resource D is just bitfields for static resources */
734 /* Device 12 enabled? */
735 if (res_a & (1 << 29)) {
736 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
737 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
739 /* Device 13 enabled? */
740 if (res_a & (1 << 30)) {
741 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
742 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
744 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
745 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
750 #define ICH_PMBASE 0x40
751 #define ICH_ACPI_CNTL 0x44
752 #define ICH4_ACPI_EN 0x10
753 #define ICH6_ACPI_EN 0x80
754 #define ICH4_GPIOBASE 0x58
755 #define ICH4_GPIO_CNTL 0x5c
756 #define ICH4_GPIO_EN 0x10
757 #define ICH6_GPIOBASE 0x48
758 #define ICH6_GPIO_CNTL 0x4c
759 #define ICH6_GPIO_EN 0x10
762 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
763 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
764 * 0x58 (64 bytes of GPIO I/O space)
766 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
771 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
772 * with low legacy (and fixed) ports. We don't know the decoding
773 * priority and can't tell whether the legacy device or the one created
774 * here is really at that address. This happens on boards with broken
777 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
778 if (enable & ICH4_ACPI_EN)
779 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
780 "ICH4 ACPI/GPIO/TCO");
782 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
783 if (enable & ICH4_GPIO_EN)
784 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
798 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
802 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
803 if (enable & ICH6_ACPI_EN)
804 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
805 "ICH6 ACPI/GPIO/TCO");
807 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
808 if (enable & ICH6_GPIO_EN)
809 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
813 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
814 const char *name, int dynsize)
819 pci_read_config_dword(dev, reg, &val);
827 * This is not correct. It is 16, 32 or 64 bytes depending on
828 * register D31:F0:ADh bits 5:4.
830 * But this gets us at least _part_ of it.
839 * Just print it out for now. We should reserve it after more
842 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
845 static void quirk_ich6_lpc(struct pci_dev *dev)
847 /* Shared ACPI/GPIO decode with all ICH6+ */
848 ich6_lpc_acpi_gpio(dev);
850 /* ICH6-specific generic IO decode */
851 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
852 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
857 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
863 pci_read_config_dword(dev, reg, &val);
869 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
871 mask = (val >> 16) & 0xfc;
875 * Just print it out for now. We should reserve it after more
878 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
881 /* ICH7-10 has the same common LPC generic IO decode registers */
882 static void quirk_ich7_lpc(struct pci_dev *dev)
884 /* We share the common ACPI/GPIO decode with ICH6 */
885 ich6_lpc_acpi_gpio(dev);
887 /* And have 4 ICH7+ generic decodes */
888 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
889 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
890 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
891 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
908 * VIA ACPI: One IO region pointed to by longword at
909 * 0x48 or 0x20 (256 bytes of ACPI registers)
911 static void quirk_vt82c586_acpi(struct pci_dev *dev)
913 if (dev->revision & 0x10)
914 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
920 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
921 * 0x48 (256 bytes of ACPI registers)
922 * 0x70 (128 bytes of hardware monitoring register)
923 * 0x90 (16 bytes of SMB registers)
925 static void quirk_vt82c686_acpi(struct pci_dev *dev)
927 quirk_vt82c586_acpi(dev);
929 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
932 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
937 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
938 * 0x88 (128 bytes of power management registers)
939 * 0xd0 (16 bytes of SMB registers)
941 static void quirk_vt8235_acpi(struct pci_dev *dev)
943 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
944 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
949 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
950 * back-to-back: Disable fast back-to-back on the secondary bus segment
952 static void quirk_xio2000a(struct pci_dev *dev)
954 struct pci_dev *pdev;
957 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
958 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
959 pci_read_config_word(pdev, PCI_COMMAND, &command);
960 if (command & PCI_COMMAND_FAST_BACK)
961 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
967 #ifdef CONFIG_X86_IO_APIC
969 #include <asm/io_apic.h>
972 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
973 * devices to the external APIC.
975 * TODO: When we have device-specific interrupt routers, this code will go
978 static void quirk_via_ioapic(struct pci_dev *dev)
983 tmp = 0; /* nothing routed to external APIC */
985 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
987 pci_info(dev, "%sbling VIA external APIC routing\n",
988 tmp == 0 ? "Disa" : "Ena");
990 /* Offset 0x58: External APIC IRQ output control */
991 pci_write_config_byte(dev, 0x58, tmp);
993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
994 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
997 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
998 * This leads to doubled level interrupt rates.
999 * Set this bit to get rid of cycle wastage.
1000 * Otherwise uncritical.
1002 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1005 #define BYPASS_APIC_DEASSERT 8
1007 pci_read_config_byte(dev, 0x5B, &misc_control2);
1008 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1009 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1010 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1014 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1017 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1018 * We check all revs >= B0 (yet not in the pre production!) as the bug
1019 * is currently marked NoFix
1021 * We have multiple reports of hangs with this chipset that went away with
1022 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1023 * of course. However the advice is demonstrably good even if so.
1025 static void quirk_amd_ioapic(struct pci_dev *dev)
1027 if (dev->revision >= 0x02) {
1028 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1029 pci_warn(dev, " : booting with the \"noapic\" option\n");
1032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1033 #endif /* CONFIG_X86_IO_APIC */
1035 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1037 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1039 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1040 if (dev->subsystem_device == 0xa118)
1041 dev->sriov->link = dev->devfn;
1043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1047 * Some settings of MMRBC can lead to data corruption so block changes.
1048 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1050 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1052 if (dev->subordinate && dev->revision <= 0x12) {
1053 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1055 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1061 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1062 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1063 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1064 * of the ACPI SCI interrupt is only done for convenience.
1067 static void quirk_via_acpi(struct pci_dev *d)
1071 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1072 pci_read_config_byte(d, 0x42, &irq);
1074 if (irq && (irq != 2))
1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1080 /* VIA bridges which have VLink */
1081 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1083 static void quirk_via_bridge(struct pci_dev *dev)
1085 /* See what bridge we have and find the device ranges */
1086 switch (dev->device) {
1087 case PCI_DEVICE_ID_VIA_82C686:
1089 * The VT82C686 is special; it attaches to PCI and can have
1090 * any device number. All its subdevices are functions of
1091 * that single device.
1093 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1094 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1096 case PCI_DEVICE_ID_VIA_8237:
1097 case PCI_DEVICE_ID_VIA_8237A:
1098 via_vlink_dev_lo = 15;
1100 case PCI_DEVICE_ID_VIA_8235:
1101 via_vlink_dev_lo = 16;
1103 case PCI_DEVICE_ID_VIA_8231:
1104 case PCI_DEVICE_ID_VIA_8233_0:
1105 case PCI_DEVICE_ID_VIA_8233A:
1106 case PCI_DEVICE_ID_VIA_8233C_0:
1107 via_vlink_dev_lo = 17;
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1121 * quirk_via_vlink - VIA VLink IRQ number update
1124 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1125 * the IRQ line register which usually is not relevant for PCI cards, is
1126 * actually written so that interrupts get sent to the right place.
1128 * We only do this on systems where a VIA south bridge was detected, and
1129 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1131 static void quirk_via_vlink(struct pci_dev *dev)
1135 /* Check if we have VLink at all */
1136 if (via_vlink_dev_lo == -1)
1141 /* Don't quirk interrupts outside the legacy IRQ range */
1142 if (!new_irq || new_irq > 15)
1145 /* Internal device ? */
1146 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1147 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1151 * This is an internal VLink device on a PIC interrupt. The BIOS
1152 * ought to have set this but may not have, so we redo it.
1154 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1155 if (new_irq != irq) {
1156 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1158 udelay(15); /* unknown if delay really needed */
1159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1162 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1165 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1166 * of VT82C597 for backward compatibility. We need to switch it off to be
1167 * able to recognize the real type of the chip.
1169 static void quirk_vt82c598_id(struct pci_dev *dev)
1171 pci_write_config_byte(dev, 0xfc, 0);
1172 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1177 * CardBus controllers have a legacy base address that enables them to
1178 * respond as i82365 pcmcia controllers. We don't want them to do this
1179 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1180 * driver does not (and should not) handle CardBus.
1182 static void quirk_cardbus_legacy(struct pci_dev *dev)
1184 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1186 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1187 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1188 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1189 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1192 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1193 * what the designers were smoking but let's not inhale...
1195 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1198 static void quirk_amd_ordering(struct pci_dev *dev)
1201 pci_read_config_dword(dev, 0x4C, &pcic);
1202 if ((pcic & 6) != 6) {
1204 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1205 pci_write_config_dword(dev, 0x4C, pcic);
1206 pci_read_config_dword(dev, 0x84, &pcic);
1207 pcic |= (1 << 23); /* Required in this mode */
1208 pci_write_config_dword(dev, 0x84, pcic);
1211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1215 * DreamWorks-provided workaround for Dunord I-3000 problem
1217 * This card decodes and responds to addresses not apparently assigned to
1218 * it. We force a larger allocation to ensure that nothing gets put too
1221 static void quirk_dunord(struct pci_dev *dev)
1223 struct resource *r = &dev->resource[1];
1225 r->flags |= IORESOURCE_UNSET;
1229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1232 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1233 * decoding (transparent), and does indicate this in the ProgIf.
1234 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1236 static void quirk_transparent_bridge(struct pci_dev *dev)
1238 dev->transparent = 1;
1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1244 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1245 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1246 * found at http://www.national.com/analog for info on what these bits do.
1247 * <christer@weinigel.se>
1249 static void quirk_mediagx_master(struct pci_dev *dev)
1253 pci_read_config_byte(dev, 0x41, ®);
1256 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1258 pci_write_config_byte(dev, 0x41, reg);
1261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1265 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1266 * in the odd case it is not the results are corruption hence the presence
1269 static void quirk_disable_pxb(struct pci_dev *pdev)
1273 if (pdev->revision != 0x04) /* Only C0 requires this */
1275 pci_read_config_word(pdev, 0x40, &config);
1276 if (config & (1<<6)) {
1278 pci_write_config_word(pdev, 0x40, config);
1279 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1283 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1285 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1287 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1290 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1292 pci_read_config_byte(pdev, 0x40, &tmp);
1293 pci_write_config_byte(pdev, 0x40, tmp|1);
1294 pci_write_config_byte(pdev, 0x9, 1);
1295 pci_write_config_byte(pdev, 0xa, 6);
1296 pci_write_config_byte(pdev, 0x40, tmp);
1298 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1299 pci_info(pdev, "set SATA to AHCI mode\n");
1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1311 /* Serverworks CSB5 IDE does not fully support native mode */
1312 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1315 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1319 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1320 /* PCI layer will sort out resources */
1323 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1325 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1326 static void quirk_ide_samemode(struct pci_dev *pdev)
1330 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1332 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1333 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1336 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1341 /* Some ATA devices break if put into D3 */
1342 static void quirk_no_ata_d3(struct pci_dev *pdev)
1344 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1346 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1347 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1348 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1349 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1350 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1351 /* ALi loses some register settings that we cannot then restore */
1352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1353 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1355 occur when mode detecting */
1356 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1357 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1360 * This was originally an Alpha-specific thing, but it really fits here.
1361 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1363 static void quirk_eisa_bridge(struct pci_dev *dev)
1365 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1370 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1371 * is not activated. The myth is that Asus said that they do not want the
1372 * users to be irritated by just another PCI Device in the Win98 device
1373 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1374 * package 2.7.0 for details)
1376 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1377 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1378 * becomes necessary to do this tweak in two steps -- the chosen trigger
1379 * is either the Host bridge (preferred) or on-board VGA controller.
1381 * Note that we used to unhide the SMBus that way on Toshiba laptops
1382 * (Satellite A40 and Tecra M2) but then found that the thermal management
1383 * was done by SMM code, which could cause unsynchronized concurrent
1384 * accesses to the SMBus registers, with potentially bad effects. Thus you
1385 * should be very careful when adding new entries: if SMM is accessing the
1386 * Intel SMBus, this is a very good reason to leave it hidden.
1388 * Likewise, many recent laptops use ACPI for thermal management. If the
1389 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1390 * natively, and keeping the SMBus hidden is the right thing to do. If you
1391 * are about to add an entry in the table below, please first disassemble
1392 * the DSDT and double-check that there is no code accessing the SMBus.
1394 static int asus_hides_smbus;
1396 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1398 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1399 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1400 switch (dev->subsystem_device) {
1401 case 0x8025: /* P4B-LX */
1402 case 0x8070: /* P4B */
1403 case 0x8088: /* P4B533 */
1404 case 0x1626: /* L3C notebook */
1405 asus_hides_smbus = 1;
1407 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1408 switch (dev->subsystem_device) {
1409 case 0x80b1: /* P4GE-V */
1410 case 0x80b2: /* P4PE */
1411 case 0x8093: /* P4B533-V */
1412 asus_hides_smbus = 1;
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1415 switch (dev->subsystem_device) {
1416 case 0x8030: /* P4T533 */
1417 asus_hides_smbus = 1;
1419 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1420 switch (dev->subsystem_device) {
1421 case 0x8070: /* P4G8X Deluxe */
1422 asus_hides_smbus = 1;
1424 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1425 switch (dev->subsystem_device) {
1426 case 0x80c9: /* PU-DLS */
1427 asus_hides_smbus = 1;
1429 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1430 switch (dev->subsystem_device) {
1431 case 0x1751: /* M2N notebook */
1432 case 0x1821: /* M5N notebook */
1433 case 0x1897: /* A6L notebook */
1434 asus_hides_smbus = 1;
1436 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1437 switch (dev->subsystem_device) {
1438 case 0x184b: /* W1N notebook */
1439 case 0x186a: /* M6Ne notebook */
1440 asus_hides_smbus = 1;
1442 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1443 switch (dev->subsystem_device) {
1444 case 0x80f2: /* P4P800-X */
1445 asus_hides_smbus = 1;
1447 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1448 switch (dev->subsystem_device) {
1449 case 0x1882: /* M6V notebook */
1450 case 0x1977: /* A6VA notebook */
1451 asus_hides_smbus = 1;
1453 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1454 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1455 switch (dev->subsystem_device) {
1456 case 0x088C: /* HP Compaq nc8000 */
1457 case 0x0890: /* HP Compaq nc6000 */
1458 asus_hides_smbus = 1;
1460 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1461 switch (dev->subsystem_device) {
1462 case 0x12bc: /* HP D330L */
1463 case 0x12bd: /* HP D530 */
1464 case 0x006a: /* HP Compaq nx9500 */
1465 asus_hides_smbus = 1;
1467 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1468 switch (dev->subsystem_device) {
1469 case 0x12bf: /* HP xw4100 */
1470 asus_hides_smbus = 1;
1472 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1473 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1474 switch (dev->subsystem_device) {
1475 case 0xC00C: /* Samsung P35 notebook */
1476 asus_hides_smbus = 1;
1478 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1479 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1480 switch (dev->subsystem_device) {
1481 case 0x0058: /* Compaq Evo N620c */
1482 asus_hides_smbus = 1;
1484 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1485 switch (dev->subsystem_device) {
1486 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1487 /* Motherboard doesn't have Host bridge
1488 * subvendor/subdevice IDs, therefore checking
1489 * its on-board VGA controller */
1490 asus_hides_smbus = 1;
1492 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1493 switch (dev->subsystem_device) {
1494 case 0x00b8: /* Compaq Evo D510 CMT */
1495 case 0x00b9: /* Compaq Evo D510 SFF */
1496 case 0x00ba: /* Compaq Evo D510 USDT */
1497 /* Motherboard doesn't have Host bridge
1498 * subvendor/subdevice IDs and on-board VGA
1499 * controller is disabled if an AGP card is
1500 * inserted, therefore checking USB UHCI
1502 asus_hides_smbus = 1;
1504 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1505 switch (dev->subsystem_device) {
1506 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1507 /* Motherboard doesn't have host bridge
1508 * subvendor/subdevice IDs, therefore checking
1509 * its on-board VGA controller */
1510 asus_hides_smbus = 1;
1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1529 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1533 if (likely(!asus_hides_smbus))
1536 pci_read_config_word(dev, 0xF2, &val);
1538 pci_write_config_word(dev, 0xF2, val & (~0x8));
1539 pci_read_config_word(dev, 0xF2, &val);
1541 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1544 pci_info(dev, "Enabled i801 SMBus device\n");
1547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1557 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1562 /* It appears we just have one such device. If not, we have a warning */
1563 static void __iomem *asus_rcba_base;
1564 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1568 if (likely(!asus_hides_smbus))
1570 WARN_ON(asus_rcba_base);
1572 pci_read_config_dword(dev, 0xF0, &rcba);
1573 /* use bits 31:14, 16 kB aligned */
1574 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1575 if (asus_rcba_base == NULL)
1579 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1583 if (likely(!asus_hides_smbus || !asus_rcba_base))
1586 /* read the Function Disable register, dword mode only */
1587 val = readl(asus_rcba_base + 0x3418);
1589 /* enable the SMBus device */
1590 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1593 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1595 if (likely(!asus_hides_smbus || !asus_rcba_base))
1598 iounmap(asus_rcba_base);
1599 asus_rcba_base = NULL;
1600 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1603 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1605 asus_hides_smbus_lpc_ich6_suspend(dev);
1606 asus_hides_smbus_lpc_ich6_resume_early(dev);
1607 asus_hides_smbus_lpc_ich6_resume(dev);
1609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1610 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1612 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1614 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1615 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1618 pci_read_config_byte(dev, 0x77, &val);
1620 pci_info(dev, "Enabling SiS 96x SMBus\n");
1621 pci_write_config_byte(dev, 0x77, val & ~0x10);
1624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1628 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1629 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1630 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1631 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1634 * ... This is further complicated by the fact that some SiS96x south
1635 * bridges pretend to be 85C503/5513 instead. In that case see if we
1636 * spotted a compatible north bridge to make sure.
1637 * (pci_find_device() doesn't work yet)
1639 * We can also enable the sis96x bit in the discovery register..
1641 #define SIS_DETECT_REGISTER 0x40
1643 static void quirk_sis_503(struct pci_dev *dev)
1648 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1649 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1650 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1651 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1652 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1657 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1658 * it has already been processed. (Depends on link order, which is
1659 * apparently not guaranteed)
1661 dev->device = devid;
1662 quirk_sis_96x_smbus(dev);
1664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1665 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1668 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1669 * and MC97 modem controller are disabled when a second PCI soundcard is
1670 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1673 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1676 int asus_hides_ac97 = 0;
1678 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1679 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1680 asus_hides_ac97 = 1;
1683 if (!asus_hides_ac97)
1686 pci_read_config_byte(dev, 0x50, &val);
1688 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1689 pci_read_config_byte(dev, 0x50, &val);
1691 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1694 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1700 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1703 * If we are using libata we can drive this chip properly but must do this
1704 * early on to make the additional device appear during the PCI scanning.
1706 static void quirk_jmicron_ata(struct pci_dev *pdev)
1708 u32 conf1, conf5, class;
1711 /* Only poke fn 0 */
1712 if (PCI_FUNC(pdev->devfn))
1715 pci_read_config_dword(pdev, 0x40, &conf1);
1716 pci_read_config_dword(pdev, 0x80, &conf5);
1718 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1719 conf5 &= ~(1 << 24); /* Clear bit 24 */
1721 switch (pdev->device) {
1722 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1723 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1724 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1725 /* The controller should be in single function ahci mode */
1726 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1729 case PCI_DEVICE_ID_JMICRON_JMB365:
1730 case PCI_DEVICE_ID_JMICRON_JMB366:
1731 /* Redirect IDE second PATA port to the right spot */
1734 case PCI_DEVICE_ID_JMICRON_JMB361:
1735 case PCI_DEVICE_ID_JMICRON_JMB363:
1736 case PCI_DEVICE_ID_JMICRON_JMB369:
1737 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1738 /* Set the class codes correctly and then direct IDE 0 */
1739 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1742 case PCI_DEVICE_ID_JMICRON_JMB368:
1743 /* The controller should be in single function IDE mode */
1744 conf1 |= 0x00C00000; /* Set 22, 23 */
1748 pci_write_config_dword(pdev, 0x40, conf1);
1749 pci_write_config_dword(pdev, 0x80, conf5);
1751 /* Update pdev accordingly */
1752 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1753 pdev->hdr_type = hdr & 0x7f;
1754 pdev->multifunction = !!(hdr & 0x80);
1756 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1757 pdev->class = class >> 8;
1759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1764 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1773 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1780 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1782 if (dev->multifunction) {
1783 device_disable_async_suspend(&dev->dev);
1784 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1787 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1788 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1792 #ifdef CONFIG_X86_IO_APIC
1793 static void quirk_alder_ioapic(struct pci_dev *pdev)
1797 if ((pdev->class >> 8) != 0xff00)
1801 * The first BAR is the location of the IO-APIC... we must
1802 * not touch this (and it's already covered by the fixmap), so
1803 * forcibly insert it into the resource tree.
1805 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1806 insert_resource(&iomem_resource, &pdev->resource[0]);
1809 * The next five BARs all seem to be rubbish, so just clean
1812 for (i = 1; i < 6; i++)
1813 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1818 static void quirk_pcie_mch(struct pci_dev *pdev)
1822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1826 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1829 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1830 * together on certain PXH-based systems.
1832 static void quirk_pcie_pxh(struct pci_dev *dev)
1835 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1837 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1838 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1839 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1840 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1841 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1844 * Some Intel PCI Express chipsets have trouble with downstream device
1847 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1849 pci_pm_d3_delay = 120;
1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1874 static void quirk_radeon_pm(struct pci_dev *dev)
1876 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1877 dev->subsystem_device == 0x00e2) {
1878 if (dev->d3_delay < 20) {
1880 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1887 #ifdef CONFIG_X86_IO_APIC
1888 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1890 noioapicreroute = 1;
1891 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1896 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1898 * Systems to exclude from boot interrupt reroute quirks
1901 .callback = dmi_disable_ioapicreroute,
1902 .ident = "ASUSTek Computer INC. M2N-LR",
1904 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1905 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1912 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1913 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1914 * that a PCI device's interrupt handler is installed on the boot interrupt
1917 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1919 dmi_check_system(boot_interrupt_dmi_table);
1920 if (noioapicquirk || noioapicreroute)
1923 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1924 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1925 dev->vendor, dev->device);
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1928 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1934 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1935 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1936 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1937 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1938 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1939 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1940 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1941 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1942 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1945 * On some chipsets we can disable the generation of legacy INTx boot
1950 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1951 * 300641-004US, section 5.7.3.
1953 #define INTEL_6300_IOAPIC_ABAR 0x40
1954 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1956 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1958 u16 pci_config_word;
1963 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1964 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1965 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1967 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1968 dev->vendor, dev->device);
1970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1971 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1973 /* Disable boot interrupts on HT-1000 */
1974 #define BC_HT1000_FEATURE_REG 0x64
1975 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1976 #define BC_HT1000_MAP_IDX 0xC00
1977 #define BC_HT1000_MAP_DATA 0xC01
1979 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1981 u32 pci_config_dword;
1987 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1988 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1989 BC_HT1000_PIC_REGS_ENABLE);
1991 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1992 outb(irq, BC_HT1000_MAP_IDX);
1993 outb(0x00, BC_HT1000_MAP_DATA);
1996 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1998 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1999 dev->vendor, dev->device);
2001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2002 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2004 /* Disable boot interrupts on AMD and ATI chipsets */
2007 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2008 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2009 * (due to an erratum).
2011 #define AMD_813X_MISC 0x40
2012 #define AMD_813X_NOIOAMODE (1<<0)
2013 #define AMD_813X_REV_B1 0x12
2014 #define AMD_813X_REV_B2 0x13
2016 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2018 u32 pci_config_dword;
2022 if ((dev->revision == AMD_813X_REV_B1) ||
2023 (dev->revision == AMD_813X_REV_B2))
2026 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2027 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2028 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2030 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2031 dev->vendor, dev->device);
2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2034 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2036 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2038 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2040 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2042 u16 pci_config_word;
2047 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2048 if (!pci_config_word) {
2049 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2050 dev->vendor, dev->device);
2053 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2054 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2055 dev->vendor, dev->device);
2057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2058 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2059 #endif /* CONFIG_X86_IO_APIC */
2062 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2063 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2064 * Re-allocate the region if needed...
2066 static void quirk_tc86c001_ide(struct pci_dev *dev)
2068 struct resource *r = &dev->resource[0];
2070 if (r->start & 0x8) {
2071 r->flags |= IORESOURCE_UNSET;
2076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2077 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2078 quirk_tc86c001_ide);
2081 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2082 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2083 * being read correctly if bit 7 of the base address is set.
2084 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2085 * Re-allocate the regions to a 256-byte boundary if necessary.
2087 static void quirk_plx_pci9050(struct pci_dev *dev)
2091 /* Fixed in revision 2 (PCI 9052). */
2092 if (dev->revision >= 2)
2094 for (bar = 0; bar <= 1; bar++)
2095 if (pci_resource_len(dev, bar) == 0x80 &&
2096 (pci_resource_start(dev, bar) & 0x80)) {
2097 struct resource *r = &dev->resource[bar];
2098 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2100 r->flags |= IORESOURCE_UNSET;
2105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2108 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2109 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2110 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2111 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2113 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2116 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2117 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2119 static void quirk_netmos(struct pci_dev *dev)
2121 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2122 unsigned int num_serial = dev->subsystem_device & 0xf;
2125 * These Netmos parts are multiport serial devices with optional
2126 * parallel ports. Even when parallel ports are present, they
2127 * are identified as class SERIAL, which means the serial driver
2128 * will claim them. To prevent this, mark them as class OTHER.
2129 * These combo devices should be claimed by parport_serial.
2131 * The subdevice ID is of the form 0x00PS, where <P> is the number
2132 * of parallel ports and <S> is the number of serial ports.
2134 switch (dev->device) {
2135 case PCI_DEVICE_ID_NETMOS_9835:
2136 /* Well, this rule doesn't hold for the following 9835 device */
2137 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2138 dev->subsystem_device == 0x0299)
2140 /* else, fall through */
2141 case PCI_DEVICE_ID_NETMOS_9735:
2142 case PCI_DEVICE_ID_NETMOS_9745:
2143 case PCI_DEVICE_ID_NETMOS_9845:
2144 case PCI_DEVICE_ID_NETMOS_9855:
2146 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2147 dev->device, num_parallel, num_serial);
2148 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2149 (dev->class & 0xff);
2153 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2154 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2156 static void quirk_e100_interrupt(struct pci_dev *dev)
2162 switch (dev->device) {
2163 /* PCI IDs taken from drivers/net/e100.c */
2165 case 0x1030 ... 0x1034:
2166 case 0x1038 ... 0x103E:
2167 case 0x1050 ... 0x1057:
2169 case 0x1064 ... 0x106B:
2170 case 0x1091 ... 0x1095:
2183 * Some firmware hands off the e100 with interrupts enabled,
2184 * which can cause a flood of interrupts if packets are
2185 * received before the driver attaches to the device. So
2186 * disable all e100 interrupts here. The driver will
2187 * re-enable them when it's ready.
2189 pci_read_config_word(dev, PCI_COMMAND, &command);
2191 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2195 * Check that the device is in the D0 power state. If it's not,
2196 * there is no point to look any further.
2199 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2200 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2204 /* Convert from PCI bus to resource space. */
2205 csr = ioremap(pci_resource_start(dev, 0), 8);
2207 pci_warn(dev, "Can't map e100 registers\n");
2211 cmd_hi = readb(csr + 3);
2213 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2219 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2220 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2223 * The 82575 and 82598 may experience data corruption issues when transitioning
2224 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2226 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2228 pci_info(dev, "Disabling L0s\n");
2229 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2247 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2248 * Link bit cleared after starting the link retrain process to allow this
2249 * process to finish.
2251 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2252 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2254 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2256 dev->clear_retrain_link = 1;
2257 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2259 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2260 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2261 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2263 static void fixup_rev1_53c810(struct pci_dev *dev)
2265 u32 class = dev->class;
2268 * rev 1 ncr53c810 chips don't set the class at all which means
2269 * they don't get their resources remapped. Fix that here.
2274 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2275 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2280 /* Enable 1k I/O space granularity on the Intel P64H2 */
2281 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2285 pci_read_config_word(dev, 0x40, &en1k);
2288 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2289 dev->io_window_1k = 1;
2292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2295 * Under some circumstances, AER is not linked with extended capabilities.
2296 * Force it to be linked by setting the corresponding control bit in the
2299 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2303 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2305 pci_write_config_byte(dev, 0xf41, b | 0x20);
2306 pci_info(dev, "Linking AER extended capability\n");
2310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2311 quirk_nvidia_ck804_pcie_aer_ext_cap);
2312 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2313 quirk_nvidia_ck804_pcie_aer_ext_cap);
2315 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2318 * Disable PCI Bus Parking and PCI Master read caching on CX700
2319 * which causes unspecified timing errors with a VT6212L on the PCI
2320 * bus leading to USB2.0 packet loss.
2322 * This quirk is only enabled if a second (on the external PCI bus)
2323 * VT6212L is found -- the CX700 core itself also contains a USB
2324 * host controller with the same PCI ID as the VT6212L.
2327 /* Count VT6212L instances */
2328 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2329 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2333 * p should contain the first (internal) VT6212L -- see if we have
2334 * an external one by searching again.
2336 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2341 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2343 /* Turn off PCI Bus Parking */
2344 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2346 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2350 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2352 /* Turn off PCI Master read caching */
2353 pci_write_config_byte(dev, 0x72, 0x0);
2355 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2356 pci_write_config_byte(dev, 0x75, 0x1);
2358 /* Disable "Read FIFO Timer" */
2359 pci_write_config_byte(dev, 0x77, 0x0);
2361 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2367 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2371 pci_read_config_dword(dev, 0xf4, &rev);
2373 /* Only CAP the MRRS if the device is a 5719 A0 */
2374 if (rev == 0x05719000) {
2375 int readrq = pcie_get_readrq(dev);
2377 pcie_set_readrq(dev, 2048);
2380 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2381 PCI_DEVICE_ID_TIGON3_5719,
2382 quirk_brcm_5719_limit_mrrs);
2384 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2385 static void quirk_paxc_bridge(struct pci_dev *pdev)
2388 * The PCI config space is shared with the PAXC root port and the first
2389 * Ethernet device. So, we need to workaround this by telling the PCI
2390 * code that the bridge is not an Ethernet device.
2392 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2393 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2396 * MPSS is not being set properly (as it is currently 0). This is
2397 * because that area of the PCI config space is hard coded to zero, and
2398 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2399 * so that the MPS can be set to the real max value.
2401 pdev->pcie_mpss = 2;
2403 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2404 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2405 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
2406 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
2407 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
2411 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2412 * hide device 6 which configures the overflow device access containing the
2413 * DRBs - this is where we expose device 6.
2414 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2416 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2420 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2421 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2422 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2425 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2426 quirk_unhide_mch_dev6);
2427 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2428 quirk_unhide_mch_dev6);
2430 #ifdef CONFIG_PCI_MSI
2432 * Some chipsets do not support MSI. We cannot easily rely on setting
2433 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2434 * other buses controlled by the chipset even if Linux is not aware of it.
2435 * Instead of setting the flag on all buses in the machine, simply disable
2438 static void quirk_disable_all_msi(struct pci_dev *dev)
2441 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2452 /* Disable MSI on chipsets that are known to not support it */
2453 static void quirk_disable_msi(struct pci_dev *dev)
2455 if (dev->subordinate) {
2456 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2457 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2465 * The APC bridge device in AMD 780 family northbridges has some random
2466 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2467 * we use the possible vendor/device IDs of the host bridge for the
2468 * declared quirk, and search for the APC bridge by slot number.
2470 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2472 struct pci_dev *apc_bridge;
2474 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2476 if (apc_bridge->device == 0x9602)
2477 quirk_disable_msi(apc_bridge);
2478 pci_dev_put(apc_bridge);
2481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2485 * Go through the list of HyperTransport capabilities and return 1 if a HT
2486 * MSI capability is found and enabled.
2488 static int msi_ht_cap_enabled(struct pci_dev *dev)
2490 int pos, ttl = PCI_FIND_CAP_TTL;
2492 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2493 while (pos && ttl--) {
2496 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2498 pci_info(dev, "Found %s HT MSI Mapping\n",
2499 flags & HT_MSI_FLAGS_ENABLE ?
2500 "enabled" : "disabled");
2501 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2504 pos = pci_find_next_ht_capability(dev, pos,
2505 HT_CAPTYPE_MSI_MAPPING);
2510 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2511 static void quirk_msi_ht_cap(struct pci_dev *dev)
2513 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2514 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2515 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2522 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2523 * if the MSI capability is set in any of these mappings.
2525 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2527 struct pci_dev *pdev;
2529 if (!dev->subordinate)
2533 * Check HT MSI cap on this chipset and the root one. A single one
2534 * having MSI is enough to be sure that MSI is supported.
2536 pdev = pci_get_slot(dev->bus, 0);
2539 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2540 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2541 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2546 quirk_nvidia_ck804_msi_ht_cap);
2548 /* Force enable MSI mapping capability on HT bridges */
2549 static void ht_enable_msi_mapping(struct pci_dev *dev)
2551 int pos, ttl = PCI_FIND_CAP_TTL;
2553 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2554 while (pos && ttl--) {
2557 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2559 pci_info(dev, "Enabling HT MSI Mapping\n");
2561 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2562 flags | HT_MSI_FLAGS_ENABLE);
2564 pos = pci_find_next_ht_capability(dev, pos,
2565 HT_CAPTYPE_MSI_MAPPING);
2568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2569 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2570 ht_enable_msi_mapping);
2571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2572 ht_enable_msi_mapping);
2575 * The P5N32-SLI motherboards from Asus have a problem with MSI
2576 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2577 * also affects other devices. As for now, turn off MSI for this device.
2579 static void nvenet_msi_disable(struct pci_dev *dev)
2581 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2584 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2585 strstr(board_name, "P5N32-E SLI"))) {
2586 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2590 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2591 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2592 nvenet_msi_disable);
2595 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2596 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2597 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2598 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2599 * for other events, since PCIe specificiation doesn't support using a mix of
2600 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2601 * service drivers registering their respective ISRs for MSIs.
2603 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2607 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2608 PCI_CLASS_BRIDGE_PCI, 8,
2609 pci_quirk_nvidia_tegra_disable_rp_msi);
2610 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2611 PCI_CLASS_BRIDGE_PCI, 8,
2612 pci_quirk_nvidia_tegra_disable_rp_msi);
2613 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2614 PCI_CLASS_BRIDGE_PCI, 8,
2615 pci_quirk_nvidia_tegra_disable_rp_msi);
2616 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2617 PCI_CLASS_BRIDGE_PCI, 8,
2618 pci_quirk_nvidia_tegra_disable_rp_msi);
2619 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2620 PCI_CLASS_BRIDGE_PCI, 8,
2621 pci_quirk_nvidia_tegra_disable_rp_msi);
2622 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2623 PCI_CLASS_BRIDGE_PCI, 8,
2624 pci_quirk_nvidia_tegra_disable_rp_msi);
2625 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2626 PCI_CLASS_BRIDGE_PCI, 8,
2627 pci_quirk_nvidia_tegra_disable_rp_msi);
2628 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2629 PCI_CLASS_BRIDGE_PCI, 8,
2630 pci_quirk_nvidia_tegra_disable_rp_msi);
2631 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2632 PCI_CLASS_BRIDGE_PCI, 8,
2633 pci_quirk_nvidia_tegra_disable_rp_msi);
2634 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2635 PCI_CLASS_BRIDGE_PCI, 8,
2636 pci_quirk_nvidia_tegra_disable_rp_msi);
2637 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2638 PCI_CLASS_BRIDGE_PCI, 8,
2639 pci_quirk_nvidia_tegra_disable_rp_msi);
2640 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2641 PCI_CLASS_BRIDGE_PCI, 8,
2642 pci_quirk_nvidia_tegra_disable_rp_msi);
2643 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2644 PCI_CLASS_BRIDGE_PCI, 8,
2645 pci_quirk_nvidia_tegra_disable_rp_msi);
2648 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2649 * config register. This register controls the routing of legacy
2650 * interrupts from devices that route through the MCP55. If this register
2651 * is misprogrammed, interrupts are only sent to the BSP, unlike
2652 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2653 * having this register set properly prevents kdump from booting up
2654 * properly, so let's make sure that we have it set correctly.
2655 * Note that this is an undocumented register.
2657 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2661 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2664 pci_read_config_dword(dev, 0x74, &cfg);
2666 if (cfg & ((1 << 2) | (1 << 15))) {
2667 pr_info("Rewriting IRQ routing register on MCP55\n");
2668 cfg &= ~((1 << 2) | (1 << 15));
2669 pci_write_config_dword(dev, 0x74, cfg);
2672 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2673 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2674 nvbridge_check_legacy_irq_routing);
2675 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2676 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2677 nvbridge_check_legacy_irq_routing);
2679 static int ht_check_msi_mapping(struct pci_dev *dev)
2681 int pos, ttl = PCI_FIND_CAP_TTL;
2684 /* Check if there is HT MSI cap or enabled on this device */
2685 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2686 while (pos && ttl--) {
2691 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2693 if (flags & HT_MSI_FLAGS_ENABLE) {
2700 pos = pci_find_next_ht_capability(dev, pos,
2701 HT_CAPTYPE_MSI_MAPPING);
2707 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2709 struct pci_dev *dev;
2714 dev_no = host_bridge->devfn >> 3;
2715 for (i = dev_no + 1; i < 0x20; i++) {
2716 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2720 /* found next host bridge? */
2721 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2727 if (ht_check_msi_mapping(dev)) {
2738 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2739 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2741 static int is_end_of_ht_chain(struct pci_dev *dev)
2747 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2752 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2754 ctrl_off = ((flags >> 10) & 1) ?
2755 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2756 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2758 if (ctrl & (1 << 6))
2765 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2767 struct pci_dev *host_bridge;
2772 dev_no = dev->devfn >> 3;
2773 for (i = dev_no; i >= 0; i--) {
2774 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2778 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2783 pci_dev_put(host_bridge);
2789 /* don't enable end_device/host_bridge with leaf directly here */
2790 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2791 host_bridge_with_leaf(host_bridge))
2794 /* root did that ! */
2795 if (msi_ht_cap_enabled(host_bridge))
2798 ht_enable_msi_mapping(dev);
2801 pci_dev_put(host_bridge);
2804 static void ht_disable_msi_mapping(struct pci_dev *dev)
2806 int pos, ttl = PCI_FIND_CAP_TTL;
2808 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2809 while (pos && ttl--) {
2812 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2814 pci_info(dev, "Disabling HT MSI Mapping\n");
2816 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2817 flags & ~HT_MSI_FLAGS_ENABLE);
2819 pos = pci_find_next_ht_capability(dev, pos,
2820 HT_CAPTYPE_MSI_MAPPING);
2824 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2826 struct pci_dev *host_bridge;
2830 if (!pci_msi_enabled())
2833 /* check if there is HT MSI cap or enabled on this device */
2834 found = ht_check_msi_mapping(dev);
2841 * HT MSI mapping should be disabled on devices that are below
2842 * a non-Hypertransport host bridge. Locate the host bridge...
2844 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2846 if (host_bridge == NULL) {
2847 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2851 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2853 /* Host bridge is to HT */
2855 /* it is not enabled, try to enable it */
2857 ht_enable_msi_mapping(dev);
2859 nv_ht_enable_msi_mapping(dev);
2864 /* HT MSI is not enabled */
2868 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2869 ht_disable_msi_mapping(dev);
2872 pci_dev_put(host_bridge);
2875 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2877 return __nv_msi_ht_cap_quirk(dev, 1);
2879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2880 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2882 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2884 return __nv_msi_ht_cap_quirk(dev, 0);
2886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2887 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2889 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2891 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2894 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2899 * SB700 MSI issue will be fixed at HW level from revision A21;
2900 * we need check PCI REVISION ID of SMBus controller to get SB700
2903 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2908 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2909 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2913 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2915 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2916 if (dev->revision < 0x18) {
2917 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2918 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2922 PCI_DEVICE_ID_TIGON3_5780,
2923 quirk_msi_intx_disable_bug);
2924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2925 PCI_DEVICE_ID_TIGON3_5780S,
2926 quirk_msi_intx_disable_bug);
2927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2928 PCI_DEVICE_ID_TIGON3_5714,
2929 quirk_msi_intx_disable_bug);
2930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2931 PCI_DEVICE_ID_TIGON3_5714S,
2932 quirk_msi_intx_disable_bug);
2933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2934 PCI_DEVICE_ID_TIGON3_5715,
2935 quirk_msi_intx_disable_bug);
2936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2937 PCI_DEVICE_ID_TIGON3_5715S,
2938 quirk_msi_intx_disable_bug);
2940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2941 quirk_msi_intx_disable_ati_bug);
2942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2943 quirk_msi_intx_disable_ati_bug);
2944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2945 quirk_msi_intx_disable_ati_bug);
2946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2947 quirk_msi_intx_disable_ati_bug);
2948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2949 quirk_msi_intx_disable_ati_bug);
2951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2952 quirk_msi_intx_disable_bug);
2953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2954 quirk_msi_intx_disable_bug);
2955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2956 quirk_msi_intx_disable_bug);
2958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2959 quirk_msi_intx_disable_bug);
2960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2961 quirk_msi_intx_disable_bug);
2962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2963 quirk_msi_intx_disable_bug);
2964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2965 quirk_msi_intx_disable_bug);
2966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2967 quirk_msi_intx_disable_bug);
2968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2969 quirk_msi_intx_disable_bug);
2970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2971 quirk_msi_intx_disable_qca_bug);
2972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2973 quirk_msi_intx_disable_qca_bug);
2974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2975 quirk_msi_intx_disable_qca_bug);
2976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2977 quirk_msi_intx_disable_qca_bug);
2978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2979 quirk_msi_intx_disable_qca_bug);
2982 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
2983 * should be disabled on platforms where the device (mistakenly) advertises it.
2985 * Notice that this quirk also disables MSI (which may work, but hasn't been
2986 * tested), since currently there is no standard way to disable only MSI-X.
2988 * The 0031 device id is reused for other non Root Port device types,
2989 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
2991 static void quirk_al_msi_disable(struct pci_dev *dev)
2994 pci_warn(dev, "Disabling MSI/MSI-X\n");
2996 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
2997 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
2998 #endif /* CONFIG_PCI_MSI */
3001 * Allow manual resource allocation for PCI hotplug bridges via
3002 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3003 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3004 * allocate resources when hotplug device is inserted and PCI bus is
3007 static void quirk_hotplug_bridge(struct pci_dev *dev)
3009 dev->is_hotplug_bridge = 1;
3011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3014 * This is a quirk for the Ricoh MMC controller found as a part of some
3015 * multifunction chips.
3017 * This is very similar and based on the ricoh_mmc driver written by
3018 * Philip Langdale. Thank you for these magic sequences.
3020 * These chips implement the four main memory card controllers (SD, MMC,
3021 * MS, xD) and one or both of CardBus or FireWire.
3023 * It happens that they implement SD and MMC support as separate
3024 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3025 * cards but the chip detects MMC cards in hardware and directs them to the
3026 * MMC controller - so the SDHCI driver never sees them.
3028 * To get around this, we must disable the useless MMC controller. At that
3029 * point, the SDHCI controller will start seeing them. It seems to be the
3030 * case that the relevant PCI registers to deactivate the MMC controller
3031 * live on PCI function 0, which might be the CardBus controller or the
3032 * FireWire controller, depending on the particular chip in question
3034 * This has to be done early, because as soon as we disable the MMC controller
3035 * other PCI functions shift up one level, e.g. function #2 becomes function
3036 * #1, and this will confuse the PCI core.
3038 #ifdef CONFIG_MMC_RICOH_MMC
3039 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3046 * Disable via CardBus interface
3048 * This must be done via function #0
3050 if (PCI_FUNC(dev->devfn))
3053 pci_read_config_byte(dev, 0xB7, &disable);
3057 pci_read_config_byte(dev, 0x8E, &write_enable);
3058 pci_write_config_byte(dev, 0x8E, 0xAA);
3059 pci_read_config_byte(dev, 0x8D, &write_target);
3060 pci_write_config_byte(dev, 0x8D, 0xB7);
3061 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3062 pci_write_config_byte(dev, 0x8E, write_enable);
3063 pci_write_config_byte(dev, 0x8D, write_target);
3065 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3066 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3068 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3069 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3071 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3077 * Disable via FireWire interface
3079 * This must be done via function #0
3081 if (PCI_FUNC(dev->devfn))
3084 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3085 * certain types of SD/MMC cards. Lowering the SD base clock
3086 * frequency from 200Mhz to 50Mhz fixes this issue.
3088 * 0x150 - SD2.0 mode enable for changing base clock
3089 * frequency to 50Mhz
3090 * 0xe1 - Base clock frequency
3091 * 0x32 - 50Mhz new clock frequency
3092 * 0xf9 - Key register for 0x150
3093 * 0xfc - key register for 0xe1
3095 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3096 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3097 pci_write_config_byte(dev, 0xf9, 0xfc);
3098 pci_write_config_byte(dev, 0x150, 0x10);
3099 pci_write_config_byte(dev, 0xf9, 0x00);
3100 pci_write_config_byte(dev, 0xfc, 0x01);
3101 pci_write_config_byte(dev, 0xe1, 0x32);
3102 pci_write_config_byte(dev, 0xfc, 0x00);
3104 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3107 pci_read_config_byte(dev, 0xCB, &disable);
3112 pci_read_config_byte(dev, 0xCA, &write_enable);
3113 pci_write_config_byte(dev, 0xCA, 0x57);
3114 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3115 pci_write_config_byte(dev, 0xCA, write_enable);
3117 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3118 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3121 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3122 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3123 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3124 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3125 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3126 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3127 #endif /*CONFIG_MMC_RICOH_MMC*/
3129 #ifdef CONFIG_DMAR_TABLE
3130 #define VTUNCERRMSK_REG 0x1ac
3131 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3133 * This is a quirk for masking VT-d spec-defined errors to platform error
3134 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3135 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3136 * on the RAS config settings of the platform) when a VT-d fault happens.
3137 * The resulting SMI caused the system to hang.
3139 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3140 * need to report the same error through other channels.
3142 static void vtd_mask_spec_errors(struct pci_dev *dev)
3146 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3147 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3149 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3150 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3153 static void fixup_ti816x_class(struct pci_dev *dev)
3155 u32 class = dev->class;
3157 /* TI 816x devices do not have class code set when in PCIe boot mode */
3158 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3159 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3162 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3163 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3166 * Some PCIe devices do not work reliably with the claimed maximum
3167 * payload size supported.
3169 static void fixup_mpss_256(struct pci_dev *dev)
3171 dev->pcie_mpss = 1; /* 256 bytes */
3173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3174 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3176 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3178 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3181 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3182 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3183 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3184 * until all of the devices are discovered and buses walked, read completion
3185 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3186 * it is possible to hotplug a device with MPS of 256B.
3188 static void quirk_intel_mc_errata(struct pci_dev *dev)
3193 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3194 pcie_bus_config == PCIE_BUS_DEFAULT)
3198 * Intel erratum specifies bits to change but does not say what
3199 * they are. Keeping them magical until such time as the registers
3200 * and values can be explained.
3202 err = pci_read_config_word(dev, 0x48, &rcc);
3204 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3208 if (!(rcc & (1 << 10)))
3213 err = pci_write_config_word(dev, 0x48, rcc);
3215 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3219 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3221 /* Intel 5000 series memory controllers and ports 2-7 */
3222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3236 /* Intel 5100 series memory controllers and ports 2-7 */
3237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3250 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3251 * To work around this, query the size it should be configured to by the
3252 * device and modify the resource end to correspond to this new size.
3254 static void quirk_intel_ntb(struct pci_dev *dev)
3259 rc = pci_read_config_byte(dev, 0x00D0, &val);
3263 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3265 rc = pci_read_config_byte(dev, 0x00D1, &val);
3269 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3275 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3276 * though no one is handling them (e.g., if the i915 driver is never
3277 * loaded). Additionally the interrupt destination is not set up properly
3278 * and the interrupt ends up -somewhere-.
3280 * These spurious interrupts are "sticky" and the kernel disables the
3281 * (shared) interrupt line after 100,000+ generated interrupts.
3283 * Fix it by disabling the still enabled interrupts. This resolves crashes
3284 * often seen on monitor unplug.
3286 #define I915_DEIER_REG 0x4400c
3287 static void disable_igfx_irq(struct pci_dev *dev)
3289 void __iomem *regs = pci_iomap(dev, 0, 0);
3291 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3295 /* Check if any interrupt line is still enabled */
3296 if (readl(regs + I915_DEIER_REG) != 0) {
3297 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3299 writel(0, regs + I915_DEIER_REG);
3302 pci_iounmap(dev, regs);
3304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3313 * PCI devices which are on Intel chips can skip the 10ms delay
3314 * before entering D3 mode.
3316 static void quirk_remove_d3_delay(struct pci_dev *dev)
3320 /* C600 Series devices do not need 10ms d3_delay */
3321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3324 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3333 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3336 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3348 * Some devices may pass our check in pci_intx_mask_supported() if
3349 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3350 * support this feature.
3352 static void quirk_broken_intx_masking(struct pci_dev *dev)
3354 dev->broken_intx_masking = 1;
3356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3357 quirk_broken_intx_masking);
3358 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3359 quirk_broken_intx_masking);
3360 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3361 quirk_broken_intx_masking);
3364 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3365 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3367 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3370 quirk_broken_intx_masking);
3373 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3374 * DisINTx can be set but the interrupt status bit is non-functional.
3376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3393 static u16 mellanox_broken_intx_devs[] = {
3394 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3395 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3396 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3397 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3398 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3399 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3400 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3401 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3402 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3403 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3404 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3405 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3406 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3407 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3410 #define CONNECTX_4_CURR_MAX_MINOR 99
3411 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3414 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3415 * If so, don't mark it as broken.
3416 * FW minor > 99 means older FW version format and no INTx masking support.
3417 * FW minor < 14 means new FW version format and no INTx masking support.
3419 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3421 __be32 __iomem *fw_ver;
3429 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3430 if (pdev->device == mellanox_broken_intx_devs[i]) {
3431 pdev->broken_intx_masking = 1;
3437 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3438 * support so shouldn't be checked further
3440 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3443 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3444 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3447 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3448 if (pci_enable_device_mem(pdev)) {
3449 pci_warn(pdev, "Can't enable device memory\n");
3453 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3455 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3459 /* Reading from resource space should be 32b aligned */
3460 fw_maj_min = ioread32be(fw_ver);
3461 fw_sub_min = ioread32be(fw_ver + 1);
3462 fw_major = fw_maj_min & 0xffff;
3463 fw_minor = fw_maj_min >> 16;
3464 fw_subminor = fw_sub_min & 0xffff;
3465 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3466 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3467 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3468 fw_major, fw_minor, fw_subminor, pdev->device ==
3469 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3470 pdev->broken_intx_masking = 1;
3476 pci_disable_device(pdev);
3478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3479 mellanox_check_broken_intx_masking);
3481 static void quirk_no_bus_reset(struct pci_dev *dev)
3483 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3487 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3488 * The device will throw a Link Down error on AER-capable systems and
3489 * regardless of AER, config space of the device is never accessible again
3490 * and typically causes the system to hang or reset when access is attempted.
3491 * http://www.spinics.net/lists/linux-pci/msg34797.html
3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3500 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3501 * reset when used with certain child devices. After the reset, config
3502 * accesses to the child may fail.
3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3506 static void quirk_no_pm_reset(struct pci_dev *dev)
3509 * We can't do a bus reset on root bus devices, but an ineffective
3510 * PM reset may be better than nothing.
3512 if (!pci_is_root_bus(dev->bus))
3513 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3517 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3518 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3519 * to have no effect on the device: it retains the framebuffer contents and
3520 * monitor sync. Advertising this support makes other layers, like VFIO,
3521 * assume pci_reset_function() is viable for this device. Mark it as
3522 * unavailable to skip it when testing reset methods.
3524 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3525 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3528 * Thunderbolt controllers with broken MSI hotplug signaling:
3529 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3530 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3532 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3534 if (pdev->is_hotplug_bridge &&
3535 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3536 pdev->revision <= 1))
3539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3540 quirk_thunderbolt_hotplug_msi);
3541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3542 quirk_thunderbolt_hotplug_msi);
3543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3544 quirk_thunderbolt_hotplug_msi);
3545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3546 quirk_thunderbolt_hotplug_msi);
3547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3548 quirk_thunderbolt_hotplug_msi);
3552 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3554 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3555 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3556 * be present after resume if a device was plugged in before suspend.
3558 * The Thunderbolt controller consists of a PCIe switch with downstream
3559 * bridges leading to the NHI and to the tunnel PCI bridges.
3561 * This quirk cuts power to the whole chip. Therefore we have to apply it
3562 * during suspend_noirq of the upstream bridge.
3564 * Power is automagically restored before resume. No action is needed.
3566 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3568 acpi_handle bridge, SXIO, SXFP, SXLV;
3570 if (!x86_apple_machine)
3572 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3574 bridge = ACPI_HANDLE(&dev->dev);
3579 * SXIO and SXLV are present only on machines requiring this quirk.
3580 * Thunderbolt bridges in external devices might have the same
3581 * device ID as those on the host, but they will not have the
3582 * associated ACPI methods. This implicitly checks that we are at
3585 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3586 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3587 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3589 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3591 /* magic sequence */
3592 acpi_execute_simple_method(SXIO, NULL, 1);
3593 acpi_execute_simple_method(SXFP, NULL, 0);
3595 acpi_execute_simple_method(SXLV, NULL, 0);
3596 acpi_execute_simple_method(SXIO, NULL, 0);
3597 acpi_execute_simple_method(SXLV, NULL, 0);
3599 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3600 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3601 quirk_apple_poweroff_thunderbolt);
3604 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3606 * During suspend the Thunderbolt controller is reset and all PCI
3607 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3608 * during resume. We have to manually wait for the NHI since there is
3609 * no parent child relationship between the NHI and the tunneled
3612 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3614 struct pci_dev *sibling = NULL;
3615 struct pci_dev *nhi = NULL;
3617 if (!x86_apple_machine)
3619 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3623 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3624 * host controller and not on a Thunderbolt endpoint.
3626 sibling = pci_get_slot(dev->bus, 0x0);
3628 goto out; /* we are the downstream bridge to the NHI */
3629 if (!sibling || !sibling->subordinate)
3631 nhi = pci_get_slot(sibling->subordinate, 0x0);
3634 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3635 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3636 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3637 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3638 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3639 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3641 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3642 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3645 pci_dev_put(sibling);
3647 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3648 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3649 quirk_apple_wait_for_thunderbolt);
3650 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3651 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3652 quirk_apple_wait_for_thunderbolt);
3653 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3654 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3655 quirk_apple_wait_for_thunderbolt);
3656 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3657 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3658 quirk_apple_wait_for_thunderbolt);
3662 * Following are device-specific reset methods which can be used to
3663 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3666 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3669 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3671 * The 82599 supports FLR on VFs, but FLR support is reported only
3672 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3673 * Thus we must call pcie_flr() directly without first checking if it is
3681 #define SOUTH_CHICKEN2 0xc2004
3682 #define PCH_PP_STATUS 0xc7200
3683 #define PCH_PP_CONTROL 0xc7204
3684 #define MSG_CTL 0x45010
3685 #define NSDE_PWR_STATE 0xd0100
3686 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3688 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3690 void __iomem *mmio_base;
3691 unsigned long timeout;
3697 mmio_base = pci_iomap(dev, 0, 0);
3701 iowrite32(0x00000002, mmio_base + MSG_CTL);
3704 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3705 * driver loaded sets the right bits. However, this's a reset and
3706 * the bits have been set by i915 previously, so we clobber
3707 * SOUTH_CHICKEN2 register directly here.
3709 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3711 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3712 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3714 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3716 val = ioread32(mmio_base + PCH_PP_STATUS);
3717 if ((val & 0xb0000000) == 0)
3718 goto reset_complete;
3720 } while (time_before(jiffies, timeout));
3721 pci_warn(dev, "timeout during reset\n");
3724 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3726 pci_iounmap(dev, mmio_base);
3730 /* Device-specific reset method for Chelsio T4-based adapters */
3731 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3737 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3738 * that we have no device-specific reset method.
3740 if ((dev->device & 0xf000) != 0x4000)
3744 * If this is the "probe" phase, return 0 indicating that we can
3745 * reset this device.
3751 * T4 can wedge if there are DMAs in flight within the chip and Bus
3752 * Master has been disabled. We need to have it on till the Function
3753 * Level Reset completes. (BUS_MASTER is disabled in
3754 * pci_reset_function()).
3756 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3757 pci_write_config_word(dev, PCI_COMMAND,
3758 old_command | PCI_COMMAND_MASTER);
3761 * Perform the actual device function reset, saving and restoring
3762 * configuration information around the reset.
3764 pci_save_state(dev);
3767 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3768 * are disabled when an MSI-X interrupt message needs to be delivered.
3769 * So we briefly re-enable MSI-X interrupts for the duration of the
3770 * FLR. The pci_restore_state() below will restore the original
3773 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3774 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3775 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3777 PCI_MSIX_FLAGS_ENABLE |
3778 PCI_MSIX_FLAGS_MASKALL);
3783 * Restore the configuration information (BAR values, etc.) including
3784 * the original PCI Configuration Space Command word, and return
3787 pci_restore_state(dev);
3788 pci_write_config_word(dev, PCI_COMMAND, old_command);
3792 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3793 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3794 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3797 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3798 * FLR where config space reads from the device return -1. We seem to be
3799 * able to avoid this condition if we disable the NVMe controller prior to
3800 * FLR. This quirk is generic for any NVMe class device requiring similar
3801 * assistance to quiesce the device prior to FLR.
3803 * NVMe specification: https://nvmexpress.org/resources/specifications/
3805 * Chapter 2: Required and optional PCI config registers
3806 * Chapter 3: NVMe control registers
3807 * Chapter 7.3: Reset behavior
3809 static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3815 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3816 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3822 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3826 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3827 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3829 cfg = readl(bar + NVME_REG_CC);
3831 /* Disable controller if enabled */
3832 if (cfg & NVME_CC_ENABLE) {
3833 u32 cap = readl(bar + NVME_REG_CAP);
3834 unsigned long timeout;
3837 * Per nvme_disable_ctrl() skip shutdown notification as it
3838 * could complete commands to the admin queue. We only intend
3839 * to quiesce the device before reset.
3841 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3843 writel(cfg, bar + NVME_REG_CC);
3846 * Some controllers require an additional delay here, see
3847 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3848 * supported by this quirk.
3851 /* Cap register provides max timeout in 500ms increments */
3852 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3855 u32 status = readl(bar + NVME_REG_CSTS);
3857 /* Ready status becomes zero on disable complete */
3858 if (!(status & NVME_CSTS_RDY))
3863 if (time_after(jiffies, timeout)) {
3864 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3870 pci_iounmap(dev, bar);
3878 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3879 * to change after NVMe enable if the driver starts interacting with the
3880 * device too soon after FLR. A 250ms delay after FLR has heuristically
3881 * proven to produce reliably working results for device assignment cases.
3883 static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3885 if (!pcie_has_flr(dev))
3898 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3899 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3900 reset_intel_82599_sfp_virtfn },
3901 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3903 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3905 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3906 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3907 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3908 reset_chelsio_generic_dev },
3913 * These device-specific reset methods are here rather than in a driver
3914 * because when a host assigns a device to a guest VM, the host may need
3915 * to reset the device but probably doesn't have a driver for it.
3917 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3919 const struct pci_dev_reset_methods *i;
3921 for (i = pci_dev_reset_methods; i->reset; i++) {
3922 if ((i->vendor == dev->vendor ||
3923 i->vendor == (u16)PCI_ANY_ID) &&
3924 (i->device == dev->device ||
3925 i->device == (u16)PCI_ANY_ID))
3926 return i->reset(dev, probe);
3932 static void quirk_dma_func0_alias(struct pci_dev *dev)
3934 if (PCI_FUNC(dev->devfn) != 0)
3935 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3939 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3941 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3946 static void quirk_dma_func1_alias(struct pci_dev *dev)
3948 if (PCI_FUNC(dev->devfn) != 1)
3949 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3953 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3954 * SKUs function 1 is present and is a legacy IDE controller, in other
3955 * SKUs this function is not present, making this a ghost requester.
3956 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3959 quirk_dma_func1_alias);
3960 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3961 quirk_dma_func1_alias);
3962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3963 quirk_dma_func1_alias);
3964 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3966 quirk_dma_func1_alias);
3967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
3968 quirk_dma_func1_alias);
3969 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3970 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3971 quirk_dma_func1_alias);
3972 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3973 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3974 quirk_dma_func1_alias);
3975 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3977 quirk_dma_func1_alias);
3978 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
3979 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
3980 quirk_dma_func1_alias);
3981 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3983 quirk_dma_func1_alias);
3984 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3986 quirk_dma_func1_alias);
3987 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3989 quirk_dma_func1_alias);
3990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3991 quirk_dma_func1_alias);
3992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3993 quirk_dma_func1_alias);
3994 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3996 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3997 quirk_dma_func1_alias);
3998 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3999 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4000 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4001 quirk_dma_func1_alias);
4004 * Some devices DMA with the wrong devfn, not just the wrong function.
4005 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4006 * the alias is "fixed" and independent of the device devfn.
4008 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4009 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4010 * single device on the secondary bus. In reality, the single exposed
4011 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4012 * that provides a bridge to the internal bus of the I/O processor. The
4013 * controller supports private devices, which can be hidden from PCI config
4014 * space. In the case of the Adaptec 3405, a private device at 01.0
4015 * appears to be the DMA engine, which therefore needs to become a DMA
4016 * alias for the device.
4018 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4019 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4020 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4021 .driver_data = PCI_DEVFN(1, 0) },
4022 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4023 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4024 .driver_data = PCI_DEVFN(1, 0) },
4028 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4030 const struct pci_device_id *id;
4032 id = pci_match_id(fixed_dma_alias_tbl, dev);
4034 pci_add_dma_alias(dev, id->driver_data);
4037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4040 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4041 * using the wrong DMA alias for the device. Some of these devices can be
4042 * used as either forward or reverse bridges, so we need to test whether the
4043 * device is operating in the correct mode. We could probably apply this
4044 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4045 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4046 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4048 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4050 if (!pci_is_root_bus(pdev->bus) &&
4051 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4052 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4053 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4054 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4056 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4058 quirk_use_pcie_bridge_dma_alias);
4059 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4060 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4061 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4062 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4063 /* ITE 8893 has the same problem as the 8892 */
4064 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4065 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4066 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4069 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4070 * be added as aliases to the DMA device in order to allow buffer access
4071 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4072 * programmed in the EEPROM.
4074 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4076 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4077 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4078 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4084 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4085 * associated not at the root bus, but at a bridge below. This quirk avoids
4086 * generating invalid DMA aliases.
4088 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4090 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4093 quirk_bridge_cavm_thrx2_pcie_root);
4094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4095 quirk_bridge_cavm_thrx2_pcie_root);
4098 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4099 * class code. Fix it.
4101 static void quirk_tw686x_class(struct pci_dev *pdev)
4103 u32 class = pdev->class;
4105 /* Use "Multimedia controller" class */
4106 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4107 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4108 class, pdev->class);
4110 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4111 quirk_tw686x_class);
4112 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4113 quirk_tw686x_class);
4114 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4115 quirk_tw686x_class);
4116 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4117 quirk_tw686x_class);
4120 * Some devices have problems with Transaction Layer Packets with the Relaxed
4121 * Ordering Attribute set. Such devices should mark themselves and other
4122 * device drivers should check before sending TLPs with RO set.
4124 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4126 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4127 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4131 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4132 * Complex have a Flow Control Credit issue which can cause performance
4133 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4135 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4136 quirk_relaxedordering_disable);
4137 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4138 quirk_relaxedordering_disable);
4139 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4140 quirk_relaxedordering_disable);
4141 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4142 quirk_relaxedordering_disable);
4143 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4144 quirk_relaxedordering_disable);
4145 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4146 quirk_relaxedordering_disable);
4147 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4148 quirk_relaxedordering_disable);
4149 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4150 quirk_relaxedordering_disable);
4151 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4152 quirk_relaxedordering_disable);
4153 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4154 quirk_relaxedordering_disable);
4155 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4156 quirk_relaxedordering_disable);
4157 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4158 quirk_relaxedordering_disable);
4159 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4160 quirk_relaxedordering_disable);
4161 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4162 quirk_relaxedordering_disable);
4163 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4164 quirk_relaxedordering_disable);
4165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4166 quirk_relaxedordering_disable);
4167 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4168 quirk_relaxedordering_disable);
4169 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4170 quirk_relaxedordering_disable);
4171 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4172 quirk_relaxedordering_disable);
4173 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4174 quirk_relaxedordering_disable);
4175 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4176 quirk_relaxedordering_disable);
4177 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4178 quirk_relaxedordering_disable);
4179 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4180 quirk_relaxedordering_disable);
4181 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4182 quirk_relaxedordering_disable);
4183 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4184 quirk_relaxedordering_disable);
4185 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4186 quirk_relaxedordering_disable);
4187 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4188 quirk_relaxedordering_disable);
4189 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4190 quirk_relaxedordering_disable);
4193 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4194 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4195 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4196 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4197 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4198 * November 10, 2010). As a result, on this platform we can't use Relaxed
4199 * Ordering for Upstream TLPs.
4201 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4202 quirk_relaxedordering_disable);
4203 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4204 quirk_relaxedordering_disable);
4205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4206 quirk_relaxedordering_disable);
4209 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4210 * values for the Attribute as were supplied in the header of the
4211 * corresponding Request, except as explicitly allowed when IDO is used."
4213 * If a non-compliant device generates a completion with a different
4214 * attribute than the request, the receiver may accept it (which itself
4215 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4216 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4217 * device access timeout.
4219 * If the non-compliant device generates completions with zero attributes
4220 * (instead of copying the attributes from the request), we can work around
4221 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4222 * upstream devices so they always generate requests with zero attributes.
4224 * This affects other devices under the same Root Port, but since these
4225 * attributes are performance hints, there should be no functional problem.
4227 * Note that Configuration Space accesses are never supposed to have TLP
4228 * Attributes, so we're safe waiting till after any Configuration Space
4229 * accesses to do the Root Port fixup.
4231 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4233 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4236 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4240 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4241 dev_name(&pdev->dev));
4242 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4243 PCI_EXP_DEVCTL_RELAX_EN |
4244 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4248 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4249 * Completion it generates.
4251 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4254 * This mask/compare operation selects for Physical Function 4 on a
4255 * T5. We only need to fix up the Root Port once for any of the
4256 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4257 * 0x54xx so we use that one.
4259 if ((pdev->device & 0xff00) == 0x5400)
4260 quirk_disable_root_port_attributes(pdev);
4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4263 quirk_chelsio_T5_disable_root_port_attributes);
4266 * AMD has indicated that the devices below do not support peer-to-peer
4267 * in any system where they are found in the southbridge with an AMD
4268 * IOMMU in the system. Multifunction devices that do not support
4269 * peer-to-peer between functions can claim to support a subset of ACS.
4270 * Such devices effectively enable request redirect (RR) and completion
4271 * redirect (CR) since all transactions are redirected to the upstream
4274 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4275 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4276 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4278 * 1002:4385 SBx00 SMBus Controller
4279 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4280 * 1002:4383 SBx00 Azalia (Intel HDA)
4281 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4282 * 1002:4384 SBx00 PCI to PCI Bridge
4283 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4285 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4287 * 1022:780f [AMD] FCH PCI Bridge
4288 * 1022:7809 [AMD] FCH USB OHCI Controller
4290 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4293 struct acpi_table_header *header = NULL;
4296 /* Targeting multifunction devices on the SB (appears on root bus) */
4297 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4300 /* The IVRS table describes the AMD IOMMU */
4301 status = acpi_get_table("IVRS", 0, &header);
4302 if (ACPI_FAILURE(status))
4305 /* Filter out flags not applicable to multifunction */
4306 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4308 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4314 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4317 * Effectively selects all downstream ports for whole ThunderX 1
4318 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4319 * bits of device ID are used to indicate which subdevice is used
4322 return (pci_is_pcie(dev) &&
4323 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4324 ((dev->device & 0xf800) == 0xa000));
4327 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4330 * Cavium root ports don't advertise an ACS capability. However,
4331 * the RTL internally implements similar protection as if ACS had
4332 * Request Redirection, Completion Redirection, Source Validation,
4333 * and Upstream Forwarding features enabled. Assert that the
4334 * hardware implements and enables equivalent ACS functionality for
4337 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4339 if (!pci_quirk_cavium_acs_match(dev))
4342 return acs_flags ? 0 : 1;
4345 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4348 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4349 * transactions with others, allowing masking out these bits as if they
4350 * were unimplemented in the ACS capability.
4352 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4354 return acs_flags ? 0 : 1;
4358 * Many Intel PCH root ports do provide ACS-like features to disable peer
4359 * transactions and validate bus numbers in requests, but do not provide an
4360 * actual PCIe ACS capability. This is the list of device IDs known to fall
4361 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4363 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4365 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4366 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4367 /* Cougarpoint PCH */
4368 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4369 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4370 /* Pantherpoint PCH */
4371 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4372 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4373 /* Lynxpoint-H PCH */
4374 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4375 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4376 /* Lynxpoint-LP PCH */
4377 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4378 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4380 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4381 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4382 /* Patsburg (X79) PCH */
4383 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4384 /* Wellsburg (X99) PCH */
4385 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4386 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4387 /* Lynx Point (9 series) PCH */
4388 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4391 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4395 /* Filter out a few obvious non-matches first */
4396 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4399 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4400 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4406 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4408 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4410 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4411 INTEL_PCH_ACS_FLAGS : 0;
4413 if (!pci_quirk_intel_pch_acs_match(dev))
4416 return acs_flags & ~flags ? 0 : 1;
4420 * These QCOM root ports do provide ACS-like features to disable peer
4421 * transactions and validate bus numbers in requests, but do not provide an
4422 * actual PCIe ACS capability. Hardware supports source validation but it
4423 * will report the issue as Completer Abort instead of ACS Violation.
4424 * Hardware doesn't support peer-to-peer and each root port is a root
4425 * complex with unique segment numbers. It is not possible for one root
4426 * port to pass traffic to another root port. All PCIe transactions are
4427 * terminated inside the root port.
4429 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4431 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4432 int ret = acs_flags & ~flags ? 0 : 1;
4434 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
4439 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4441 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4445 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4446 * but do include ACS-like functionality. The hardware doesn't support
4447 * peer-to-peer transactions via the root port and each has a unique
4450 * Additionally, the root ports cannot send traffic to each other.
4452 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4454 return acs_flags ? 0 : 1;
4458 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4459 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4460 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4461 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4462 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4463 * control register is at offset 8 instead of 6 and we should probably use
4464 * dword accesses to them. This applies to the following PCI Device IDs, as
4465 * found in volume 1 of the datasheet[2]:
4467 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4468 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4470 * N.B. This doesn't fix what lspci shows.
4472 * The 100 series chipset specification update includes this as errata #23[3].
4474 * The 200 series chipset (Union Point) has the same bug according to the
4475 * specification update (Intel 200 Series Chipset Family Platform Controller
4476 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4477 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4480 * 0xa290-0xa29f PCI Express Root port #{0-16}
4481 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4483 * Mobile chipsets are also affected, 7th & 8th Generation
4484 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4485 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4486 * Processor Family I/O for U Quad Core Platforms Specification Update,
4487 * August 2017, Revision 002, Document#: 334660-002)[6]
4488 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4489 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4490 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4492 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4494 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4495 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4496 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4497 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4498 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4499 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4500 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4502 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4504 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4507 switch (dev->device) {
4508 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4509 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4510 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4517 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4519 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4524 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4527 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4531 /* see pci_acs_flags_enabled() */
4532 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4533 acs_flags &= (cap | PCI_ACS_EC);
4535 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4537 return acs_flags & ~ctrl ? 0 : 1;
4540 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4543 * SV, TB, and UF are not relevant to multifunction endpoints.
4545 * Multifunction devices are only required to implement RR, CR, and DT
4546 * in their ACS capability if they support peer-to-peer transactions.
4547 * Devices matching this quirk have been verified by the vendor to not
4548 * perform peer-to-peer with other functions, allowing us to mask out
4549 * these bits as if they were unimplemented in the ACS capability.
4551 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4552 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4554 return acs_flags ? 0 : 1;
4557 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4560 * iProc PAXB Root Ports don't advertise an ACS capability, but
4561 * they do not allow peer-to-peer transactions between Root Ports.
4562 * Allow each Root Port to be in a separate IOMMU group by masking
4565 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4567 return acs_flags ? 0 : 1;
4570 static const struct pci_dev_acs_enabled {
4573 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4574 } pci_dev_acs_enabled[] = {
4575 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4576 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4577 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4578 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4579 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4580 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4581 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4582 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4583 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4584 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4585 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4586 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4587 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4588 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4589 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4590 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4591 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4592 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4593 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4594 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4595 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4596 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4597 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4598 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4599 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4600 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4601 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4602 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4603 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4604 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4605 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4607 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4608 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4609 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4610 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4611 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4612 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4613 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4615 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4616 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4617 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4618 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4619 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4620 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4621 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4622 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4624 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4625 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4626 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4628 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4629 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4630 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4631 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4632 /* 82571 (Quads omitted due to non-ACS switch) */
4633 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4634 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4635 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4636 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4638 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4639 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4640 /* QCOM QDF2xxx root ports */
4641 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4642 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4643 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4644 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4645 /* Intel PCH root ports */
4646 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4647 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4648 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4649 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4650 /* Cavium ThunderX */
4651 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4653 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4654 /* Ampere Computing */
4655 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4656 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4657 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4658 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4659 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4660 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4661 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4662 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4663 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4664 /* Amazon Annapurna Labs */
4665 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4669 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4671 const struct pci_dev_acs_enabled *i;
4675 * Allow devices that do not expose standard PCIe ACS capabilities
4676 * or control to indicate their support here. Multi-function express
4677 * devices which do not allow internal peer-to-peer between functions,
4678 * but do not implement PCIe ACS may wish to return true here.
4680 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4681 if ((i->vendor == dev->vendor ||
4682 i->vendor == (u16)PCI_ANY_ID) &&
4683 (i->device == dev->device ||
4684 i->device == (u16)PCI_ANY_ID)) {
4685 ret = i->acs_enabled(dev, acs_flags);
4694 /* Config space offset of Root Complex Base Address register */
4695 #define INTEL_LPC_RCBA_REG 0xf0
4696 /* 31:14 RCBA address */
4697 #define INTEL_LPC_RCBA_MASK 0xffffc000
4699 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4701 /* Backbone Scratch Pad Register */
4702 #define INTEL_BSPR_REG 0x1104
4703 /* Backbone Peer Non-Posted Disable */
4704 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4705 /* Backbone Peer Posted Disable */
4706 #define INTEL_BSPR_REG_BPPD (1 << 9)
4708 /* Upstream Peer Decode Configuration Register */
4709 #define INTEL_UPDCR_REG 0x1114
4710 /* 5:0 Peer Decode Enable bits */
4711 #define INTEL_UPDCR_REG_MASK 0x3f
4713 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4715 u32 rcba, bspr, updcr;
4716 void __iomem *rcba_mem;
4719 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4720 * are D28:F* and therefore get probed before LPC, thus we can't
4721 * use pci_get_slot()/pci_read_config_dword() here.
4723 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4724 INTEL_LPC_RCBA_REG, &rcba);
4725 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4728 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4729 PAGE_ALIGN(INTEL_UPDCR_REG));
4734 * The BSPR can disallow peer cycles, but it's set by soft strap and
4735 * therefore read-only. If both posted and non-posted peer cycles are
4736 * disallowed, we're ok. If either are allowed, then we need to use
4737 * the UPDCR to disable peer decodes for each port. This provides the
4738 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4740 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4741 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4742 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4743 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4744 if (updcr & INTEL_UPDCR_REG_MASK) {
4745 pci_info(dev, "Disabling UPDCR peer decodes\n");
4746 updcr &= ~INTEL_UPDCR_REG_MASK;
4747 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4755 /* Miscellaneous Port Configuration register */
4756 #define INTEL_MPC_REG 0xd8
4757 /* MPC: Invalid Receive Bus Number Check Enable */
4758 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4760 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4765 * When enabled, the IRBNCE bit of the MPC register enables the
4766 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4767 * ensures that requester IDs fall within the bus number range
4768 * of the bridge. Enable if not already.
4770 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4771 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4772 pci_info(dev, "Enabling MPC IRBNCE\n");
4773 mpc |= INTEL_MPC_REG_IRBNCE;
4774 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4778 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4780 if (!pci_quirk_intel_pch_acs_match(dev))
4783 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4784 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4788 pci_quirk_enable_intel_rp_mpc_acs(dev);
4790 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4792 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4797 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4802 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4805 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4809 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4810 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4812 ctrl |= (cap & PCI_ACS_SV);
4813 ctrl |= (cap & PCI_ACS_RR);
4814 ctrl |= (cap & PCI_ACS_CR);
4815 ctrl |= (cap & PCI_ACS_UF);
4817 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4819 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4824 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4829 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4832 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4836 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4837 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4839 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
4841 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4843 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4848 static const struct pci_dev_acs_ops {
4851 int (*enable_acs)(struct pci_dev *dev);
4852 int (*disable_acs_redir)(struct pci_dev *dev);
4853 } pci_dev_acs_ops[] = {
4854 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4855 .enable_acs = pci_quirk_enable_intel_pch_acs,
4857 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4858 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
4859 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
4863 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4865 const struct pci_dev_acs_ops *p;
4868 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4869 p = &pci_dev_acs_ops[i];
4870 if ((p->vendor == dev->vendor ||
4871 p->vendor == (u16)PCI_ANY_ID) &&
4872 (p->device == dev->device ||
4873 p->device == (u16)PCI_ANY_ID) &&
4875 ret = p->enable_acs(dev);
4884 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
4886 const struct pci_dev_acs_ops *p;
4889 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4890 p = &pci_dev_acs_ops[i];
4891 if ((p->vendor == dev->vendor ||
4892 p->vendor == (u16)PCI_ANY_ID) &&
4893 (p->device == dev->device ||
4894 p->device == (u16)PCI_ANY_ID) &&
4895 p->disable_acs_redir) {
4896 ret = p->disable_acs_redir(dev);
4906 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4907 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4908 * Next Capability pointer in the MSI Capability Structure should point to
4909 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4912 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4917 struct pci_cap_saved_state *state;
4919 /* Bail if the hardware bug is fixed */
4920 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4923 /* Bail if MSI Capability Structure is not found for some reason */
4924 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4929 * Bail if Next Capability pointer in the MSI Capability Structure
4930 * is not the expected incorrect 0x00.
4932 pci_read_config_byte(pdev, pos + 1, &next_cap);
4937 * PCIe Capability Structure is expected to be at 0x50 and should
4938 * terminate the list (Next Capability pointer is 0x00). Verify
4939 * Capability Id and Next Capability pointer is as expected.
4940 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4941 * to correctly set kernel data structures which have already been
4942 * set incorrectly due to the hardware bug.
4945 pci_read_config_word(pdev, pos, ®16);
4946 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4948 #ifndef PCI_EXP_SAVE_REGS
4949 #define PCI_EXP_SAVE_REGS 7
4951 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4953 pdev->pcie_cap = pos;
4954 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
4955 pdev->pcie_flags_reg = reg16;
4956 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
4957 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4959 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4960 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4961 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4962 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4964 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4968 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4972 state->cap.cap_nr = PCI_CAP_ID_EXP;
4973 state->cap.cap_extended = 0;
4974 state->cap.size = size;
4975 cap = (u16 *)&state->cap.data[0];
4976 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4977 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4978 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4979 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4980 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4981 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4982 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4983 hlist_add_head(&state->next, &pdev->saved_cap_space);
4986 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4988 /* FLR may cause some 82579 devices to hang */
4989 static void quirk_intel_no_flr(struct pci_dev *dev)
4991 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4993 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4994 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4996 static void quirk_no_ext_tags(struct pci_dev *pdev)
4998 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5003 bridge->no_ext_tags = 1;
5004 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5006 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5008 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5009 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5010 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5011 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5012 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5013 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5014 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5016 #ifdef CONFIG_PCI_ATS
5018 * Some devices have a broken ATS implementation causing IOMMU stalls.
5019 * Don't use ATS for those devices.
5021 static void quirk_no_ats(struct pci_dev *pdev)
5023 pci_info(pdev, "disabling ATS (broken on this device)\n");
5027 /* AMD Stoney platform GPU */
5028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
5029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
5030 #endif /* CONFIG_PCI_ATS */
5032 /* Freescale PCIe doesn't support MSI in RC mode */
5033 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5035 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5041 * Although not allowed by the spec, some multi-function devices have
5042 * dependencies of one function (consumer) on another (supplier). For the
5043 * consumer to work in D0, the supplier must also be in D0. Create a
5044 * device link from the consumer to the supplier to enforce this
5045 * dependency. Runtime PM is allowed by default on the consumer to prevent
5046 * it from permanently keeping the supplier awake.
5048 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5049 unsigned int supplier, unsigned int class,
5050 unsigned int class_shift)
5052 struct pci_dev *supplier_pdev;
5054 if (PCI_FUNC(pdev->devfn) != consumer)
5057 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5059 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5060 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5061 pci_dev_put(supplier_pdev);
5065 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5066 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5067 pci_info(pdev, "D0 power state depends on %s\n",
5068 pci_name(supplier_pdev));
5070 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5071 pci_name(supplier_pdev));
5073 pm_runtime_allow(&pdev->dev);
5074 pci_dev_put(supplier_pdev);
5078 * Create device link for GPUs with integrated HDA controller for streaming
5079 * audio to attached displays.
5081 static void quirk_gpu_hda(struct pci_dev *hda)
5083 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5085 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5086 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5087 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5088 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5089 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5090 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5093 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5094 * controller to VGA.
5096 static void quirk_gpu_usb(struct pci_dev *usb)
5098 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5100 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5101 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5104 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5105 * to VGA. Currently there is no class code defined for UCSI device over PCI
5106 * so using UNKNOWN class for now and it will be updated when UCSI
5107 * over PCI gets a class code.
5109 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5110 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5112 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5114 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5115 PCI_CLASS_SERIAL_UNKNOWN, 8,
5116 quirk_gpu_usb_typec_ucsi);
5119 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5120 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5122 static void quirk_nvidia_hda(struct pci_dev *gpu)
5127 /* There was no integrated HDA controller before MCP89 */
5128 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5131 /* Bit 25 at offset 0x488 enables the HDA controller */
5132 pci_read_config_dword(gpu, 0x488, &val);
5136 pci_info(gpu, "Enabling HDA controller\n");
5137 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5139 /* The GPU becomes a multi-function device when the HDA is enabled */
5140 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5141 gpu->multifunction = !!(hdr_type & 0x80);
5143 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5144 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5145 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5146 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5149 * Some IDT switches incorrectly flag an ACS Source Validation error on
5150 * completions for config read requests even though PCIe r4.0, sec
5151 * 6.12.1.1, says that completions are never affected by ACS Source
5152 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5154 * Item #36 - Downstream port applies ACS Source Validation to Completions
5155 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5156 * completions are never affected by ACS Source Validation. However,
5157 * completions received by a downstream port of the PCIe switch from a
5158 * device that has not yet captured a PCIe bus number are incorrectly
5159 * dropped by ACS Source Validation by the switch downstream port.
5161 * The workaround suggested by IDT is to issue a config write to the
5162 * downstream device before issuing the first config read. This allows the
5163 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5164 * sec 2.2.9), thus avoiding the ACS error on the completion.
5166 * However, we don't know when the device is ready to accept the config
5167 * write, so we do config reads until we receive a non-Config Request Retry
5168 * Status, then do the config write.
5170 * To avoid hitting the erratum when doing the config reads, we disable ACS
5171 * SV around this process.
5173 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5178 struct pci_dev *bridge = bus->self;
5180 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5182 /* Disable ACS SV before initial config reads */
5184 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5185 if (ctrl & PCI_ACS_SV)
5186 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5187 ctrl & ~PCI_ACS_SV);
5190 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5192 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5194 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5196 /* Re-enable ACS_SV if it was previously enabled */
5197 if (ctrl & PCI_ACS_SV)
5198 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5204 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5205 * NT endpoints via the internal switch fabric. These IDs replace the
5206 * originating requestor ID TLPs which access host memory on peer NTB
5207 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5208 * to permit access when the IOMMU is turned on.
5210 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5213 struct ntb_info_regs __iomem *mmio_ntb;
5214 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5219 if (pci_enable_device(pdev)) {
5220 pci_err(pdev, "Cannot enable Switchtec device\n");
5224 mmio = pci_iomap(pdev, 0, 0);
5226 pci_disable_device(pdev);
5227 pci_err(pdev, "Cannot iomap Switchtec device\n");
5231 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5233 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5234 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5236 partition = ioread8(&mmio_ntb->partition_id);
5238 partition_map = ioread32(&mmio_ntb->ep_map);
5239 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5240 partition_map &= ~(1ULL << partition);
5242 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5243 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5247 if (!(partition_map & (1ULL << pp)))
5250 pci_dbg(pdev, "Processing partition %d\n", pp);
5252 mmio_peer_ctrl = &mmio_ctrl[pp];
5254 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5256 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5260 if (table_sz > 512) {
5262 "Invalid Switchtec partition %d table_sz %d\n",
5267 for (te = 0; te < table_sz; te++) {
5271 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5272 devfn = (rid_entry >> 1) & 0xFF;
5274 "Aliasing Partition %d Proxy ID %02x.%d\n",
5275 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5276 pci_add_dma_alias(pdev, devfn);
5280 pci_iounmap(pdev, mmio);
5281 pci_disable_device(pdev);
5283 #define SWITCHTEC_QUIRK(vid) \
5284 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5285 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5287 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5288 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5289 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5290 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5291 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5292 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5293 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5294 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5295 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5296 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5297 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5298 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5299 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5300 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5301 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5302 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5303 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5304 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5305 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5306 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5307 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5308 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5309 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5310 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5311 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5312 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5313 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5314 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5315 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5316 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5319 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5320 * not always reset the secondary Nvidia GPU between reboots if the system
5321 * is configured to use Hybrid Graphics mode. This results in the GPU
5322 * being left in whatever state it was in during the *previous* boot, which
5323 * causes spurious interrupts from the GPU, which in turn causes us to
5324 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5325 * this also completely breaks nouveau.
5327 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5328 * clean state and fixes all these issues.
5330 * When the machine is configured in Dedicated display mode, the issue
5331 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5332 * mode, so we can detect that and avoid resetting it.
5334 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5339 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5340 pdev->subsystem_device != 0x222e ||
5344 if (pci_enable_device_mem(pdev))
5348 * Based on nvkm_device_ctor() in
5349 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5351 map = pci_iomap(pdev, 0, 0x23000);
5353 pci_err(pdev, "Can't map MMIO space\n");
5358 * Make sure the GPU looks like it's been POSTed before resetting
5361 if (ioread32(map + 0x2240c) & 0x2) {
5362 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5363 ret = pci_reset_bus(pdev);
5365 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5370 pci_disable_device(pdev);
5372 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5373 PCI_CLASS_DISPLAY_VGA, 8,
5374 quirk_reset_lenovo_thinkpad_p50_nvgpu);