2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
23 LIST_HEAD(pci_devices);
25 #ifdef HAVE_PCI_LEGACY
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
34 static void pci_create_legacy_files(struct pci_bus *b)
36 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
39 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
40 b->legacy_io->attr.name = "legacy_io";
41 b->legacy_io->size = 0xffff;
42 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
43 b->legacy_io->attr.owner = THIS_MODULE;
44 b->legacy_io->read = pci_read_legacy_io;
45 b->legacy_io->write = pci_write_legacy_io;
46 class_device_create_bin_file(&b->class_dev, b->legacy_io);
48 /* Allocated above after the legacy_io struct */
49 b->legacy_mem = b->legacy_io + 1;
50 b->legacy_mem->attr.name = "legacy_mem";
51 b->legacy_mem->size = 1024*1024;
52 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
53 b->legacy_mem->attr.owner = THIS_MODULE;
54 b->legacy_mem->mmap = pci_mmap_legacy_mem;
55 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
59 void pci_remove_legacy_files(struct pci_bus *b)
62 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
63 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
64 kfree(b->legacy_io); /* both are allocated here */
67 #else /* !HAVE_PCI_LEGACY */
68 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
69 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
70 #endif /* HAVE_PCI_LEGACY */
73 * PCI Bus Class Devices
75 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
81 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
82 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
87 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
92 static void release_pcibus_dev(struct class_device *class_dev)
94 struct pci_bus *pci_bus = to_pci_bus(class_dev);
97 put_device(pci_bus->bridge);
101 static struct class pcibus_class = {
103 .release = &release_pcibus_dev,
106 static int __init pcibus_class_init(void)
108 return class_register(&pcibus_class);
110 postcore_initcall(pcibus_class_init);
113 * Translate the low bits of the PCI base
114 * to the resource type
116 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
118 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
119 return IORESOURCE_IO;
121 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
122 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
124 return IORESOURCE_MEM;
128 * Find the extent of a PCI decode..
130 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
132 u32 size = mask & maxbase; /* Find the significant bits */
136 /* Get the lowest of them to find the decode size, and
137 from that the extent. */
138 size = (size & ~(size-1)) - 1;
140 /* base == maxbase can be valid only if the BAR has
141 already been programmed with all 1s. */
142 if (base == maxbase && ((base | size) & mask) != mask)
148 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
150 unsigned int pos, reg, next;
152 struct resource *res;
154 for(pos=0; pos<howmany; pos = next) {
156 res = &dev->resource[pos];
157 res->name = pci_name(dev);
158 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
159 pci_read_config_dword(dev, reg, &l);
160 pci_write_config_dword(dev, reg, ~0);
161 pci_read_config_dword(dev, reg, &sz);
162 pci_write_config_dword(dev, reg, l);
163 if (!sz || sz == 0xffffffff)
167 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
168 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
171 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
172 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
174 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
177 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
178 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
180 res->end = res->start + (unsigned long) sz;
181 res->flags |= pci_calc_resource_flags(l);
182 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
183 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
184 pci_read_config_dword(dev, reg+4, &l);
186 #if BITS_PER_LONG == 64
187 res->start |= ((unsigned long) l) << 32;
188 res->end = res->start + sz;
189 pci_write_config_dword(dev, reg+4, ~0);
190 pci_read_config_dword(dev, reg+4, &sz);
191 pci_write_config_dword(dev, reg+4, l);
192 sz = pci_size(l, sz, 0xffffffff);
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)sz<<32;
199 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
208 dev->rom_base_reg = rom;
209 res = &dev->resource[PCI_ROM_RESOURCE];
210 res->name = pci_name(dev);
211 pci_read_config_dword(dev, rom, &l);
212 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
213 pci_read_config_dword(dev, rom, &sz);
214 pci_write_config_dword(dev, rom, l);
217 if (sz && sz != 0xffffffff) {
218 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
220 res->flags = (l & IORESOURCE_ROM_ENABLE) |
221 IORESOURCE_MEM | IORESOURCE_PREFETCH |
222 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
223 res->start = l & PCI_ROM_ADDRESS_MASK;
224 res->end = res->start + (unsigned long) sz;
230 void __devinit pci_read_bridge_bases(struct pci_bus *child)
232 struct pci_dev *dev = child->self;
233 u8 io_base_lo, io_limit_lo;
234 u16 mem_base_lo, mem_limit_lo;
235 unsigned long base, limit;
236 struct resource *res;
239 if (!dev) /* It's a host bus, nothing to read */
242 if (dev->transparent) {
243 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
244 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
245 child->resource[i] = child->parent->resource[i - 3];
249 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
251 res = child->resource[0];
252 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
253 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
254 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
255 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
257 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
258 u16 io_base_hi, io_limit_hi;
259 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
260 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
261 base |= (io_base_hi << 16);
262 limit |= (io_limit_hi << 16);
266 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
268 res->end = limit + 0xfff;
271 res = child->resource[1];
272 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
273 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
274 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
275 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
277 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
279 res->end = limit + 0xfffff;
282 res = child->resource[2];
283 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
284 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
285 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
286 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
288 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
289 u32 mem_base_hi, mem_limit_hi;
290 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
291 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
294 * Some bridges set the base > limit by default, and some
295 * (broken) BIOSes do not initialize them. If we find
296 * this, just assume they are not being used.
298 if (mem_base_hi <= mem_limit_hi) {
299 #if BITS_PER_LONG == 64
300 base |= ((long) mem_base_hi) << 32;
301 limit |= ((long) mem_limit_hi) << 32;
303 if (mem_base_hi || mem_limit_hi) {
304 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
311 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
313 res->end = limit + 0xfffff;
317 static struct pci_bus * __devinit pci_alloc_bus(void)
321 b = kmalloc(sizeof(*b), GFP_KERNEL);
323 memset(b, 0, sizeof(*b));
324 INIT_LIST_HEAD(&b->node);
325 INIT_LIST_HEAD(&b->children);
326 INIT_LIST_HEAD(&b->devices);
331 static struct pci_bus * __devinit
332 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
334 struct pci_bus *child;
338 * Allocate a new bus, and inherit stuff from the parent..
340 child = pci_alloc_bus();
344 child->self = bridge;
345 child->parent = parent;
346 child->ops = parent->ops;
347 child->sysdata = parent->sysdata;
348 child->bridge = get_device(&bridge->dev);
350 child->class_dev.class = &pcibus_class;
351 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
352 class_device_register(&child->class_dev);
353 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
356 * Set up the primary, secondary and subordinate
359 child->number = child->secondary = busnr;
360 child->primary = parent->secondary;
361 child->subordinate = 0xff;
363 /* Set up default resource pointers and names.. */
364 for (i = 0; i < 4; i++) {
365 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
366 child->resource[i]->name = child->name;
368 bridge->subordinate = child;
373 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
375 struct pci_bus *child;
377 child = pci_alloc_child_bus(parent, dev, busnr);
379 spin_lock(&pci_bus_lock);
380 list_add_tail(&child->node, &parent->children);
381 spin_unlock(&pci_bus_lock);
386 static void pci_enable_crs(struct pci_dev *dev)
389 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
393 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
394 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
397 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
398 rpctl |= PCI_EXP_RTCTL_CRSSVE;
399 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
402 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
404 struct pci_bus *parent = child->parent;
406 /* Attempts to fix that up are really dangerous unless
407 we're going to re-assign all bus numbers. */
408 if (!pcibios_assign_all_busses())
411 while (parent->parent && parent->subordinate < max) {
412 parent->subordinate = max;
413 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
414 parent = parent->parent;
418 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
421 * If it's a bridge, configure it and scan the bus behind it.
422 * For CardBus bridges, we don't scan behind as the devices will
423 * be handled by the bridge driver itself.
425 * We need to process bridges in two passes -- first we scan those
426 * already configured by the BIOS and after we are done with all of
427 * them, we proceed to assigning numbers to the remaining buses in
428 * order to avoid overlaps between old and new bus numbers.
430 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
432 struct pci_bus *child;
433 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
437 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
439 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
440 pci_name(dev), buses & 0xffffff, pass);
442 /* Disable MasterAbortMode during probing to avoid reporting
443 of bus errors (in some architectures) */
444 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
445 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
446 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
450 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
451 unsigned int cmax, busnr;
453 * Bus already configured by firmware, process it in the first
454 * pass and just note the configuration.
458 busnr = (buses >> 8) & 0xFF;
461 * If we already got to this bus through a different bridge,
462 * ignore it. This can happen with the i450NX chipset.
464 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
465 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
466 pci_domain_nr(bus), busnr);
470 child = pci_add_new_bus(bus, dev, busnr);
473 child->primary = buses & 0xFF;
474 child->subordinate = (buses >> 16) & 0xFF;
475 child->bridge_ctl = bctl;
477 cmax = pci_scan_child_bus(child);
480 if (child->subordinate > max)
481 max = child->subordinate;
484 * We need to assign a number to this bus which we always
485 * do in the second pass.
488 if (pcibios_assign_all_busses())
489 /* Temporarily disable forwarding of the
490 configuration cycles on all bridges in
491 this bus segment to avoid possible
492 conflicts in the second pass between two
493 bridges programmed with overlapping
495 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
501 pci_write_config_word(dev, PCI_STATUS, 0xffff);
503 /* Prevent assigning a bus number that already exists.
504 * This can happen when a bridge is hot-plugged */
505 if (pci_find_bus(pci_domain_nr(bus), max+1))
507 child = pci_add_new_bus(bus, dev, ++max);
508 buses = (buses & 0xff000000)
509 | ((unsigned int)(child->primary) << 0)
510 | ((unsigned int)(child->secondary) << 8)
511 | ((unsigned int)(child->subordinate) << 16);
514 * yenta.c forces a secondary latency timer of 176.
515 * Copy that behaviour here.
518 buses &= ~0xff000000;
519 buses |= CARDBUS_LATENCY_TIMER << 24;
523 * We need to blast all three values with a single write.
525 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
528 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
530 * Adjust subordinate busnr in parent buses.
531 * We do this before scanning for children because
532 * some devices may not be detected if the bios
535 pci_fixup_parent_subordinate_busnr(child, max);
536 /* Now we can scan all subordinate buses... */
537 max = pci_scan_child_bus(child);
540 * For CardBus bridges, we leave 4 bus numbers
541 * as cards with a PCI-to-PCI bridge can be
544 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++)
545 if (pci_find_bus(pci_domain_nr(bus),
549 pci_fixup_parent_subordinate_busnr(child, max);
552 * Set the subordinate bus number to its real value.
554 child->subordinate = max;
555 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
558 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
560 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
566 * Read interrupt line and base address registers.
567 * The architecture-dependent code can tweak these, of course.
569 static void pci_read_irq(struct pci_dev *dev)
573 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
575 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
580 * pci_setup_device - fill in class and map information of a device
581 * @dev: the device structure to fill
583 * Initialize the device structure with information about the device's
584 * vendor,class,memory and IO-space addresses,IRQ lines etc.
585 * Called at initialisation of the PCI subsystem and by CardBus services.
586 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
589 static int pci_setup_device(struct pci_dev * dev)
593 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
594 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
596 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
597 class >>= 8; /* upper 3 bytes */
601 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
602 dev->vendor, dev->device, class, dev->hdr_type);
604 /* "Unknown power state" */
605 dev->current_state = PCI_UNKNOWN;
607 /* Early fixups, before probing the BARs */
608 pci_fixup_device(pci_fixup_early, dev);
609 class = dev->class >> 8;
611 switch (dev->hdr_type) { /* header type */
612 case PCI_HEADER_TYPE_NORMAL: /* standard header */
613 if (class == PCI_CLASS_BRIDGE_PCI)
616 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
617 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
618 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
621 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
622 if (class != PCI_CLASS_BRIDGE_PCI)
624 /* The PCI-to-PCI bridge spec requires that subtractive
625 decoding (i.e. transparent) bridge must have programming
626 interface code of 0x01. */
627 dev->transparent = ((dev->class & 0xff) == 1);
628 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
631 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
632 if (class != PCI_CLASS_BRIDGE_CARDBUS)
635 pci_read_bases(dev, 1, 0);
636 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
637 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
640 default: /* unknown header */
641 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
642 pci_name(dev), dev->hdr_type);
646 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
647 pci_name(dev), class, dev->hdr_type);
648 dev->class = PCI_CLASS_NOT_DEFINED;
651 /* We found a fine healthy device, go go go... */
656 * pci_release_dev - free a pci device structure when all users of it are finished.
657 * @dev: device that's been disconnected
659 * Will be called only by the device core when all users of this pci device are
662 static void pci_release_dev(struct device *dev)
664 struct pci_dev *pci_dev;
666 pci_dev = to_pci_dev(dev);
671 * pci_cfg_space_size - get the configuration space size of the PCI device.
673 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
674 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
675 * access it. Maybe we don't have a way to generate extended config space
676 * accesses, or the device is behind a reverse Express bridge. So we try
677 * reading the dword at 0x100 which must either be 0 or a valid extended
680 static int pci_cfg_space_size(struct pci_dev *dev)
685 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
687 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
691 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
692 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
696 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
698 if (status == 0xffffffff)
701 return PCI_CFG_SPACE_EXP_SIZE;
704 return PCI_CFG_SPACE_SIZE;
707 static void pci_release_bus_bridge_dev(struct device *dev)
713 * Read the config data for a PCI device, sanity-check it
714 * and fill in the dev structure...
716 static struct pci_dev * __devinit
717 pci_scan_device(struct pci_bus *bus, int devfn)
724 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
727 /* some broken boards return 0 or ~0 if a slot is empty: */
728 if (l == 0xffffffff || l == 0x00000000 ||
729 l == 0x0000ffff || l == 0xffff0000)
732 /* Configuration request Retry Status */
733 while (l == 0xffff0001) {
736 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
738 /* Card hasn't responded in 60 seconds? Must be stuck. */
739 if (delay > 60 * 1000) {
740 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
741 "responding\n", pci_domain_nr(bus),
742 bus->number, PCI_SLOT(devfn),
748 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
751 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
755 memset(dev, 0, sizeof(struct pci_dev));
757 dev->sysdata = bus->sysdata;
758 dev->dev.parent = bus->bridge;
759 dev->dev.bus = &pci_bus_type;
761 dev->hdr_type = hdr_type & 0x7f;
762 dev->multifunction = !!(hdr_type & 0x80);
763 dev->vendor = l & 0xffff;
764 dev->device = (l >> 16) & 0xffff;
765 dev->cfg_size = pci_cfg_space_size(dev);
767 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
768 set this higher, assuming the system even supports it. */
769 dev->dma_mask = 0xffffffff;
770 if (pci_setup_device(dev) < 0) {
778 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
780 device_initialize(&dev->dev);
781 dev->dev.release = pci_release_dev;
784 dev->dev.dma_mask = &dev->dma_mask;
785 dev->dev.coherent_dma_mask = 0xffffffffull;
787 /* Fix up broken headers */
788 pci_fixup_device(pci_fixup_header, dev);
791 * Add the device to our list of discovered devices
792 * and the bus list for fixup functions, etc.
794 INIT_LIST_HEAD(&dev->global_list);
795 spin_lock(&pci_bus_lock);
796 list_add_tail(&dev->bus_list, &bus->devices);
797 spin_unlock(&pci_bus_lock);
800 struct pci_dev * __devinit
801 pci_scan_single_device(struct pci_bus *bus, int devfn)
805 dev = pci_scan_device(bus, devfn);
809 pci_device_add(dev, bus);
810 pci_scan_msi_device(dev);
816 * pci_scan_slot - scan a PCI slot on a bus for devices.
817 * @bus: PCI bus to scan
818 * @devfn: slot number to scan (must have zero function.)
820 * Scan a PCI slot on the specified PCI bus for devices, adding
821 * discovered devices to the @bus->devices list. New devices
822 * will have an empty dev->global_list head.
824 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
829 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
831 for (func = 0; func < 8; func++, devfn++) {
834 dev = pci_scan_single_device(bus, devfn);
839 * If this is a single function device,
840 * don't scan past the first function.
842 if (!dev->multifunction) {
844 dev->multifunction = 1;
850 if (func == 0 && !scan_all_fns)
857 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
859 unsigned int devfn, pass, max = bus->secondary;
862 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
864 /* Go find them, Rover! */
865 for (devfn = 0; devfn < 0x100; devfn += 8)
866 pci_scan_slot(bus, devfn);
869 * After performing arch-dependent fixup of the bus, look behind
870 * all PCI-to-PCI bridges on this bus.
872 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
873 pcibios_fixup_bus(bus);
874 for (pass=0; pass < 2; pass++)
875 list_for_each_entry(dev, &bus->devices, bus_list) {
876 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
877 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
878 max = pci_scan_bridge(bus, dev, max, pass);
882 * We've scanned the bus and so we know all about what's on
883 * the other side of any bridges that may be on this bus plus
886 * Return how far we've got finding sub-buses.
888 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
889 pci_domain_nr(bus), bus->number, max);
893 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
897 max = pci_scan_child_bus(bus);
900 * Make the discovered devices available.
902 pci_bus_add_devices(bus);
907 struct pci_bus * __devinit pci_create_bus(struct device *parent,
908 int bus, struct pci_ops *ops, void *sysdata)
918 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
924 b->sysdata = sysdata;
927 if (pci_find_bus(pci_domain_nr(b), bus)) {
928 /* If we already got to this bus through a different bridge, ignore it */
929 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
932 spin_lock(&pci_bus_lock);
933 list_add_tail(&b->node, &pci_root_buses);
934 spin_unlock(&pci_bus_lock);
936 memset(dev, 0, sizeof(*dev));
937 dev->parent = parent;
938 dev->release = pci_release_bus_bridge_dev;
939 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
940 error = device_register(dev);
943 b->bridge = get_device(dev);
945 b->class_dev.class = &pcibus_class;
946 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
947 error = class_device_register(&b->class_dev);
949 goto class_dev_reg_err;
950 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
952 goto class_dev_create_file_err;
954 /* Create legacy_io and legacy_mem files for this bus */
955 pci_create_legacy_files(b);
957 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
959 goto sys_create_link_err;
961 b->number = b->secondary = bus;
962 b->resource[0] = &ioport_resource;
963 b->resource[1] = &iomem_resource;
968 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
969 class_dev_create_file_err:
970 class_device_unregister(&b->class_dev);
972 device_unregister(dev);
974 spin_lock(&pci_bus_lock);
976 spin_unlock(&pci_bus_lock);
982 EXPORT_SYMBOL_GPL(pci_create_bus);
984 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
985 int bus, struct pci_ops *ops, void *sysdata)
989 b = pci_create_bus(parent, bus, ops, sysdata);
991 b->subordinate = pci_scan_child_bus(b);
994 EXPORT_SYMBOL(pci_scan_bus_parented);
996 #ifdef CONFIG_HOTPLUG
997 EXPORT_SYMBOL(pci_add_new_bus);
998 EXPORT_SYMBOL(pci_do_scan_bus);
999 EXPORT_SYMBOL(pci_scan_slot);
1000 EXPORT_SYMBOL(pci_scan_bridge);
1001 EXPORT_SYMBOL(pci_scan_single_device);
1002 EXPORT_SYMBOL_GPL(pci_scan_child_bus);