1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci_hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/cpumask.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/hypervisor.h>
19 #include <linux/irqdomain.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/bitfield.h>
24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25 #define CARDBUS_RESERVE_BUSNR 3
27 static struct resource busn_resource = {
31 .flags = IORESOURCE_BUS,
34 /* Ugh. Need to stop exporting this to modules. */
35 LIST_HEAD(pci_root_buses);
36 EXPORT_SYMBOL(pci_root_buses);
38 static LIST_HEAD(pci_domain_busn_res_list);
40 struct pci_domain_busn_res {
41 struct list_head list;
46 static struct resource *get_pci_domain_busn_res(int domain_nr)
48 struct pci_domain_busn_res *r;
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
58 r->domain_nr = domain_nr;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
69 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
71 * is no device to be found on the pci_bus_type.
73 int no_pci_devices(void)
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
83 EXPORT_SYMBOL(no_pci_devices);
88 static void release_pcibus_dev(struct device *dev)
90 struct pci_bus *pci_bus = to_pci_bus(dev);
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
98 static struct class pcibus_class = {
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
104 static int __init pcibus_class_init(void)
106 return class_register(&pcibus_class);
108 postcore_initcall(pcibus_class_init);
110 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112 u64 size = mask & maxbase; /* Find the significant bits */
117 * Get the lowest of them to find the decode size, and from that
120 size = size & ~(size-1);
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153 /* 1M mem BAR treated as 32-bit BAR */
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
159 /* mem unknown type treated as 32-bit BAR */
165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
168 * __pci_read_base - Read a PCI BAR
169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
182 struct pci_bus_region region, inverted_region;
184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186 /* No printks while decoding is disabled! */
187 if (!dev->mmio_always_on) {
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
190 pci_write_config_word(dev, PCI_COMMAND,
191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
195 res->name = pci_name(dev);
197 pci_read_config_dword(dev, pos, &l);
198 pci_write_config_dword(dev, pos, l | mask);
199 pci_read_config_dword(dev, pos, &sz);
200 pci_write_config_dword(dev, pos, l);
203 * All bits set in sz means the device isn't working properly.
204 * If the BAR isn't implemented, all bits must be 0. If it's a
205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
208 if (PCI_POSSIBLE_ERROR(sz))
212 * I don't know how l can have all bits set. Copied from old code.
213 * Maybe it fixes a bug on some ancient platform.
215 if (PCI_POSSIBLE_ERROR(l))
218 if (type == pci_bar_unknown) {
219 res->flags = decode_bar(dev, l);
220 res->flags |= IORESOURCE_SIZEALIGN;
221 if (res->flags & IORESOURCE_IO) {
222 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
231 if (l & PCI_ROM_ADDRESS_ENABLE)
232 res->flags |= IORESOURCE_ROM_ENABLE;
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = PCI_ROM_ADDRESS_MASK;
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
255 sz64 = pci_size(l64, sz64, mask64);
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
285 region.end = l64 + sz64 - 1;
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
296 * resource_to_bus(bus_to_resource(A)) == A
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
304 res->end = region.end - region.start;
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323 unsigned int pos, reg;
325 if (dev->non_compliant_bars)
328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
347 static void pci_read_bridge_windows(struct pci_dev *bridge)
352 pci_read_config_word(bridge, PCI_IO_BASE, &io);
354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355 pci_read_config_word(bridge, PCI_IO_BASE, &io);
356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
359 bridge->io_window = 1;
362 * DECchip 21050 pass 2 errata: the bridge may miss an address
363 * disconnect boundary by one PCI data phase. Workaround: do not
364 * use prefetching on this device.
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
379 bridge->pref_window = 1;
381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
384 * Bridge claims to have a 64-bit prefetchable memory
385 * window; verify that the upper bits are actually
388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
394 bridge->pref_64_window = 1;
398 static void pci_read_bridge_io(struct pci_bus *child)
400 struct pci_dev *dev = child->self;
401 u8 io_base_lo, io_limit_lo;
402 unsigned long io_mask, io_granularity, base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
406 io_mask = PCI_IO_RANGE_MASK;
407 io_granularity = 0x1000;
408 if (dev->io_window_1k) {
409 /* Support 1K I/O space granularity */
410 io_mask = PCI_IO_1K_RANGE_MASK;
411 io_granularity = 0x400;
414 res = child->resource[0];
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
417 base = (io_base_lo & io_mask) << 8;
418 limit = (io_limit_lo & io_mask) << 8;
420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
421 u16 io_base_hi, io_limit_hi;
423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
425 base |= ((unsigned long) io_base_hi << 16);
426 limit |= ((unsigned long) io_limit_hi << 16);
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
432 region.end = limit + io_granularity - 1;
433 pcibios_bus_to_resource(dev->bus, res, ®ion);
434 pci_info(dev, " bridge window %pR\n", res);
438 static void pci_read_bridge_mmio(struct pci_bus *child)
440 struct pci_dev *dev = child->self;
441 u16 mem_base_lo, mem_limit_lo;
442 unsigned long base, limit;
443 struct pci_bus_region region;
444 struct resource *res;
446 res = child->resource[1];
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
454 region.end = limit + 0xfffff;
455 pcibios_bus_to_resource(dev->bus, res, ®ion);
456 pci_info(dev, " bridge window %pR\n", res);
460 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462 struct pci_dev *dev = child->self;
463 u16 mem_base_lo, mem_limit_lo;
465 pci_bus_addr_t base, limit;
466 struct pci_bus_region region;
467 struct resource *res;
469 res = child->resource[2];
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
476 u32 mem_base_hi, mem_limit_hi;
478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
482 * Some bridges set the base > limit by default, and some
483 * (broken) BIOSes do not initialize them. If we find
484 * this, just assume they are not being used.
486 if (mem_base_hi <= mem_limit_hi) {
487 base64 |= (u64) mem_base_hi << 32;
488 limit64 |= (u64) mem_limit_hi << 32;
492 base = (pci_bus_addr_t) base64;
493 limit = (pci_bus_addr_t) limit64;
495 if (base != base64) {
496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
497 (unsigned long long) base64);
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
503 IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (res->flags & PCI_PREF_RANGE_TYPE_64)
505 res->flags |= IORESOURCE_MEM_64;
507 region.end = limit + 0xfffff;
508 pcibios_bus_to_resource(dev->bus, res, ®ion);
509 pci_info(dev, " bridge window %pR\n", res);
513 void pci_read_bridge_bases(struct pci_bus *child)
515 struct pci_dev *dev = child->self;
516 struct resource *res;
519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
522 pci_info(dev, "PCI bridge to %pR%s\n",
524 dev->transparent ? " (subtractive decode)" : "");
526 pci_bus_remove_resources(child);
527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530 pci_read_bridge_io(child);
531 pci_read_bridge_mmio(child);
532 pci_read_bridge_mmio_pref(child);
534 if (dev->transparent) {
535 pci_bus_for_each_resource(child->parent, res) {
536 if (res && res->flags) {
537 pci_bus_add_resource(child, res,
538 PCI_SUBTRACTIVE_DECODE);
539 pci_info(dev, " bridge window %pR (subtractive decode)\n",
546 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
550 b = kzalloc(sizeof(*b), GFP_KERNEL);
554 INIT_LIST_HEAD(&b->node);
555 INIT_LIST_HEAD(&b->children);
556 INIT_LIST_HEAD(&b->devices);
557 INIT_LIST_HEAD(&b->slots);
558 INIT_LIST_HEAD(&b->resources);
559 b->max_bus_speed = PCI_SPEED_UNKNOWN;
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
561 #ifdef CONFIG_PCI_DOMAINS_GENERIC
563 b->domain_nr = parent->domain_nr;
568 static void pci_release_host_bridge_dev(struct device *dev)
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572 if (bridge->release_fn)
573 bridge->release_fn(bridge);
575 pci_free_resource_list(&bridge->windows);
576 pci_free_resource_list(&bridge->dma_ranges);
580 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
582 INIT_LIST_HEAD(&bridge->windows);
583 INIT_LIST_HEAD(&bridge->dma_ranges);
586 * We assume we can manage these PCIe features. Some systems may
587 * reserve these for use by the platform itself, e.g., an ACPI BIOS
588 * may implement its own AER handling and use _OSC to prevent the
589 * OS from interfering.
591 bridge->native_aer = 1;
592 bridge->native_pcie_hotplug = 1;
593 bridge->native_shpc_hotplug = 1;
594 bridge->native_pme = 1;
595 bridge->native_ltr = 1;
596 bridge->native_dpc = 1;
597 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
598 bridge->native_cxl_error = 1;
600 device_initialize(&bridge->dev);
603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
605 struct pci_host_bridge *bridge;
607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
611 pci_init_host_bridge(bridge);
612 bridge->dev.release = pci_release_host_bridge_dev;
616 EXPORT_SYMBOL(pci_alloc_host_bridge);
618 static void devm_pci_alloc_host_bridge_release(void *data)
620 pci_free_host_bridge(data);
623 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
627 struct pci_host_bridge *bridge;
629 bridge = pci_alloc_host_bridge(priv);
633 bridge->dev.parent = dev;
635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
640 ret = devm_of_pci_bridge_init(dev, bridge);
646 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
648 void pci_free_host_bridge(struct pci_host_bridge *bridge)
650 put_device(&bridge->dev);
652 EXPORT_SYMBOL(pci_free_host_bridge);
654 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
655 static const unsigned char pcix_bus_speed[] = {
656 PCI_SPEED_UNKNOWN, /* 0 */
657 PCI_SPEED_66MHz_PCIX, /* 1 */
658 PCI_SPEED_100MHz_PCIX, /* 2 */
659 PCI_SPEED_133MHz_PCIX, /* 3 */
660 PCI_SPEED_UNKNOWN, /* 4 */
661 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
662 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
663 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
664 PCI_SPEED_UNKNOWN, /* 8 */
665 PCI_SPEED_66MHz_PCIX_266, /* 9 */
666 PCI_SPEED_100MHz_PCIX_266, /* A */
667 PCI_SPEED_133MHz_PCIX_266, /* B */
668 PCI_SPEED_UNKNOWN, /* C */
669 PCI_SPEED_66MHz_PCIX_533, /* D */
670 PCI_SPEED_100MHz_PCIX_533, /* E */
671 PCI_SPEED_133MHz_PCIX_533 /* F */
674 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
675 const unsigned char pcie_link_speed[] = {
676 PCI_SPEED_UNKNOWN, /* 0 */
677 PCIE_SPEED_2_5GT, /* 1 */
678 PCIE_SPEED_5_0GT, /* 2 */
679 PCIE_SPEED_8_0GT, /* 3 */
680 PCIE_SPEED_16_0GT, /* 4 */
681 PCIE_SPEED_32_0GT, /* 5 */
682 PCIE_SPEED_64_0GT, /* 6 */
683 PCI_SPEED_UNKNOWN, /* 7 */
684 PCI_SPEED_UNKNOWN, /* 8 */
685 PCI_SPEED_UNKNOWN, /* 9 */
686 PCI_SPEED_UNKNOWN, /* A */
687 PCI_SPEED_UNKNOWN, /* B */
688 PCI_SPEED_UNKNOWN, /* C */
689 PCI_SPEED_UNKNOWN, /* D */
690 PCI_SPEED_UNKNOWN, /* E */
691 PCI_SPEED_UNKNOWN /* F */
693 EXPORT_SYMBOL_GPL(pcie_link_speed);
695 const char *pci_speed_string(enum pci_bus_speed speed)
697 /* Indexed by the pci_bus_speed enum */
698 static const char *speed_strings[] = {
699 "33 MHz PCI", /* 0x00 */
700 "66 MHz PCI", /* 0x01 */
701 "66 MHz PCI-X", /* 0x02 */
702 "100 MHz PCI-X", /* 0x03 */
703 "133 MHz PCI-X", /* 0x04 */
708 "66 MHz PCI-X 266", /* 0x09 */
709 "100 MHz PCI-X 266", /* 0x0a */
710 "133 MHz PCI-X 266", /* 0x0b */
711 "Unknown AGP", /* 0x0c */
716 "66 MHz PCI-X 533", /* 0x11 */
717 "100 MHz PCI-X 533", /* 0x12 */
718 "133 MHz PCI-X 533", /* 0x13 */
719 "2.5 GT/s PCIe", /* 0x14 */
720 "5.0 GT/s PCIe", /* 0x15 */
721 "8.0 GT/s PCIe", /* 0x16 */
722 "16.0 GT/s PCIe", /* 0x17 */
723 "32.0 GT/s PCIe", /* 0x18 */
724 "64.0 GT/s PCIe", /* 0x19 */
727 if (speed < ARRAY_SIZE(speed_strings))
728 return speed_strings[speed];
731 EXPORT_SYMBOL_GPL(pci_speed_string);
733 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
737 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
739 static unsigned char agp_speeds[] = {
747 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
753 else if (agpstat & 2)
755 else if (agpstat & 1)
767 return agp_speeds[index];
770 static void pci_set_bus_speed(struct pci_bus *bus)
772 struct pci_dev *bridge = bus->self;
775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
777 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
781 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
784 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
788 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
791 enum pci_bus_speed max;
793 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
796 if (status & PCI_X_SSTATUS_533MHZ) {
797 max = PCI_SPEED_133MHz_PCIX_533;
798 } else if (status & PCI_X_SSTATUS_266MHZ) {
799 max = PCI_SPEED_133MHz_PCIX_266;
800 } else if (status & PCI_X_SSTATUS_133MHZ) {
801 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
802 max = PCI_SPEED_133MHz_PCIX_ECC;
804 max = PCI_SPEED_133MHz_PCIX;
806 max = PCI_SPEED_66MHz_PCIX;
809 bus->max_bus_speed = max;
810 bus->cur_bus_speed = pcix_bus_speed[
811 (status & PCI_X_SSTATUS_FREQ) >> 6];
816 if (pci_is_pcie(bridge)) {
820 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
823 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
824 pcie_update_link_speed(bus, linksta);
828 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
830 struct irq_domain *d;
832 /* If the host bridge driver sets a MSI domain of the bridge, use it */
833 d = dev_get_msi_domain(bus->bridge);
836 * Any firmware interface that can resolve the msi_domain
837 * should be called from here.
840 d = pci_host_bridge_of_msi_domain(bus);
842 d = pci_host_bridge_acpi_msi_domain(bus);
845 * If no IRQ domain was found via the OF tree, try looking it up
846 * directly through the fwnode_handle.
849 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
852 d = irq_find_matching_fwnode(fwnode,
859 static void pci_set_bus_msi_domain(struct pci_bus *bus)
861 struct irq_domain *d;
865 * The bus can be a root bus, a subordinate bus, or a virtual bus
866 * created by an SR-IOV device. Walk up to the first bridge device
867 * found or derive the domain from the host bridge.
869 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
871 d = dev_get_msi_domain(&b->self->dev);
875 d = pci_host_bridge_msi_domain(b);
877 dev_set_msi_domain(&bus->dev, d);
880 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
882 struct device *parent = bridge->dev.parent;
883 struct resource_entry *window, *next, *n;
884 struct pci_bus *bus, *b;
885 resource_size_t offset, next_offset;
886 LIST_HEAD(resources);
887 struct resource *res, *next_res;
892 bus = pci_alloc_bus(NULL);
898 bus->sysdata = bridge->sysdata;
899 bus->ops = bridge->ops;
900 bus->number = bus->busn_res.start = bridge->busnr;
901 #ifdef CONFIG_PCI_DOMAINS_GENERIC
902 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
903 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
905 bus->domain_nr = bridge->domain_nr;
906 if (bus->domain_nr < 0) {
907 err = bus->domain_nr;
912 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
914 /* Ignore it if we already got here via a different bridge */
915 dev_dbg(&b->dev, "bus already known\n");
920 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
923 err = pcibios_root_bridge_prepare(bridge);
927 /* Temporarily move resources off the list */
928 list_splice_init(&bridge->windows, &resources);
929 err = device_add(&bridge->dev);
931 put_device(&bridge->dev);
934 bus->bridge = get_device(&bridge->dev);
935 device_enable_async_suspend(bus->bridge);
936 pci_set_bus_of_node(bus);
937 pci_set_bus_msi_domain(bus);
938 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
939 !pci_host_of_has_msi_map(parent))
940 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
943 set_dev_node(bus->bridge, pcibus_to_node(bus));
945 bus->dev.class = &pcibus_class;
946 bus->dev.parent = bus->bridge;
948 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
949 name = dev_name(&bus->dev);
951 err = device_register(&bus->dev);
955 pcibios_add_bus(bus);
957 if (bus->ops->add_bus) {
958 err = bus->ops->add_bus(bus);
959 if (WARN_ON(err < 0))
960 dev_err(&bus->dev, "failed to add bus: %d\n", err);
963 /* Create legacy_io and legacy_mem files for this bus */
964 pci_create_legacy_files(bus);
967 dev_info(parent, "PCI host bridge to bus %s\n", name);
969 pr_info("PCI host bridge to bus %s\n", name);
971 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
972 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
974 /* Coalesce contiguous windows */
975 resource_list_for_each_entry_safe(window, n, &resources) {
976 if (list_is_last(&window->node, &resources))
979 next = list_next_entry(window, node);
980 offset = window->offset;
982 next_offset = next->offset;
983 next_res = next->res;
985 if (res->flags != next_res->flags || offset != next_offset)
988 if (res->end + 1 == next_res->start) {
989 next_res->start = res->start;
990 res->flags = res->start = res->end = 0;
994 /* Add initial resources to the bus */
995 resource_list_for_each_entry_safe(window, n, &resources) {
996 offset = window->offset;
998 if (!res->flags && !res->start && !res->end) {
999 release_resource(res);
1003 list_move_tail(&window->node, &bridge->windows);
1005 if (res->flags & IORESOURCE_BUS)
1006 pci_bus_insert_busn_res(bus, bus->number, res->end);
1008 pci_bus_add_resource(bus, res, 0);
1011 if (resource_type(res) == IORESOURCE_IO)
1012 fmt = " (bus address [%#06llx-%#06llx])";
1014 fmt = " (bus address [%#010llx-%#010llx])";
1016 snprintf(addr, sizeof(addr), fmt,
1017 (unsigned long long)(res->start - offset),
1018 (unsigned long long)(res->end - offset));
1022 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1025 down_write(&pci_bus_sem);
1026 list_add_tail(&bus->node, &pci_root_buses);
1027 up_write(&pci_bus_sem);
1032 put_device(&bridge->dev);
1033 device_del(&bridge->dev);
1036 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1037 pci_bus_release_domain_nr(bus, parent);
1043 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1049 * If extended config space isn't accessible on a bridge's primary
1050 * bus, we certainly can't access it on the secondary bus.
1052 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1056 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1057 * extended config space is accessible on the primary, it's also
1058 * accessible on the secondary.
1060 if (pci_is_pcie(bridge) &&
1061 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1062 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1063 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1067 * For the other bridge types:
1068 * - PCI-to-PCI bridges
1069 * - PCIe-to-PCI/PCI-X forward bridges
1070 * - PCI/PCI-X-to-PCIe reverse bridges
1071 * extended config space on the secondary side is only accessible
1072 * if the bridge supports PCI-X Mode 2.
1074 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1078 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1079 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1082 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1083 struct pci_dev *bridge, int busnr)
1085 struct pci_bus *child;
1086 struct pci_host_bridge *host;
1090 /* Allocate a new bus and inherit stuff from the parent */
1091 child = pci_alloc_bus(parent);
1095 child->parent = parent;
1096 child->sysdata = parent->sysdata;
1097 child->bus_flags = parent->bus_flags;
1099 host = pci_find_host_bridge(parent);
1100 if (host->child_ops)
1101 child->ops = host->child_ops;
1103 child->ops = parent->ops;
1106 * Initialize some portions of the bus device, but don't register
1107 * it now as the parent is not properly set up yet.
1109 child->dev.class = &pcibus_class;
1110 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1112 /* Set up the primary, secondary and subordinate bus numbers */
1113 child->number = child->busn_res.start = busnr;
1114 child->primary = parent->busn_res.start;
1115 child->busn_res.end = 0xff;
1118 child->dev.parent = parent->bridge;
1122 child->self = bridge;
1123 child->bridge = get_device(&bridge->dev);
1124 child->dev.parent = child->bridge;
1125 pci_set_bus_of_node(child);
1126 pci_set_bus_speed(child);
1129 * Check whether extended config space is accessible on the child
1130 * bus. Note that we currently assume it is always accessible on
1133 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1134 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1135 pci_info(child, "extended config space not accessible\n");
1138 /* Set up default resource pointers and names */
1139 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1140 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1141 child->resource[i]->name = child->name;
1143 bridge->subordinate = child;
1146 pci_set_bus_msi_domain(child);
1147 ret = device_register(&child->dev);
1150 pcibios_add_bus(child);
1152 if (child->ops->add_bus) {
1153 ret = child->ops->add_bus(child);
1154 if (WARN_ON(ret < 0))
1155 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1158 /* Create legacy_io and legacy_mem files for this bus */
1159 pci_create_legacy_files(child);
1164 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1167 struct pci_bus *child;
1169 child = pci_alloc_child_bus(parent, dev, busnr);
1171 down_write(&pci_bus_sem);
1172 list_add_tail(&child->node, &parent->children);
1173 up_write(&pci_bus_sem);
1177 EXPORT_SYMBOL(pci_add_new_bus);
1179 static void pci_enable_crs(struct pci_dev *pdev)
1183 /* Enable CRS Software Visibility if supported */
1184 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1185 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1186 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1187 PCI_EXP_RTCTL_CRSSVE);
1190 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1191 unsigned int available_buses);
1193 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1194 * numbers from EA capability.
1196 * @sec: updated with secondary bus number from EA
1197 * @sub: updated with subordinate bus number from EA
1199 * If @dev is a bridge with EA capability that specifies valid secondary
1200 * and subordinate bus numbers, return true with the bus numbers in @sec
1201 * and @sub. Otherwise return false.
1203 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1209 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1212 /* find PCI EA capability in list */
1213 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1217 offset = ea + PCI_EA_FIRST_ENT;
1218 pci_read_config_dword(dev, offset, &dw);
1219 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1220 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1221 if (ea_sec == 0 || ea_sub < ea_sec)
1230 * pci_scan_bridge_extend() - Scan buses behind a bridge
1231 * @bus: Parent bus the bridge is on
1232 * @dev: Bridge itself
1233 * @max: Starting subordinate number of buses behind this bridge
1234 * @available_buses: Total number of buses available for this bridge and
1235 * the devices below. After the minimal bus space has
1236 * been allocated the remaining buses will be
1237 * distributed equally between hotplug-capable bridges.
1238 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1239 * that need to be reconfigured.
1241 * If it's a bridge, configure it and scan the bus behind it.
1242 * For CardBus bridges, we don't scan behind as the devices will
1243 * be handled by the bridge driver itself.
1245 * We need to process bridges in two passes -- first we scan those
1246 * already configured by the BIOS and after we are done with all of
1247 * them, we proceed to assigning numbers to the remaining buses in
1248 * order to avoid overlaps between old and new bus numbers.
1250 * Return: New subordinate number covering all buses behind this bridge.
1252 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1253 int max, unsigned int available_buses,
1256 struct pci_bus *child;
1257 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1258 u32 buses, i, j = 0;
1260 u8 primary, secondary, subordinate;
1263 u8 fixed_sec, fixed_sub;
1267 * Make sure the bridge is powered on to be able to access config
1268 * space of devices below it.
1270 pm_runtime_get_sync(&dev->dev);
1272 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1273 primary = buses & 0xFF;
1274 secondary = (buses >> 8) & 0xFF;
1275 subordinate = (buses >> 16) & 0xFF;
1277 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1278 secondary, subordinate, pass);
1280 if (!primary && (primary != bus->number) && secondary && subordinate) {
1281 pci_warn(dev, "Primary bus is hard wired to 0\n");
1282 primary = bus->number;
1285 /* Check if setup is sensible at all */
1287 (primary != bus->number || secondary <= bus->number ||
1288 secondary > subordinate)) {
1289 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1290 secondary, subordinate);
1295 * Disable Master-Abort Mode during probing to avoid reporting of
1296 * bus errors in some architectures.
1298 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1299 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1300 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1302 pci_enable_crs(dev);
1304 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1305 !is_cardbus && !broken) {
1306 unsigned int cmax, buses;
1309 * Bus already configured by firmware, process it in the
1310 * first pass and just note the configuration.
1316 * The bus might already exist for two reasons: Either we
1317 * are rescanning the bus or the bus is reachable through
1318 * more than one bridge. The second case can happen with
1319 * the i450NX chipset.
1321 child = pci_find_bus(pci_domain_nr(bus), secondary);
1323 child = pci_add_new_bus(bus, dev, secondary);
1326 child->primary = primary;
1327 pci_bus_insert_busn_res(child, secondary, subordinate);
1328 child->bridge_ctl = bctl;
1331 buses = subordinate - secondary;
1332 cmax = pci_scan_child_bus_extend(child, buses);
1333 if (cmax > subordinate)
1334 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1337 /* Subordinate should equal child->busn_res.end */
1338 if (subordinate > max)
1343 * We need to assign a number to this bus which we always
1344 * do in the second pass.
1347 if (pcibios_assign_all_busses() || broken || is_cardbus)
1350 * Temporarily disable forwarding of the
1351 * configuration cycles on all bridges in
1352 * this bus segment to avoid possible
1353 * conflicts in the second pass between two
1354 * bridges programmed with overlapping bus
1357 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1363 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1365 /* Read bus numbers from EA Capability (if present) */
1366 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1368 next_busnr = fixed_sec;
1370 next_busnr = max + 1;
1373 * Prevent assigning a bus number that already exists.
1374 * This can happen when a bridge is hot-plugged, so in this
1375 * case we only re-scan this bus.
1377 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1379 child = pci_add_new_bus(bus, dev, next_busnr);
1382 pci_bus_insert_busn_res(child, next_busnr,
1386 if (available_buses)
1389 buses = (buses & 0xff000000)
1390 | ((unsigned int)(child->primary) << 0)
1391 | ((unsigned int)(child->busn_res.start) << 8)
1392 | ((unsigned int)(child->busn_res.end) << 16);
1395 * yenta.c forces a secondary latency timer of 176.
1396 * Copy that behaviour here.
1399 buses &= ~0xff000000;
1400 buses |= CARDBUS_LATENCY_TIMER << 24;
1403 /* We need to blast all three values with a single write */
1404 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1407 child->bridge_ctl = bctl;
1408 max = pci_scan_child_bus_extend(child, available_buses);
1412 * For CardBus bridges, we leave 4 bus numbers as
1413 * cards with a PCI-to-PCI bridge can be inserted
1416 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1417 struct pci_bus *parent = bus;
1418 if (pci_find_bus(pci_domain_nr(bus),
1421 while (parent->parent) {
1422 if ((!pcibios_assign_all_busses()) &&
1423 (parent->busn_res.end > max) &&
1424 (parent->busn_res.end <= max+i)) {
1427 parent = parent->parent;
1432 * Often, there are two CardBus
1433 * bridges -- try to leave one
1434 * valid bus number for each one.
1444 * Set subordinate bus number to its real value.
1445 * If fixed subordinate bus number exists from EA
1446 * capability then use it.
1450 pci_bus_update_busn_res_end(child, max);
1451 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1454 sprintf(child->name,
1455 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1456 pci_domain_nr(bus), child->number);
1458 /* Check that all devices are accessible */
1459 while (bus->parent) {
1460 if ((child->busn_res.end > bus->busn_res.end) ||
1461 (child->number > bus->busn_res.end) ||
1462 (child->number < bus->number) ||
1463 (child->busn_res.end < bus->number)) {
1464 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1472 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1474 pm_runtime_put(&dev->dev);
1480 * pci_scan_bridge() - Scan buses behind a bridge
1481 * @bus: Parent bus the bridge is on
1482 * @dev: Bridge itself
1483 * @max: Starting subordinate number of buses behind this bridge
1484 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1485 * that need to be reconfigured.
1487 * If it's a bridge, configure it and scan the bus behind it.
1488 * For CardBus bridges, we don't scan behind as the devices will
1489 * be handled by the bridge driver itself.
1491 * We need to process bridges in two passes -- first we scan those
1492 * already configured by the BIOS and after we are done with all of
1493 * them, we proceed to assigning numbers to the remaining buses in
1494 * order to avoid overlaps between old and new bus numbers.
1496 * Return: New subordinate number covering all buses behind this bridge.
1498 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1500 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1502 EXPORT_SYMBOL(pci_scan_bridge);
1505 * Read interrupt line and base address registers.
1506 * The architecture-dependent code can tweak these, of course.
1508 static void pci_read_irq(struct pci_dev *dev)
1512 /* VFs are not allowed to use INTx, so skip the config reads */
1513 if (dev->is_virtfn) {
1519 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1522 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1526 void set_pcie_port_type(struct pci_dev *pdev)
1532 struct pci_dev *parent;
1534 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1538 pdev->pcie_cap = pos;
1539 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1540 pdev->pcie_flags_reg = reg16;
1541 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1542 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1544 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
1545 if (reg32 & PCI_EXP_LNKCAP_DLLLARC)
1546 pdev->link_active_reporting = 1;
1548 parent = pci_upstream_bridge(pdev);
1553 * Some systems do not identify their upstream/downstream ports
1554 * correctly so detect impossible configurations here and correct
1555 * the port type accordingly.
1557 type = pci_pcie_type(pdev);
1558 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1560 * If pdev claims to be downstream port but the parent
1561 * device is also downstream port assume pdev is actually
1564 if (pcie_downstream_port(parent)) {
1565 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1566 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1567 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1569 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1571 * If pdev claims to be upstream port but the parent
1572 * device is also upstream port assume pdev is actually
1575 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1576 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1577 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1578 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1583 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1587 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1588 if (reg32 & PCI_EXP_SLTCAP_HPC)
1589 pdev->is_hotplug_bridge = 1;
1592 static void set_pcie_thunderbolt(struct pci_dev *dev)
1596 /* Is the device part of a Thunderbolt controller? */
1597 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1599 dev->is_thunderbolt = 1;
1602 static void set_pcie_untrusted(struct pci_dev *dev)
1604 struct pci_dev *parent;
1607 * If the upstream bridge is untrusted we treat this device
1608 * untrusted as well.
1610 parent = pci_upstream_bridge(dev);
1611 if (parent && (parent->untrusted || parent->external_facing))
1612 dev->untrusted = true;
1615 static void pci_set_removable(struct pci_dev *dev)
1617 struct pci_dev *parent = pci_upstream_bridge(dev);
1620 * We (only) consider everything downstream from an external_facing
1621 * device to be removable by the user. We're mainly concerned with
1622 * consumer platforms with user accessible thunderbolt ports that are
1623 * vulnerable to DMA attacks, and we expect those ports to be marked by
1624 * the firmware as external_facing. Devices in traditional hotplug
1625 * slots can technically be removed, but the expectation is that unless
1626 * the port is marked with external_facing, such devices are less
1627 * accessible to user / may not be removed by end user, and thus not
1628 * exposed as "removable" to userspace.
1631 (parent->external_facing || dev_is_removable(&parent->dev)))
1632 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1636 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1639 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1640 * when forwarding a type1 configuration request the bridge must check that
1641 * the extended register address field is zero. The bridge is not permitted
1642 * to forward the transactions and must handle it as an Unsupported Request.
1643 * Some bridges do not follow this rule and simply drop the extended register
1644 * bits, resulting in the standard config space being aliased, every 256
1645 * bytes across the entire configuration space. Test for this condition by
1646 * comparing the first dword of each potential alias to the vendor/device ID.
1648 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1649 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1651 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1653 #ifdef CONFIG_PCI_QUIRKS
1657 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1659 for (pos = PCI_CFG_SPACE_SIZE;
1660 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1661 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1673 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1676 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1677 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1678 * access it. Maybe we don't have a way to generate extended config space
1679 * accesses, or the device is behind a reverse Express bridge. So we try
1680 * reading the dword at 0x100 which must either be 0 or a valid extended
1681 * capability header.
1683 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1686 int pos = PCI_CFG_SPACE_SIZE;
1688 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1689 return PCI_CFG_SPACE_SIZE;
1690 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1691 return PCI_CFG_SPACE_SIZE;
1693 return PCI_CFG_SPACE_EXP_SIZE;
1696 int pci_cfg_space_size(struct pci_dev *dev)
1702 #ifdef CONFIG_PCI_IOV
1704 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1705 * implement a PCIe capability and therefore must implement extended
1706 * config space. We can skip the NO_EXTCFG test below and the
1707 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1708 * the fact that the SR-IOV capability on the PF resides in extended
1709 * config space and must be accessible and non-aliased to have enabled
1710 * support for this VF. This is a micro performance optimization for
1711 * systems supporting many VFs.
1714 return PCI_CFG_SPACE_EXP_SIZE;
1717 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1718 return PCI_CFG_SPACE_SIZE;
1720 class = dev->class >> 8;
1721 if (class == PCI_CLASS_BRIDGE_HOST)
1722 return pci_cfg_space_size_ext(dev);
1724 if (pci_is_pcie(dev))
1725 return pci_cfg_space_size_ext(dev);
1727 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1729 return PCI_CFG_SPACE_SIZE;
1731 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1732 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1733 return pci_cfg_space_size_ext(dev);
1735 return PCI_CFG_SPACE_SIZE;
1738 static u32 pci_class(struct pci_dev *dev)
1742 #ifdef CONFIG_PCI_IOV
1744 return dev->physfn->sriov->class;
1746 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1750 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1752 #ifdef CONFIG_PCI_IOV
1753 if (dev->is_virtfn) {
1754 *vendor = dev->physfn->sriov->subsystem_vendor;
1755 *device = dev->physfn->sriov->subsystem_device;
1759 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1760 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1763 static u8 pci_hdr_type(struct pci_dev *dev)
1767 #ifdef CONFIG_PCI_IOV
1769 return dev->physfn->sriov->hdr_type;
1771 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1775 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1778 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1781 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1782 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1784 static int pci_intx_mask_broken(struct pci_dev *dev)
1786 u16 orig, toggle, new;
1788 pci_read_config_word(dev, PCI_COMMAND, &orig);
1789 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1790 pci_write_config_word(dev, PCI_COMMAND, toggle);
1791 pci_read_config_word(dev, PCI_COMMAND, &new);
1793 pci_write_config_word(dev, PCI_COMMAND, orig);
1796 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1797 * r2.3, so strictly speaking, a device is not *broken* if it's not
1798 * writable. But we'll live with the misnomer for now.
1805 static void early_dump_pci_device(struct pci_dev *pdev)
1810 pci_info(pdev, "config space:\n");
1812 for (i = 0; i < 256; i += 4)
1813 pci_read_config_dword(pdev, i, &value[i / 4]);
1815 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1820 * pci_setup_device - Fill in class and map information of a device
1821 * @dev: the device structure to fill
1823 * Initialize the device structure with information about the device's
1824 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1825 * Called at initialisation of the PCI subsystem and by CardBus services.
1826 * Returns 0 on success and negative if unknown type of device (not normal,
1827 * bridge or CardBus).
1829 int pci_setup_device(struct pci_dev *dev)
1835 struct pci_bus_region region;
1836 struct resource *res;
1838 hdr_type = pci_hdr_type(dev);
1840 dev->sysdata = dev->bus->sysdata;
1841 dev->dev.parent = dev->bus->bridge;
1842 dev->dev.bus = &pci_bus_type;
1843 dev->hdr_type = hdr_type & 0x7f;
1844 dev->multifunction = !!(hdr_type & 0x80);
1845 dev->error_state = pci_channel_io_normal;
1846 set_pcie_port_type(dev);
1848 err = pci_set_of_node(dev);
1851 pci_set_acpi_fwnode(dev);
1853 pci_dev_assign_slot(dev);
1856 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1857 * set this higher, assuming the system even supports it.
1859 dev->dma_mask = 0xffffffff;
1861 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1862 dev->bus->number, PCI_SLOT(dev->devfn),
1863 PCI_FUNC(dev->devfn));
1865 class = pci_class(dev);
1867 dev->revision = class & 0xff;
1868 dev->class = class >> 8; /* upper 3 bytes */
1871 early_dump_pci_device(dev);
1873 /* Need to have dev->class ready */
1874 dev->cfg_size = pci_cfg_space_size(dev);
1876 /* Need to have dev->cfg_size ready */
1877 set_pcie_thunderbolt(dev);
1879 set_pcie_untrusted(dev);
1881 /* "Unknown power state" */
1882 dev->current_state = PCI_UNKNOWN;
1884 /* Early fixups, before probing the BARs */
1885 pci_fixup_device(pci_fixup_early, dev);
1887 pci_set_removable(dev);
1889 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1890 dev->vendor, dev->device, dev->hdr_type, dev->class);
1892 /* Device class may be changed after fixup */
1893 class = dev->class >> 8;
1895 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1896 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1897 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1898 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1899 cmd &= ~PCI_COMMAND_IO;
1900 cmd &= ~PCI_COMMAND_MEMORY;
1901 pci_write_config_word(dev, PCI_COMMAND, cmd);
1905 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1907 switch (dev->hdr_type) { /* header type */
1908 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1909 if (class == PCI_CLASS_BRIDGE_PCI)
1912 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1914 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1917 * Do the ugly legacy mode stuff here rather than broken chip
1918 * quirk code. Legacy mode ATA controllers have fixed
1919 * addresses. These are not always echoed in BAR0-3, and
1920 * BAR0-3 in a few cases contain junk!
1922 if (class == PCI_CLASS_STORAGE_IDE) {
1924 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1925 if ((progif & 1) == 0) {
1926 region.start = 0x1F0;
1928 res = &dev->resource[0];
1929 res->flags = LEGACY_IO_RESOURCE;
1930 pcibios_bus_to_resource(dev->bus, res, ®ion);
1931 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1933 region.start = 0x3F6;
1935 res = &dev->resource[1];
1936 res->flags = LEGACY_IO_RESOURCE;
1937 pcibios_bus_to_resource(dev->bus, res, ®ion);
1938 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1941 if ((progif & 4) == 0) {
1942 region.start = 0x170;
1944 res = &dev->resource[2];
1945 res->flags = LEGACY_IO_RESOURCE;
1946 pcibios_bus_to_resource(dev->bus, res, ®ion);
1947 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1949 region.start = 0x376;
1951 res = &dev->resource[3];
1952 res->flags = LEGACY_IO_RESOURCE;
1953 pcibios_bus_to_resource(dev->bus, res, ®ion);
1954 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1960 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1962 * The PCI-to-PCI bridge spec requires that subtractive
1963 * decoding (i.e. transparent) bridge must have programming
1964 * interface code of 0x01.
1967 dev->transparent = ((dev->class & 0xff) == 1);
1968 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1969 pci_read_bridge_windows(dev);
1970 set_pcie_hotplug_bridge(dev);
1971 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1973 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1974 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1978 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1979 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1982 pci_read_bases(dev, 1, 0);
1983 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1984 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1987 default: /* unknown header */
1988 pci_err(dev, "unknown header type %02x, ignoring device\n",
1990 pci_release_of_node(dev);
1994 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1995 dev->class, dev->hdr_type);
1996 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1999 /* We found a fine healthy device, go go go... */
2003 static void pci_configure_mps(struct pci_dev *dev)
2005 struct pci_dev *bridge = pci_upstream_bridge(dev);
2006 int mps, mpss, p_mps, rc;
2008 if (!pci_is_pcie(dev))
2011 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2016 * For Root Complex Integrated Endpoints, program the maximum
2017 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2019 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2020 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2023 mps = 128 << dev->pcie_mpss;
2024 rc = pcie_set_mps(dev, mps);
2026 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2032 if (!bridge || !pci_is_pcie(bridge))
2035 mps = pcie_get_mps(dev);
2036 p_mps = pcie_get_mps(bridge);
2041 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2042 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2043 mps, pci_name(bridge), p_mps);
2048 * Fancier MPS configuration is done later by
2049 * pcie_bus_configure_settings()
2051 if (pcie_bus_config != PCIE_BUS_DEFAULT)
2054 mpss = 128 << dev->pcie_mpss;
2055 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2056 pcie_set_mps(bridge, mpss);
2057 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2058 mpss, p_mps, 128 << bridge->pcie_mpss);
2059 p_mps = pcie_get_mps(bridge);
2062 rc = pcie_set_mps(dev, p_mps);
2064 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2069 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2073 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2075 struct pci_host_bridge *host;
2080 if (!pci_is_pcie(dev))
2083 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2087 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2090 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2094 host = pci_find_host_bridge(dev->bus);
2099 * If some device in the hierarchy doesn't handle Extended Tags
2100 * correctly, make sure they're disabled.
2102 if (host->no_ext_tags) {
2103 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2104 pci_info(dev, "disabling Extended Tags\n");
2105 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2106 PCI_EXP_DEVCTL_EXT_TAG);
2111 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2112 pci_info(dev, "enabling Extended Tags\n");
2113 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2114 PCI_EXP_DEVCTL_EXT_TAG);
2120 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2121 * @dev: PCI device to query
2123 * Returns true if the device has enabled relaxed ordering attribute.
2125 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2129 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2131 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2133 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2135 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2137 struct pci_dev *root;
2139 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */
2143 if (!pcie_relaxed_ordering_enabled(dev))
2147 * For now, we only deal with Relaxed Ordering issues with Root
2148 * Ports. Peer-to-Peer DMA is another can of worms.
2150 root = pcie_find_root_port(dev);
2154 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2155 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2156 PCI_EXP_DEVCTL_RELAX_EN);
2157 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2161 static void pci_configure_ltr(struct pci_dev *dev)
2163 #ifdef CONFIG_PCIEASPM
2164 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2165 struct pci_dev *bridge;
2168 if (!pci_is_pcie(dev))
2171 /* Read L1 PM substate capabilities */
2172 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2174 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2175 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2178 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2179 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2180 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2185 bridge = pci_upstream_bridge(dev);
2186 if (bridge && bridge->ltr_path)
2192 if (!host->native_ltr)
2196 * Software must not enable LTR in an Endpoint unless the Root
2197 * Complex and all intermediate Switches indicate support for LTR.
2198 * PCIe r4.0, sec 6.18.
2200 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2201 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2202 PCI_EXP_DEVCTL2_LTR_EN);
2208 * If we're configuring a hot-added device, LTR was likely
2209 * disabled in the upstream bridge, so re-enable it before enabling
2210 * it in the new device.
2212 bridge = pci_upstream_bridge(dev);
2213 if (bridge && bridge->ltr_path) {
2214 pci_bridge_reconfigure_ltr(dev);
2215 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2216 PCI_EXP_DEVCTL2_LTR_EN);
2222 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2224 #ifdef CONFIG_PCI_PASID
2225 struct pci_dev *bridge;
2229 if (!pci_is_pcie(dev))
2232 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2233 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2236 pcie_type = pci_pcie_type(dev);
2237 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2238 pcie_type == PCI_EXP_TYPE_RC_END)
2239 dev->eetlp_prefix_path = 1;
2241 bridge = pci_upstream_bridge(dev);
2242 if (bridge && bridge->eetlp_prefix_path)
2243 dev->eetlp_prefix_path = 1;
2248 static void pci_configure_serr(struct pci_dev *dev)
2252 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2255 * A bridge will not forward ERR_ messages coming from an
2256 * endpoint unless SERR# forwarding is enabled.
2258 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2259 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2260 control |= PCI_BRIDGE_CTL_SERR;
2261 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2266 static void pci_configure_device(struct pci_dev *dev)
2268 pci_configure_mps(dev);
2269 pci_configure_extended_tags(dev, NULL);
2270 pci_configure_relaxed_ordering(dev);
2271 pci_configure_ltr(dev);
2272 pci_configure_eetlp_prefix(dev);
2273 pci_configure_serr(dev);
2275 pci_acpi_program_hp_params(dev);
2278 static void pci_release_capabilities(struct pci_dev *dev)
2282 pci_iov_release(dev);
2283 pci_free_cap_save_buffers(dev);
2287 * pci_release_dev - Free a PCI device structure when all users of it are
2289 * @dev: device that's been disconnected
2291 * Will be called only by the device core when all users of this PCI device are
2294 static void pci_release_dev(struct device *dev)
2296 struct pci_dev *pci_dev;
2298 pci_dev = to_pci_dev(dev);
2299 pci_release_capabilities(pci_dev);
2300 pci_release_of_node(pci_dev);
2301 pcibios_release_device(pci_dev);
2302 pci_bus_put(pci_dev->bus);
2303 kfree(pci_dev->driver_override);
2304 bitmap_free(pci_dev->dma_alias_mask);
2305 dev_dbg(dev, "device released\n");
2309 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2311 struct pci_dev *dev;
2313 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2317 INIT_LIST_HEAD(&dev->bus_list);
2318 dev->dev.type = &pci_dev_type;
2319 dev->bus = pci_bus_get(bus);
2320 dev->driver_exclusive_resource = (struct resource) {
2321 .name = "PCI Exclusive",
2326 spin_lock_init(&dev->pcie_cap_lock);
2327 #ifdef CONFIG_PCI_MSI
2328 raw_spin_lock_init(&dev->msi_lock);
2332 EXPORT_SYMBOL(pci_alloc_dev);
2334 static bool pci_bus_crs_vendor_id(u32 l)
2336 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
2339 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2344 if (!pci_bus_crs_vendor_id(*l))
2345 return true; /* not a CRS completion */
2348 return false; /* CRS, but caller doesn't want to wait */
2351 * We got the reserved Vendor ID that indicates a completion with
2352 * Configuration Request Retry Status (CRS). Retry until we get a
2353 * valid Vendor ID or we time out.
2355 while (pci_bus_crs_vendor_id(*l)) {
2356 if (delay > timeout) {
2357 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2358 pci_domain_nr(bus), bus->number,
2359 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2364 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2365 pci_domain_nr(bus), bus->number,
2366 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2371 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2376 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2377 pci_domain_nr(bus), bus->number,
2378 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2383 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2386 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2389 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2390 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2391 *l == 0x0000ffff || *l == 0xffff0000)
2394 if (pci_bus_crs_vendor_id(*l))
2395 return pci_bus_wait_crs(bus, devfn, l, timeout);
2400 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2403 #ifdef CONFIG_PCI_QUIRKS
2404 struct pci_dev *bridge = bus->self;
2407 * Certain IDT switches have an issue where they improperly trigger
2408 * ACS Source Validation errors on completions for config reads.
2410 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2411 bridge->device == 0x80b5)
2412 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2415 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2417 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2420 * Read the config data for a PCI device, sanity-check it,
2421 * and fill in the dev structure.
2423 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2425 struct pci_dev *dev;
2428 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2431 dev = pci_alloc_dev(bus);
2436 dev->vendor = l & 0xffff;
2437 dev->device = (l >> 16) & 0xffff;
2439 if (pci_setup_device(dev)) {
2440 pci_bus_put(dev->bus);
2448 void pcie_report_downtraining(struct pci_dev *dev)
2450 if (!pci_is_pcie(dev))
2453 /* Look from the device up to avoid downstream ports with no devices */
2454 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2455 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2456 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2459 /* Multi-function PCIe devices share the same link/status */
2460 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2463 /* Print link status only if the device is constrained by the fabric */
2464 __pcie_print_link_status(dev, false);
2467 static void pci_init_capabilities(struct pci_dev *dev)
2469 pci_ea_init(dev); /* Enhanced Allocation */
2470 pci_msi_init(dev); /* Disable MSI */
2471 pci_msix_init(dev); /* Disable MSI-X */
2473 /* Buffers for saving PCIe and PCI-X capabilities */
2474 pci_allocate_cap_save_buffers(dev);
2476 pci_pm_init(dev); /* Power Management */
2477 pci_vpd_init(dev); /* Vital Product Data */
2478 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2479 pci_iov_init(dev); /* Single Root I/O Virtualization */
2480 pci_ats_init(dev); /* Address Translation Services */
2481 pci_pri_init(dev); /* Page Request Interface */
2482 pci_pasid_init(dev); /* Process Address Space ID */
2483 pci_acs_init(dev); /* Access Control Services */
2484 pci_ptm_init(dev); /* Precision Time Measurement */
2485 pci_aer_init(dev); /* Advanced Error Reporting */
2486 pci_dpc_init(dev); /* Downstream Port Containment */
2487 pci_rcec_init(dev); /* Root Complex Event Collector */
2488 pci_doe_init(dev); /* Data Object Exchange */
2490 pcie_report_downtraining(dev);
2491 pci_init_reset_methods(dev);
2495 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2496 * devices. Firmware interfaces that can select the MSI domain on a
2497 * per-device basis should be called from here.
2499 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2501 struct irq_domain *d;
2504 * If a domain has been set through the pcibios_device_add()
2505 * callback, then this is the one (platform code knows best).
2507 d = dev_get_msi_domain(&dev->dev);
2512 * Let's see if we have a firmware interface able to provide
2515 d = pci_msi_get_device_domain(dev);
2522 static void pci_set_msi_domain(struct pci_dev *dev)
2524 struct irq_domain *d;
2527 * If the platform or firmware interfaces cannot supply a
2528 * device-specific MSI domain, then inherit the default domain
2529 * from the host bridge itself.
2531 d = pci_dev_msi_domain(dev);
2533 d = dev_get_msi_domain(&dev->bus->dev);
2535 dev_set_msi_domain(&dev->dev, d);
2538 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2542 pci_configure_device(dev);
2544 device_initialize(&dev->dev);
2545 dev->dev.release = pci_release_dev;
2547 set_dev_node(&dev->dev, pcibus_to_node(bus));
2548 dev->dev.dma_mask = &dev->dma_mask;
2549 dev->dev.dma_parms = &dev->dma_parms;
2550 dev->dev.coherent_dma_mask = 0xffffffffull;
2552 dma_set_max_seg_size(&dev->dev, 65536);
2553 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2555 pcie_failed_link_retrain(dev);
2557 /* Fix up broken headers */
2558 pci_fixup_device(pci_fixup_header, dev);
2560 pci_reassigndev_resource_alignment(dev);
2562 dev->state_saved = false;
2564 pci_init_capabilities(dev);
2567 * Add the device to our list of discovered devices
2568 * and the bus list for fixup functions, etc.
2570 down_write(&pci_bus_sem);
2571 list_add_tail(&dev->bus_list, &bus->devices);
2572 up_write(&pci_bus_sem);
2574 ret = pcibios_device_add(dev);
2577 /* Set up MSI IRQ domain */
2578 pci_set_msi_domain(dev);
2580 /* Notifier could use PCI capabilities */
2581 dev->match_driver = false;
2582 ret = device_add(&dev->dev);
2586 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2588 struct pci_dev *dev;
2590 dev = pci_get_slot(bus, devfn);
2596 dev = pci_scan_device(bus, devfn);
2600 pci_device_add(dev, bus);
2604 EXPORT_SYMBOL(pci_scan_single_device);
2606 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2610 unsigned int next_fn;
2615 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2619 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2620 next_fn = PCI_ARI_CAP_NFN(cap);
2622 return -ENODEV; /* protect against malformed list */
2627 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2629 if (pci_ari_enabled(bus))
2630 return next_ari_fn(bus, dev, fn);
2634 /* only multifunction devices may have more functions */
2635 if (dev && !dev->multifunction)
2641 static int only_one_child(struct pci_bus *bus)
2643 struct pci_dev *bridge = bus->self;
2646 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2647 * we scan for all possible devices, not just Device 0.
2649 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2653 * A PCIe Downstream Port normally leads to a Link with only Device
2654 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2655 * only for Device 0 in that situation.
2657 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2664 * pci_scan_slot - Scan a PCI slot on a bus for devices
2665 * @bus: PCI bus to scan
2666 * @devfn: slot number to scan (must have zero function)
2668 * Scan a PCI slot on the specified PCI bus for devices, adding
2669 * discovered devices to the @bus->devices list. New devices
2670 * will not have is_added set.
2672 * Returns the number of new devices found.
2674 int pci_scan_slot(struct pci_bus *bus, int devfn)
2676 struct pci_dev *dev;
2679 if (only_one_child(bus) && (devfn > 0))
2680 return 0; /* Already scanned the entire slot */
2683 dev = pci_scan_single_device(bus, devfn + fn);
2685 if (!pci_dev_is_added(dev))
2688 dev->multifunction = 1;
2689 } else if (fn == 0) {
2691 * Function 0 is required unless we are running on
2692 * a hypervisor that passes through individual PCI
2695 if (!hypervisor_isolated_pci_functions())
2698 fn = next_fn(bus, dev, fn);
2701 /* Only one slot has PCIe device */
2702 if (bus->self && nr)
2703 pcie_aspm_init_link_state(bus->self);
2707 EXPORT_SYMBOL(pci_scan_slot);
2709 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2713 if (!pci_is_pcie(dev))
2717 * We don't have a way to change MPS settings on devices that have
2718 * drivers attached. A hot-added device might support only the minimum
2719 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2720 * where devices may be hot-added, we limit the fabric MPS to 128 so
2721 * hot-added devices will work correctly.
2723 * However, if we hot-add a device to a slot directly below a Root
2724 * Port, it's impossible for there to be other existing devices below
2725 * the port. We don't limit the MPS in this case because we can
2726 * reconfigure MPS on both the Root Port and the hot-added device,
2727 * and there are no other devices involved.
2729 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2731 if (dev->is_hotplug_bridge &&
2732 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2735 if (*smpss > dev->pcie_mpss)
2736 *smpss = dev->pcie_mpss;
2741 static void pcie_write_mps(struct pci_dev *dev, int mps)
2745 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2746 mps = 128 << dev->pcie_mpss;
2748 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2752 * For "Performance", the assumption is made that
2753 * downstream communication will never be larger than
2754 * the MRRS. So, the MPS only needs to be configured
2755 * for the upstream communication. This being the case,
2756 * walk from the top down and set the MPS of the child
2757 * to that of the parent bus.
2759 * Configure the device MPS with the smaller of the
2760 * device MPSS or the bridge MPS (which is assumed to be
2761 * properly configured at this point to the largest
2762 * allowable MPS based on its parent bus).
2764 mps = min(mps, pcie_get_mps(dev->bus->self));
2767 rc = pcie_set_mps(dev, mps);
2769 pci_err(dev, "Failed attempting to set the MPS\n");
2772 static void pcie_write_mrrs(struct pci_dev *dev)
2777 * In the "safe" case, do not configure the MRRS. There appear to be
2778 * issues with setting MRRS to 0 on a number of devices.
2780 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2784 * For max performance, the MRRS must be set to the largest supported
2785 * value. However, it cannot be configured larger than the MPS the
2786 * device or the bus can support. This should already be properly
2787 * configured by a prior call to pcie_write_mps().
2789 mrrs = pcie_get_mps(dev);
2792 * MRRS is a R/W register. Invalid values can be written, but a
2793 * subsequent read will verify if the value is acceptable or not.
2794 * If the MRRS value provided is not acceptable (e.g., too large),
2795 * shrink the value until it is acceptable to the HW.
2797 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2798 rc = pcie_set_readrq(dev, mrrs);
2802 pci_warn(dev, "Failed attempting to set the MRRS\n");
2807 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2810 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2814 if (!pci_is_pcie(dev))
2817 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2818 pcie_bus_config == PCIE_BUS_DEFAULT)
2821 mps = 128 << *(u8 *)data;
2822 orig_mps = pcie_get_mps(dev);
2824 pcie_write_mps(dev, mps);
2825 pcie_write_mrrs(dev);
2827 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2828 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2829 orig_mps, pcie_get_readrq(dev));
2835 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2836 * parents then children fashion. If this changes, then this code will not
2839 void pcie_bus_configure_settings(struct pci_bus *bus)
2846 if (!pci_is_pcie(bus->self))
2850 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2851 * to be aware of the MPS of the destination. To work around this,
2852 * simply force the MPS of the entire system to the smallest possible.
2854 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2857 if (pcie_bus_config == PCIE_BUS_SAFE) {
2858 smpss = bus->self->pcie_mpss;
2860 pcie_find_smpss(bus->self, &smpss);
2861 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2864 pcie_bus_configure_set(bus->self, &smpss);
2865 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2867 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2870 * Called after each bus is probed, but before its children are examined. This
2871 * is marked as __weak because multiple architectures define it.
2873 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2875 /* nothing to do, expected to be removed in the future */
2879 * pci_scan_child_bus_extend() - Scan devices below a bus
2880 * @bus: Bus to scan for devices
2881 * @available_buses: Total number of buses available (%0 does not try to
2882 * extend beyond the minimal)
2884 * Scans devices below @bus including subordinate buses. Returns new
2885 * subordinate number including all the found devices. Passing
2886 * @available_buses causes the remaining bus space to be distributed
2887 * equally between hotplug-capable bridges to allow future extension of the
2890 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2891 unsigned int available_buses)
2893 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2894 unsigned int start = bus->busn_res.start;
2895 unsigned int devfn, cmax, max = start;
2896 struct pci_dev *dev;
2898 dev_dbg(&bus->dev, "scanning bus\n");
2900 /* Go find them, Rover! */
2901 for (devfn = 0; devfn < 256; devfn += 8)
2902 pci_scan_slot(bus, devfn);
2904 /* Reserve buses for SR-IOV capability */
2905 used_buses = pci_iov_bus_range(bus);
2909 * After performing arch-dependent fixup of the bus, look behind
2910 * all PCI-to-PCI bridges on this bus.
2912 if (!bus->is_added) {
2913 dev_dbg(&bus->dev, "fixups for bus\n");
2914 pcibios_fixup_bus(bus);
2919 * Calculate how many hotplug bridges and normal bridges there
2920 * are on this bus. We will distribute the additional available
2921 * buses between hotplug bridges.
2923 for_each_pci_bridge(dev, bus) {
2924 if (dev->is_hotplug_bridge)
2931 * Scan bridges that are already configured. We don't touch them
2932 * unless they are misconfigured (which will be done in the second
2935 for_each_pci_bridge(dev, bus) {
2937 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2940 * Reserve one bus for each bridge now to avoid extending
2941 * hotplug bridges too much during the second scan below.
2945 used_buses += max - cmax - 1;
2948 /* Scan bridges that need to be reconfigured */
2949 for_each_pci_bridge(dev, bus) {
2950 unsigned int buses = 0;
2952 if (!hotplug_bridges && normal_bridges == 1) {
2954 * There is only one bridge on the bus (upstream
2955 * port) so it gets all available buses which it
2956 * can then distribute to the possible hotplug
2959 buses = available_buses;
2960 } else if (dev->is_hotplug_bridge) {
2962 * Distribute the extra buses between hotplug
2965 buses = available_buses / hotplug_bridges;
2966 buses = min(buses, available_buses - used_buses + 1);
2970 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2971 /* One bus is already accounted so don't add it again */
2973 used_buses += max - cmax - 1;
2977 * Make sure a hotplug bridge has at least the minimum requested
2978 * number of buses but allow it to grow up to the maximum available
2979 * bus number if there is room.
2981 if (bus->self && bus->self->is_hotplug_bridge) {
2982 used_buses = max_t(unsigned int, available_buses,
2983 pci_hotplug_bus_size - 1);
2984 if (max - start < used_buses) {
2985 max = start + used_buses;
2987 /* Do not allocate more buses than we have room left */
2988 if (max > bus->busn_res.end)
2989 max = bus->busn_res.end;
2991 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2992 &bus->busn_res, max - start);
2997 * We've scanned the bus and so we know all about what's on
2998 * the other side of any bridges that may be on this bus plus
3001 * Return how far we've got finding sub-buses.
3003 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
3008 * pci_scan_child_bus() - Scan devices below a bus
3009 * @bus: Bus to scan for devices
3011 * Scans devices below @bus including subordinate buses. Returns new
3012 * subordinate number including all the found devices.
3014 unsigned int pci_scan_child_bus(struct pci_bus *bus)
3016 return pci_scan_child_bus_extend(bus, 0);
3018 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3021 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3022 * @bridge: Host bridge to set up
3024 * Default empty implementation. Replace with an architecture-specific setup
3025 * routine, if necessary.
3027 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3032 void __weak pcibios_add_bus(struct pci_bus *bus)
3036 void __weak pcibios_remove_bus(struct pci_bus *bus)
3040 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3041 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3044 struct pci_host_bridge *bridge;
3046 bridge = pci_alloc_host_bridge(0);
3050 bridge->dev.parent = parent;
3052 list_splice_init(resources, &bridge->windows);
3053 bridge->sysdata = sysdata;
3054 bridge->busnr = bus;
3057 error = pci_register_host_bridge(bridge);
3064 put_device(&bridge->dev);
3067 EXPORT_SYMBOL_GPL(pci_create_root_bus);
3069 int pci_host_probe(struct pci_host_bridge *bridge)
3071 struct pci_bus *bus, *child;
3074 ret = pci_scan_root_bus_bridge(bridge);
3076 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3083 * We insert PCI resources into the iomem_resource and
3084 * ioport_resource trees in either pci_bus_claim_resources()
3085 * or pci_bus_assign_resources().
3087 if (pci_has_flag(PCI_PROBE_ONLY)) {
3088 pci_bus_claim_resources(bus);
3090 pci_bus_size_bridges(bus);
3091 pci_bus_assign_resources(bus);
3093 list_for_each_entry(child, &bus->children, node)
3094 pcie_bus_configure_settings(child);
3097 pci_bus_add_devices(bus);
3100 EXPORT_SYMBOL_GPL(pci_host_probe);
3102 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3104 struct resource *res = &b->busn_res;
3105 struct resource *parent_res, *conflict;
3109 res->flags = IORESOURCE_BUS;
3111 if (!pci_is_root_bus(b))
3112 parent_res = &b->parent->busn_res;
3114 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3115 res->flags |= IORESOURCE_PCI_FIXED;
3118 conflict = request_resource_conflict(parent_res, res);
3122 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3123 res, pci_is_root_bus(b) ? "domain " : "",
3124 parent_res, conflict->name, conflict);
3126 return conflict == NULL;
3129 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3131 struct resource *res = &b->busn_res;
3132 struct resource old_res = *res;
3133 resource_size_t size;
3136 if (res->start > bus_max)
3139 size = bus_max - res->start + 1;
3140 ret = adjust_resource(res, res->start, size);
3141 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3142 &old_res, ret ? "can not be" : "is", bus_max);
3144 if (!ret && !res->parent)
3145 pci_bus_insert_busn_res(b, res->start, res->end);
3150 void pci_bus_release_busn_res(struct pci_bus *b)
3152 struct resource *res = &b->busn_res;
3155 if (!res->flags || !res->parent)
3158 ret = release_resource(res);
3159 dev_info(&b->dev, "busn_res: %pR %s released\n",
3160 res, ret ? "can not be" : "is");
3163 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3165 struct resource_entry *window;
3173 resource_list_for_each_entry(window, &bridge->windows)
3174 if (window->res->flags & IORESOURCE_BUS) {
3175 bridge->busnr = window->res->start;
3180 ret = pci_register_host_bridge(bridge);
3185 bus = bridge->busnr;
3189 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3191 pci_bus_insert_busn_res(b, bus, 255);
3194 max = pci_scan_child_bus(b);
3197 pci_bus_update_busn_res_end(b, max);
3201 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3203 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3204 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3206 struct resource_entry *window;
3211 resource_list_for_each_entry(window, resources)
3212 if (window->res->flags & IORESOURCE_BUS) {
3217 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3223 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3225 pci_bus_insert_busn_res(b, bus, 255);
3228 max = pci_scan_child_bus(b);
3231 pci_bus_update_busn_res_end(b, max);
3235 EXPORT_SYMBOL(pci_scan_root_bus);
3237 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3240 LIST_HEAD(resources);
3243 pci_add_resource(&resources, &ioport_resource);
3244 pci_add_resource(&resources, &iomem_resource);
3245 pci_add_resource(&resources, &busn_resource);
3246 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3248 pci_scan_child_bus(b);
3250 pci_free_resource_list(&resources);
3254 EXPORT_SYMBOL(pci_scan_bus);
3257 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3258 * @bridge: PCI bridge for the bus to scan
3260 * Scan a PCI bus and child buses for new devices, add them,
3261 * and enable them, resizing bridge mmio/io resource if necessary
3262 * and possible. The caller must ensure the child devices are already
3263 * removed for resizing to occur.
3265 * Returns the max number of subordinate bus discovered.
3267 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3270 struct pci_bus *bus = bridge->subordinate;
3272 max = pci_scan_child_bus(bus);
3274 pci_assign_unassigned_bridge_resources(bridge);
3276 pci_bus_add_devices(bus);
3282 * pci_rescan_bus - Scan a PCI bus for devices
3283 * @bus: PCI bus to scan
3285 * Scan a PCI bus and child buses for new devices, add them,
3288 * Returns the max number of subordinate bus discovered.
3290 unsigned int pci_rescan_bus(struct pci_bus *bus)
3294 max = pci_scan_child_bus(bus);
3295 pci_assign_unassigned_bus_resources(bus);
3296 pci_bus_add_devices(bus);
3300 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3303 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3304 * routines should always be executed under this mutex.
3306 static DEFINE_MUTEX(pci_rescan_remove_lock);
3308 void pci_lock_rescan_remove(void)
3310 mutex_lock(&pci_rescan_remove_lock);
3312 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3314 void pci_unlock_rescan_remove(void)
3316 mutex_unlock(&pci_rescan_remove_lock);
3318 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3320 static int __init pci_sort_bf_cmp(const struct device *d_a,
3321 const struct device *d_b)
3323 const struct pci_dev *a = to_pci_dev(d_a);
3324 const struct pci_dev *b = to_pci_dev(d_b);
3326 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3327 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3329 if (a->bus->number < b->bus->number) return -1;
3330 else if (a->bus->number > b->bus->number) return 1;
3332 if (a->devfn < b->devfn) return -1;
3333 else if (a->devfn > b->devfn) return 1;
3338 void __init pci_sort_breadthfirst(void)
3340 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3343 int pci_hp_add_bridge(struct pci_dev *dev)
3345 struct pci_bus *parent = dev->bus;
3346 int busnr, start = parent->busn_res.start;
3347 unsigned int available_buses = 0;
3348 int end = parent->busn_res.end;
3350 for (busnr = start; busnr <= end; busnr++) {
3351 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3354 if (busnr-- > end) {
3355 pci_err(dev, "No bus number available for hot-added bridge\n");
3359 /* Scan bridges that are already configured */
3360 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3363 * Distribute the available bus numbers between hotplug-capable
3364 * bridges to make extending the chain later possible.
3366 available_buses = end - busnr;
3368 /* Scan bridges that need to be reconfigured */
3369 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3371 if (!dev->subordinate)
3376 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);