2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
24 LIST_HEAD(pci_devices);
27 * Some device drivers need know if pci is initiated.
28 * Basically, we think pci is not initiated when there
29 * is no device in list of pci_devices.
31 int no_pci_devices(void)
33 return list_empty(&pci_devices);
36 EXPORT_SYMBOL(no_pci_devices);
38 #ifdef HAVE_PCI_LEGACY
40 * pci_create_legacy_files - create legacy I/O port and memory files
41 * @b: bus to create files under
43 * Some platforms allow access to legacy I/O port and ISA memory space on
44 * a per-bus basis. This routine creates the files and ties them into
45 * their associated read, write and mmap files from pci-sysfs.c
47 static void pci_create_legacy_files(struct pci_bus *b)
49 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
52 b->legacy_io->attr.name = "legacy_io";
53 b->legacy_io->size = 0xffff;
54 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
55 b->legacy_io->read = pci_read_legacy_io;
56 b->legacy_io->write = pci_write_legacy_io;
57 class_device_create_bin_file(&b->class_dev, b->legacy_io);
59 /* Allocated above after the legacy_io struct */
60 b->legacy_mem = b->legacy_io + 1;
61 b->legacy_mem->attr.name = "legacy_mem";
62 b->legacy_mem->size = 1024*1024;
63 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_mem->mmap = pci_mmap_legacy_mem;
65 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
69 void pci_remove_legacy_files(struct pci_bus *b)
72 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
73 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
74 kfree(b->legacy_io); /* both are allocated here */
77 #else /* !HAVE_PCI_LEGACY */
78 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
79 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
80 #endif /* HAVE_PCI_LEGACY */
83 * PCI Bus Class Devices
85 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
91 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
92 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
97 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
102 static void release_pcibus_dev(struct class_device *class_dev)
104 struct pci_bus *pci_bus = to_pci_bus(class_dev);
107 put_device(pci_bus->bridge);
111 static struct class pcibus_class = {
113 .release = &release_pcibus_dev,
116 static int __init pcibus_class_init(void)
118 return class_register(&pcibus_class);
120 postcore_initcall(pcibus_class_init);
123 * Translate the low bits of the PCI base
124 * to the resource type
126 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
128 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
129 return IORESOURCE_IO;
131 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
132 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
134 return IORESOURCE_MEM;
138 * Find the extent of a PCI decode..
140 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
142 u32 size = mask & maxbase; /* Find the significant bits */
146 /* Get the lowest of them to find the decode size, and
147 from that the extent. */
148 size = (size & ~(size-1)) - 1;
150 /* base == maxbase can be valid only if the BAR has
151 already been programmed with all 1s. */
152 if (base == maxbase && ((base | size) & mask) != mask)
158 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
160 u64 size = mask & maxbase; /* Find the significant bits */
164 /* Get the lowest of them to find the decode size, and
165 from that the extent. */
166 size = (size & ~(size-1)) - 1;
168 /* base == maxbase can be valid only if the BAR has
169 already been programmed with all 1s. */
170 if (base == maxbase && ((base | size) & mask) != mask)
176 static inline int is_64bit_memory(u32 mask)
178 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
179 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
184 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
186 unsigned int pos, reg, next;
188 struct resource *res;
190 for(pos=0; pos<howmany; pos = next) {
196 res = &dev->resource[pos];
197 res->name = pci_name(dev);
198 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
199 pci_read_config_dword(dev, reg, &l);
200 pci_write_config_dword(dev, reg, ~0);
201 pci_read_config_dword(dev, reg, &sz);
202 pci_write_config_dword(dev, reg, l);
203 if (!sz || sz == 0xffffffff)
208 if ((l & PCI_BASE_ADDRESS_SPACE) ==
209 PCI_BASE_ADDRESS_SPACE_MEMORY) {
210 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
212 * For 64bit prefetchable memory sz could be 0, if the
213 * real size is bigger than 4G, so we need to check
216 if (!is_64bit_memory(l) && !sz)
218 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
219 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
221 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
224 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
225 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
227 res->end = res->start + (unsigned long) sz;
228 res->flags |= pci_calc_resource_flags(l);
229 if (is_64bit_memory(l)) {
232 pci_read_config_dword(dev, reg+4, &lhi);
233 pci_write_config_dword(dev, reg+4, ~0);
234 pci_read_config_dword(dev, reg+4, &szhi);
235 pci_write_config_dword(dev, reg+4, lhi);
236 sz64 = ((u64)szhi << 32) | raw_sz;
237 l64 = ((u64)lhi << 32) | l;
238 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
240 #if BITS_PER_LONG == 64
247 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
248 res->end = res->start + sz64;
250 if (sz64 > 0x100000000ULL) {
251 printk(KERN_ERR "PCI: Unable to handle 64-bit "
252 "BAR for device %s\n", pci_name(dev));
256 /* 64-bit wide address, treat as disabled */
257 pci_write_config_dword(dev, reg,
258 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
259 pci_write_config_dword(dev, reg+4, 0);
267 dev->rom_base_reg = rom;
268 res = &dev->resource[PCI_ROM_RESOURCE];
269 res->name = pci_name(dev);
270 pci_read_config_dword(dev, rom, &l);
271 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
272 pci_read_config_dword(dev, rom, &sz);
273 pci_write_config_dword(dev, rom, l);
276 if (sz && sz != 0xffffffff) {
277 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
279 res->flags = (l & IORESOURCE_ROM_ENABLE) |
280 IORESOURCE_MEM | IORESOURCE_PREFETCH |
281 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
282 res->start = l & PCI_ROM_ADDRESS_MASK;
283 res->end = res->start + (unsigned long) sz;
289 void pci_read_bridge_bases(struct pci_bus *child)
291 struct pci_dev *dev = child->self;
292 u8 io_base_lo, io_limit_lo;
293 u16 mem_base_lo, mem_limit_lo;
294 unsigned long base, limit;
295 struct resource *res;
298 if (!dev) /* It's a host bus, nothing to read */
301 if (dev->transparent) {
302 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
303 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
304 child->resource[i] = child->parent->resource[i - 3];
308 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
310 res = child->resource[0];
311 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
312 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
313 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
314 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
316 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
317 u16 io_base_hi, io_limit_hi;
318 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
319 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
320 base |= (io_base_hi << 16);
321 limit |= (io_limit_hi << 16);
325 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
329 res->end = limit + 0xfff;
332 res = child->resource[1];
333 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
334 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
335 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
336 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
338 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
340 res->end = limit + 0xfffff;
343 res = child->resource[2];
344 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
345 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
346 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
347 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
349 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
350 u32 mem_base_hi, mem_limit_hi;
351 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
352 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
355 * Some bridges set the base > limit by default, and some
356 * (broken) BIOSes do not initialize them. If we find
357 * this, just assume they are not being used.
359 if (mem_base_hi <= mem_limit_hi) {
360 #if BITS_PER_LONG == 64
361 base |= ((long) mem_base_hi) << 32;
362 limit |= ((long) mem_limit_hi) << 32;
364 if (mem_base_hi || mem_limit_hi) {
365 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
372 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
374 res->end = limit + 0xfffff;
378 static struct pci_bus * pci_alloc_bus(void)
382 b = kzalloc(sizeof(*b), GFP_KERNEL);
384 INIT_LIST_HEAD(&b->node);
385 INIT_LIST_HEAD(&b->children);
386 INIT_LIST_HEAD(&b->devices);
391 static struct pci_bus * __devinit
392 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
394 struct pci_bus *child;
399 * Allocate a new bus, and inherit stuff from the parent..
401 child = pci_alloc_bus();
405 child->self = bridge;
406 child->parent = parent;
407 child->ops = parent->ops;
408 child->sysdata = parent->sysdata;
409 child->bus_flags = parent->bus_flags;
410 child->bridge = get_device(&bridge->dev);
412 child->class_dev.class = &pcibus_class;
413 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
414 retval = class_device_register(&child->class_dev);
417 retval = class_device_create_file(&child->class_dev,
418 &class_device_attr_cpuaffinity);
420 goto error_file_create;
423 * Set up the primary, secondary and subordinate
426 child->number = child->secondary = busnr;
427 child->primary = parent->secondary;
428 child->subordinate = 0xff;
430 /* Set up default resource pointers and names.. */
431 for (i = 0; i < 4; i++) {
432 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
433 child->resource[i]->name = child->name;
435 bridge->subordinate = child;
440 class_device_unregister(&child->class_dev);
446 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
448 struct pci_bus *child;
450 child = pci_alloc_child_bus(parent, dev, busnr);
452 down_write(&pci_bus_sem);
453 list_add_tail(&child->node, &parent->children);
454 up_write(&pci_bus_sem);
459 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
461 struct pci_bus *parent = child->parent;
463 /* Attempts to fix that up are really dangerous unless
464 we're going to re-assign all bus numbers. */
465 if (!pcibios_assign_all_busses())
468 while (parent->parent && parent->subordinate < max) {
469 parent->subordinate = max;
470 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
471 parent = parent->parent;
476 * If it's a bridge, configure it and scan the bus behind it.
477 * For CardBus bridges, we don't scan behind as the devices will
478 * be handled by the bridge driver itself.
480 * We need to process bridges in two passes -- first we scan those
481 * already configured by the BIOS and after we are done with all of
482 * them, we proceed to assigning numbers to the remaining buses in
483 * order to avoid overlaps between old and new bus numbers.
485 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
487 struct pci_bus *child;
488 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
492 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
494 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
495 pci_name(dev), buses & 0xffffff, pass);
497 /* Disable MasterAbortMode during probing to avoid reporting
498 of bus errors (in some architectures) */
499 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
500 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
501 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
503 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
504 unsigned int cmax, busnr;
506 * Bus already configured by firmware, process it in the first
507 * pass and just note the configuration.
511 busnr = (buses >> 8) & 0xFF;
514 * If we already got to this bus through a different bridge,
515 * ignore it. This can happen with the i450NX chipset.
517 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
518 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
519 pci_domain_nr(bus), busnr);
523 child = pci_add_new_bus(bus, dev, busnr);
526 child->primary = buses & 0xFF;
527 child->subordinate = (buses >> 16) & 0xFF;
528 child->bridge_ctl = bctl;
530 cmax = pci_scan_child_bus(child);
533 if (child->subordinate > max)
534 max = child->subordinate;
537 * We need to assign a number to this bus which we always
538 * do in the second pass.
541 if (pcibios_assign_all_busses())
542 /* Temporarily disable forwarding of the
543 configuration cycles on all bridges in
544 this bus segment to avoid possible
545 conflicts in the second pass between two
546 bridges programmed with overlapping
548 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
554 pci_write_config_word(dev, PCI_STATUS, 0xffff);
556 /* Prevent assigning a bus number that already exists.
557 * This can happen when a bridge is hot-plugged */
558 if (pci_find_bus(pci_domain_nr(bus), max+1))
560 child = pci_add_new_bus(bus, dev, ++max);
561 buses = (buses & 0xff000000)
562 | ((unsigned int)(child->primary) << 0)
563 | ((unsigned int)(child->secondary) << 8)
564 | ((unsigned int)(child->subordinate) << 16);
567 * yenta.c forces a secondary latency timer of 176.
568 * Copy that behaviour here.
571 buses &= ~0xff000000;
572 buses |= CARDBUS_LATENCY_TIMER << 24;
576 * We need to blast all three values with a single write.
578 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
581 child->bridge_ctl = bctl;
583 * Adjust subordinate busnr in parent buses.
584 * We do this before scanning for children because
585 * some devices may not be detected if the bios
588 pci_fixup_parent_subordinate_busnr(child, max);
589 /* Now we can scan all subordinate buses... */
590 max = pci_scan_child_bus(child);
592 * now fix it up again since we have found
593 * the real value of max.
595 pci_fixup_parent_subordinate_busnr(child, max);
598 * For CardBus bridges, we leave 4 bus numbers
599 * as cards with a PCI-to-PCI bridge can be
602 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
603 struct pci_bus *parent = bus;
604 if (pci_find_bus(pci_domain_nr(bus),
607 while (parent->parent) {
608 if ((!pcibios_assign_all_busses()) &&
609 (parent->subordinate > max) &&
610 (parent->subordinate <= max+i)) {
613 parent = parent->parent;
617 * Often, there are two cardbus bridges
618 * -- try to leave one valid bus number
626 pci_fixup_parent_subordinate_busnr(child, max);
629 * Set the subordinate bus number to its real value.
631 child->subordinate = max;
632 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
635 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
637 /* Has only triggered on CardBus, fixup is in yenta_socket */
638 while (bus->parent) {
639 if ((child->subordinate > bus->subordinate) ||
640 (child->number > bus->subordinate) ||
641 (child->number < bus->number) ||
642 (child->subordinate < bus->number)) {
643 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
644 "hidden behind%s bridge #%02x (-#%02x)\n",
645 child->number, child->subordinate,
646 (bus->number > child->subordinate &&
647 bus->subordinate < child->number) ?
648 "wholly" : "partially",
649 bus->self->transparent ? " transparent" : "",
650 bus->number, bus->subordinate);
656 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
662 * Read interrupt line and base address registers.
663 * The architecture-dependent code can tweak these, of course.
665 static void pci_read_irq(struct pci_dev *dev)
669 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
672 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
676 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
679 * pci_setup_device - fill in class and map information of a device
680 * @dev: the device structure to fill
682 * Initialize the device structure with information about the device's
683 * vendor,class,memory and IO-space addresses,IRQ lines etc.
684 * Called at initialisation of the PCI subsystem and by CardBus services.
685 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
688 static int pci_setup_device(struct pci_dev * dev)
692 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
693 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
695 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
696 dev->revision = class & 0xff;
697 class >>= 8; /* upper 3 bytes */
701 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
702 dev->vendor, dev->device, class, dev->hdr_type);
704 /* "Unknown power state" */
705 dev->current_state = PCI_UNKNOWN;
707 /* Early fixups, before probing the BARs */
708 pci_fixup_device(pci_fixup_early, dev);
709 class = dev->class >> 8;
711 switch (dev->hdr_type) { /* header type */
712 case PCI_HEADER_TYPE_NORMAL: /* standard header */
713 if (class == PCI_CLASS_BRIDGE_PCI)
716 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
717 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
718 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
721 * Do the ugly legacy mode stuff here rather than broken chip
722 * quirk code. Legacy mode ATA controllers have fixed
723 * addresses. These are not always echoed in BAR0-3, and
724 * BAR0-3 in a few cases contain junk!
726 if (class == PCI_CLASS_STORAGE_IDE) {
728 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
729 if ((progif & 1) == 0) {
730 dev->resource[0].start = 0x1F0;
731 dev->resource[0].end = 0x1F7;
732 dev->resource[0].flags = LEGACY_IO_RESOURCE;
733 dev->resource[1].start = 0x3F6;
734 dev->resource[1].end = 0x3F6;
735 dev->resource[1].flags = LEGACY_IO_RESOURCE;
737 if ((progif & 4) == 0) {
738 dev->resource[2].start = 0x170;
739 dev->resource[2].end = 0x177;
740 dev->resource[2].flags = LEGACY_IO_RESOURCE;
741 dev->resource[3].start = 0x376;
742 dev->resource[3].end = 0x376;
743 dev->resource[3].flags = LEGACY_IO_RESOURCE;
748 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
749 if (class != PCI_CLASS_BRIDGE_PCI)
751 /* The PCI-to-PCI bridge spec requires that subtractive
752 decoding (i.e. transparent) bridge must have programming
753 interface code of 0x01. */
755 dev->transparent = ((dev->class & 0xff) == 1);
756 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
759 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
760 if (class != PCI_CLASS_BRIDGE_CARDBUS)
763 pci_read_bases(dev, 1, 0);
764 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
765 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
768 default: /* unknown header */
769 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
770 pci_name(dev), dev->hdr_type);
774 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
775 pci_name(dev), class, dev->hdr_type);
776 dev->class = PCI_CLASS_NOT_DEFINED;
779 /* We found a fine healthy device, go go go... */
784 * pci_release_dev - free a pci device structure when all users of it are finished.
785 * @dev: device that's been disconnected
787 * Will be called only by the device core when all users of this pci device are
790 static void pci_release_dev(struct device *dev)
792 struct pci_dev *pci_dev;
794 pci_dev = to_pci_dev(dev);
798 static void set_pcie_port_type(struct pci_dev *pdev)
803 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
807 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
808 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
812 * pci_cfg_space_size - get the configuration space size of the PCI device.
815 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
816 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
817 * access it. Maybe we don't have a way to generate extended config space
818 * accesses, or the device is behind a reverse Express bridge. So we try
819 * reading the dword at 0x100 which must either be 0 or a valid extended
822 int pci_cfg_space_size(struct pci_dev *dev)
827 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
829 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
833 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
834 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
838 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
840 if (status == 0xffffffff)
843 return PCI_CFG_SPACE_EXP_SIZE;
846 return PCI_CFG_SPACE_SIZE;
849 static void pci_release_bus_bridge_dev(struct device *dev)
854 struct pci_dev *alloc_pci_dev(void)
858 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
862 INIT_LIST_HEAD(&dev->global_list);
863 INIT_LIST_HEAD(&dev->bus_list);
865 pci_msi_init_pci_dev(dev);
869 EXPORT_SYMBOL(alloc_pci_dev);
872 * Read the config data for a PCI device, sanity-check it
873 * and fill in the dev structure...
875 static struct pci_dev * __devinit
876 pci_scan_device(struct pci_bus *bus, int devfn)
883 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
886 /* some broken boards return 0 or ~0 if a slot is empty: */
887 if (l == 0xffffffff || l == 0x00000000 ||
888 l == 0x0000ffff || l == 0xffff0000)
891 /* Configuration request Retry Status */
892 while (l == 0xffff0001) {
895 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
897 /* Card hasn't responded in 60 seconds? Must be stuck. */
898 if (delay > 60 * 1000) {
899 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
900 "responding\n", pci_domain_nr(bus),
901 bus->number, PCI_SLOT(devfn),
907 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
910 dev = alloc_pci_dev();
915 dev->sysdata = bus->sysdata;
916 dev->dev.parent = bus->bridge;
917 dev->dev.bus = &pci_bus_type;
919 dev->hdr_type = hdr_type & 0x7f;
920 dev->multifunction = !!(hdr_type & 0x80);
921 dev->vendor = l & 0xffff;
922 dev->device = (l >> 16) & 0xffff;
923 dev->cfg_size = pci_cfg_space_size(dev);
924 dev->error_state = pci_channel_io_normal;
925 set_pcie_port_type(dev);
927 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
928 set this higher, assuming the system even supports it. */
929 dev->dma_mask = 0xffffffff;
930 if (pci_setup_device(dev) < 0) {
938 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
940 device_initialize(&dev->dev);
941 dev->dev.release = pci_release_dev;
944 set_dev_node(&dev->dev, pcibus_to_node(bus));
945 dev->dev.dma_mask = &dev->dma_mask;
946 dev->dev.coherent_dma_mask = 0xffffffffull;
948 /* Fix up broken headers */
949 pci_fixup_device(pci_fixup_header, dev);
952 * Add the device to our list of discovered devices
953 * and the bus list for fixup functions, etc.
955 INIT_LIST_HEAD(&dev->global_list);
956 down_write(&pci_bus_sem);
957 list_add_tail(&dev->bus_list, &bus->devices);
958 up_write(&pci_bus_sem);
961 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
965 dev = pci_scan_device(bus, devfn);
969 pci_device_add(dev, bus);
973 EXPORT_SYMBOL(pci_scan_single_device);
976 * pci_scan_slot - scan a PCI slot on a bus for devices.
977 * @bus: PCI bus to scan
978 * @devfn: slot number to scan (must have zero function.)
980 * Scan a PCI slot on the specified PCI bus for devices, adding
981 * discovered devices to the @bus->devices list. New devices
982 * will have an empty dev->global_list head.
984 int pci_scan_slot(struct pci_bus *bus, int devfn)
989 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
991 for (func = 0; func < 8; func++, devfn++) {
994 dev = pci_scan_single_device(bus, devfn);
999 * If this is a single function device,
1000 * don't scan past the first function.
1002 if (!dev->multifunction) {
1004 dev->multifunction = 1;
1010 if (func == 0 && !scan_all_fns)
1016 pcie_aspm_init_link_state(bus->self);
1021 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1023 unsigned int devfn, pass, max = bus->secondary;
1024 struct pci_dev *dev;
1026 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1028 /* Go find them, Rover! */
1029 for (devfn = 0; devfn < 0x100; devfn += 8)
1030 pci_scan_slot(bus, devfn);
1033 * After performing arch-dependent fixup of the bus, look behind
1034 * all PCI-to-PCI bridges on this bus.
1036 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1037 pcibios_fixup_bus(bus);
1038 for (pass=0; pass < 2; pass++)
1039 list_for_each_entry(dev, &bus->devices, bus_list) {
1040 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1041 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1042 max = pci_scan_bridge(bus, dev, max, pass);
1046 * We've scanned the bus and so we know all about what's on
1047 * the other side of any bridges that may be on this bus plus
1050 * Return how far we've got finding sub-buses.
1052 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1053 pci_domain_nr(bus), bus->number, max);
1057 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
1061 max = pci_scan_child_bus(bus);
1064 * Make the discovered devices available.
1066 pci_bus_add_devices(bus);
1071 struct pci_bus * pci_create_bus(struct device *parent,
1072 int bus, struct pci_ops *ops, void *sysdata)
1078 b = pci_alloc_bus();
1082 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1088 b->sysdata = sysdata;
1091 if (pci_find_bus(pci_domain_nr(b), bus)) {
1092 /* If we already got to this bus through a different bridge, ignore it */
1093 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1097 down_write(&pci_bus_sem);
1098 list_add_tail(&b->node, &pci_root_buses);
1099 up_write(&pci_bus_sem);
1101 memset(dev, 0, sizeof(*dev));
1102 dev->parent = parent;
1103 dev->release = pci_release_bus_bridge_dev;
1104 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1105 error = device_register(dev);
1108 b->bridge = get_device(dev);
1110 b->class_dev.class = &pcibus_class;
1111 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1112 error = class_device_register(&b->class_dev);
1114 goto class_dev_reg_err;
1115 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1117 goto class_dev_create_file_err;
1119 /* Create legacy_io and legacy_mem files for this bus */
1120 pci_create_legacy_files(b);
1122 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1124 goto sys_create_link_err;
1126 b->number = b->secondary = bus;
1127 b->resource[0] = &ioport_resource;
1128 b->resource[1] = &iomem_resource;
1132 sys_create_link_err:
1133 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1134 class_dev_create_file_err:
1135 class_device_unregister(&b->class_dev);
1137 device_unregister(dev);
1139 down_write(&pci_bus_sem);
1141 up_write(&pci_bus_sem);
1148 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1149 int bus, struct pci_ops *ops, void *sysdata)
1153 b = pci_create_bus(parent, bus, ops, sysdata);
1155 b->subordinate = pci_scan_child_bus(b);
1158 EXPORT_SYMBOL(pci_scan_bus_parented);
1160 #ifdef CONFIG_HOTPLUG
1161 EXPORT_SYMBOL(pci_add_new_bus);
1162 EXPORT_SYMBOL(pci_do_scan_bus);
1163 EXPORT_SYMBOL(pci_scan_slot);
1164 EXPORT_SYMBOL(pci_scan_bridge);
1165 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1168 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1170 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1171 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1173 if (a->bus->number < b->bus->number) return -1;
1174 else if (a->bus->number > b->bus->number) return 1;
1176 if (a->devfn < b->devfn) return -1;
1177 else if (a->devfn > b->devfn) return 1;
1183 * Yes, this forcably breaks the klist abstraction temporarily. It
1184 * just wants to sort the klist, not change reference counts and
1185 * take/drop locks rapidly in the process. It does all this while
1186 * holding the lock for the list, so objects can't otherwise be
1187 * added/removed while we're swizzling.
1189 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1191 struct list_head *pos;
1192 struct klist_node *n;
1196 list_for_each(pos, list) {
1197 n = container_of(pos, struct klist_node, n_node);
1198 dev = container_of(n, struct device, knode_bus);
1199 b = to_pci_dev(dev);
1200 if (pci_sort_bf_cmp(a, b) <= 0) {
1201 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1205 list_move_tail(&a->dev.knode_bus.n_node, list);
1208 static void __init pci_sort_breadthfirst_klist(void)
1210 LIST_HEAD(sorted_devices);
1211 struct list_head *pos, *tmp;
1212 struct klist_node *n;
1214 struct pci_dev *pdev;
1215 struct klist *device_klist;
1217 device_klist = bus_get_device_klist(&pci_bus_type);
1219 spin_lock(&device_klist->k_lock);
1220 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1221 n = container_of(pos, struct klist_node, n_node);
1222 dev = container_of(n, struct device, knode_bus);
1223 pdev = to_pci_dev(dev);
1224 pci_insertion_sort_klist(pdev, &sorted_devices);
1226 list_splice(&sorted_devices, &device_klist->k_list);
1227 spin_unlock(&device_klist->k_lock);
1230 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1234 list_for_each_entry(b, list, global_list) {
1235 if (pci_sort_bf_cmp(a, b) <= 0) {
1236 list_move_tail(&a->global_list, &b->global_list);
1240 list_move_tail(&a->global_list, list);
1243 static void __init pci_sort_breadthfirst_devices(void)
1245 LIST_HEAD(sorted_devices);
1246 struct pci_dev *dev, *tmp;
1248 down_write(&pci_bus_sem);
1249 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1250 pci_insertion_sort_devices(dev, &sorted_devices);
1252 list_splice(&sorted_devices, &pci_devices);
1253 up_write(&pci_bus_sem);
1256 void __init pci_sort_breadthfirst(void)
1258 pci_sort_breadthfirst_devices();
1259 pci_sort_breadthfirst_klist();