1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXI Bridge for PCI Express Driver
5 * Copyright (C) 2016 Imagination Technologies
11 #include <asm/global_data.h>
12 #include <linux/bitops.h>
17 * struct xilinx_pcie - Xilinx PCIe controller state
18 * @cfg_base: The base address of memory mapped configuration space
24 /* Register definitions */
25 #define XILINX_PCIE_REG_PSCR 0x144
26 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
29 * pcie_xilinx_link_up() - Check whether the PCIe link is up
30 * @pcie: Pointer to the PCI controller state
32 * Checks whether the PCIe link for the given device is up or down.
34 * Return: true if the link is up, else false
36 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
38 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
40 return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
44 * pcie_xilinx_config_address() - Calculate the address of a config access
45 * @udev: Pointer to the PCI bus
46 * @bdf: Identifies the PCIe device to access
47 * @offset: The offset into the device's configuration space
48 * @paddress: Pointer to the pointer to write the calculates address to
50 * Calculates the address that should be accessed to perform a PCIe
51 * configuration space access for a given device identified by the PCIe
52 * controller device @pcie and the bus, device & function numbers in @bdf. If
53 * access to the device is not valid then the function will return an error
54 * code. Otherwise the address to access will be written to the pointer pointed
57 * Return: 0 on success, else -ENODEV
59 static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
60 uint offset, void **paddress)
62 struct xilinx_pcie *pcie = dev_get_priv(udev);
63 unsigned int bus = PCI_BUS(bdf);
64 unsigned int dev = PCI_DEV(bdf);
65 unsigned int func = PCI_FUNC(bdf);
68 if ((bus > 0) && !pcie_xilinx_link_up(pcie))
72 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
73 * limited to a single device each.
75 if ((bus < 2) && (dev > 0))
78 addr = pcie->cfg_base;
79 addr += PCIE_ECAM_OFFSET(bus, dev, func, offset);
86 * pcie_xilinx_read_config() - Read from configuration space
87 * @bus: Pointer to the PCI bus
88 * @bdf: Identifies the PCIe device to access
89 * @offset: The offset into the device's configuration space
90 * @valuep: A pointer at which to store the read value
91 * @size: Indicates the size of access to perform
93 * Read a value of size @size from offset @offset within the configuration
94 * space of the device identified by the bus, device & function numbers in @bdf
95 * on the PCI bus @bus.
97 * Return: 0 on success, else -ENODEV or -EINVAL
99 static int pcie_xilinx_read_config(const struct udevice *bus, pci_dev_t bdf,
100 uint offset, ulong *valuep,
101 enum pci_size_t size)
103 return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
104 bdf, offset, valuep, size);
108 * pcie_xilinx_write_config() - Write to configuration space
109 * @bus: Pointer to the PCI bus
110 * @bdf: Identifies the PCIe device to access
111 * @offset: The offset into the device's configuration space
112 * @value: The value to write
113 * @size: Indicates the size of access to perform
115 * Write the value @value of size @size from offset @offset within the
116 * configuration space of the device identified by the bus, device & function
117 * numbers in @bdf on the PCI bus @bus.
119 * Return: 0 on success, else -ENODEV or -EINVAL
121 static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
122 uint offset, ulong value,
123 enum pci_size_t size)
125 return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
126 bdf, offset, value, size);
130 * pcie_xilinx_of_to_plat() - Translate from DT to device state
131 * @dev: A pointer to the device being operated on
133 * Translate relevant data from the device tree pertaining to device @dev into
134 * state that the driver will later make use of. This state is stored in the
135 * device's private data structure.
137 * Return: 0 on success, else -EINVAL
139 static int pcie_xilinx_of_to_plat(struct udevice *dev)
141 struct xilinx_pcie *pcie = dev_get_priv(dev);
142 struct fdt_resource reg_res;
143 DECLARE_GLOBAL_DATA_PTR;
146 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
149 pr_err("\"reg\" resource not found\n");
153 pcie->cfg_base = map_physmem(reg_res.start,
154 fdt_resource_size(®_res),
160 static const struct dm_pci_ops pcie_xilinx_ops = {
161 .read_config = pcie_xilinx_read_config,
162 .write_config = pcie_xilinx_write_config,
165 static const struct udevice_id pcie_xilinx_ids[] = {
166 { .compatible = "xlnx,axi-pcie-host-1.00.a" },
170 U_BOOT_DRIVER(pcie_xilinx) = {
171 .name = "pcie_xilinx",
173 .of_match = pcie_xilinx_ids,
174 .ops = &pcie_xilinx_ops,
175 .of_to_plat = pcie_xilinx_of_to_plat,
176 .priv_auto = sizeof(struct xilinx_pcie),