1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Copyright 2018-2020 NXP
5 * PCIe Gen4 driver for NXP Layerscape SoCs
6 * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
13 #include <asm/arch/fsl_serdes.h>
16 #ifdef CONFIG_OF_BOARD_SETUP
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
20 #include <asm/arch/clock.h>
22 #include "pcie_layerscape_gen4.h"
23 #include "pcie_layerscape_fixup_common.h"
25 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
27 * Return next available LUT index.
29 static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
31 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
32 return pcie->next_lut_index++;
34 return -ENOSPC; /* LUT is full */
38 * Program a single LUT entry
40 static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
41 u32 devid, u32 streamid)
43 /* leave mask as all zeroes, want to match all bits */
44 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
45 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
49 * An msi-map is a property to be added to the pci controller
50 * node. It is a table, where each entry consists of 4 fields
53 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
54 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
56 static void fdt_pcie_set_msi_map_entry_ls_gen4(void *blob,
57 struct ls_pcie_g4 *pcie,
58 u32 devid, u32 streamid)
64 #ifdef CONFIG_FSL_PCIE_COMPAT
65 nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
66 pcie->ccsr_res.start);
68 #error "No CONFIG_FSL_PCIE_COMPAT defined"
71 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
75 /* get phandle to MSI controller */
76 prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
78 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
82 phandle = fdt32_to_cpu(*prop);
84 /* set one msi-map row */
85 fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
86 fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
87 fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
88 fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
92 * An iommu-map is a property to be added to the pci controller
93 * node. It is a table, where each entry consists of 4 fields
96 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
97 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
99 static void fdt_pcie_set_iommu_map_entry_ls_gen4(void *blob,
100 struct ls_pcie_g4 *pcie,
101 u32 devid, u32 streamid)
108 #ifdef CONFIG_FSL_PCIE_COMPAT
109 nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
110 pcie->ccsr_res.start);
112 #error "No CONFIG_FSL_PCIE_COMPAT defined"
115 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
119 /* get phandle to iommu controller */
120 prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
122 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
123 __func__, pcie->idx);
127 /* set iommu-map row */
128 iommu_map[0] = cpu_to_fdt32(devid);
129 iommu_map[1] = *++prop;
130 iommu_map[2] = cpu_to_fdt32(streamid);
131 iommu_map[3] = cpu_to_fdt32(1);
134 fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
136 fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
139 static void fdt_fixup_pcie_ls_gen4(void *blob)
141 struct udevice *dev, *bus;
142 struct ls_pcie_g4 *pcie;
147 /* Scan all known buses */
148 for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
149 for (bus = dev; device_is_on_pci_bus(bus);)
151 pcie = dev_get_priv(bus);
153 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
155 debug("ERROR: no stream ids free\n");
158 pcie->stream_id_cur++;
161 index = ls_pcie_g4_next_lut_index(pcie);
163 debug("ERROR: no LUT indexes free\n");
167 /* the DT fixup must be relative to the hose first_busno */
168 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
169 /* map PCI b.d.f to streamID in LUT */
170 ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
171 /* update msi-map in device tree */
172 fdt_pcie_set_msi_map_entry_ls_gen4(blob, pcie, bdf >> 8,
174 /* update iommu-map in device tree */
175 fdt_pcie_set_iommu_map_entry_ls_gen4(blob, pcie, bdf >> 8,
181 static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
185 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
186 pcie->ccsr_res.start);
189 debug("%s: ERROR: failed to find pcie compatiable\n",
194 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
195 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
197 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
200 static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
204 #ifdef CONFIG_FSL_PCIE_COMPAT
205 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
206 pcie->ccsr_res.start);
208 #error "No CONFIG_FSL_PCIE_COMPAT defined"
211 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
215 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
216 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
218 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
221 static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
223 ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
224 ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
227 /* Fixup Kernel DT for PCIe */
228 void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
230 struct ls_pcie_g4 *pcie;
232 list_for_each_entry(pcie, &ls_pcie_g4_list, list)
233 ft_pcie_layerscape_gen4_setup(blob, pcie);
235 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
236 fdt_fixup_pcie_ls_gen4(blob);
240 #else /* !CONFIG_OF_BOARD_SETUP */
241 void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)