1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
12 #include <asm/arch/fsl_serdes.h>
15 #ifdef CONFIG_OF_BOARD_SETUP
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
19 #include <asm/arch/clock.h>
21 #include "pcie_layerscape.h"
22 #include "pcie_layerscape_fixup_common.h"
24 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
26 * Return next available LUT index.
28 static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
30 if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
31 return pcie_rc->next_lut_index++;
33 return -ENOSPC; /* LUT is full */
36 static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
39 struct ls_pcie *pcie = pcie_rc->pcie;
42 out_be32(pcie->lut + offset, value);
44 out_le32(pcie->lut + offset, value);
48 * Program a single LUT entry
50 static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
51 u32 devid, u32 streamid)
53 /* leave mask as all zeroes, want to match all bits */
54 lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
55 lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
59 * An msi-map is a property to be added to the pci controller
60 * node. It is a table, where each entry consists of 4 fields
63 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
64 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
66 static void fdt_pcie_set_msi_map_entry_ls(void *blob,
67 struct ls_pcie_rc *pcie_rc,
68 u32 devid, u32 streamid)
75 struct ls_pcie *pcie = pcie_rc->pcie;
77 /* find pci controller node */
78 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
79 pcie_rc->dbi_res.start);
81 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
82 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
83 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
84 svr == SVR_LS2048A || svr == SVR_LS2044A ||
85 svr == SVR_LS2081A || svr == SVR_LS2041A)
86 compat = "fsl,ls2088a-pcie";
88 compat = CONFIG_FSL_PCIE_COMPAT;
90 nodeoffset = fdt_node_offset_by_compat_reg(blob,
91 compat, pcie_rc->dbi_res.start);
97 /* get phandle to MSI controller */
98 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
100 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
101 __func__, pcie->idx);
104 phandle = fdt32_to_cpu(*prop);
106 /* set one msi-map row */
107 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
108 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
109 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
110 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
114 * An iommu-map is a property to be added to the pci controller
115 * node. It is a table, where each entry consists of 4 fields
118 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
119 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
121 static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
122 struct ls_pcie_rc *pcie_rc,
123 u32 devid, u32 streamid)
131 struct ls_pcie *pcie = pcie_rc->pcie;
133 /* find pci controller node */
134 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
135 pcie_rc->dbi_res.start);
136 if (nodeoffset < 0) {
137 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
138 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
139 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
140 svr == SVR_LS2048A || svr == SVR_LS2044A ||
141 svr == SVR_LS2081A || svr == SVR_LS2041A)
142 compat = "fsl,ls2088a-pcie";
144 compat = CONFIG_FSL_PCIE_COMPAT;
147 nodeoffset = fdt_node_offset_by_compat_reg(blob,
148 compat, pcie_rc->dbi_res.start);
154 /* get phandle to iommu controller */
155 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
157 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
158 __func__, pcie->idx);
162 /* set iommu-map row */
163 iommu_map[0] = cpu_to_fdt32(devid);
164 iommu_map[1] = *++prop;
165 iommu_map[2] = cpu_to_fdt32(streamid);
166 iommu_map[3] = cpu_to_fdt32(1);
169 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
172 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
176 static void fdt_fixup_pcie_ls(void *blob)
178 struct udevice *dev, *bus;
179 struct ls_pcie_rc *pcie_rc;
184 /* Scan all known buses */
185 for (pci_find_first_device(&dev);
187 pci_find_next_device(&dev)) {
188 for (bus = dev; device_is_on_pci_bus(bus);)
190 pcie_rc = dev_get_priv(bus);
192 streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
195 debug("ERROR: no stream ids free\n");
198 pcie_rc->stream_id_cur++;
201 index = ls_pcie_next_lut_index(pcie_rc);
203 debug("ERROR: no LUT indexes free\n");
207 /* the DT fixup must be relative to the hose first_busno */
208 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
209 /* map PCI b.d.f to streamID in LUT */
210 ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
212 /* update msi-map in device tree */
213 fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
215 /* update iommu-map in device tree */
216 fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
219 pcie_board_fix_fdt(blob);
223 static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
228 struct ls_pcie *pcie = pcie_rc->pcie;
230 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
231 pcie_rc->dbi_res.start);
233 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
234 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
235 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
236 svr == SVR_LS2048A || svr == SVR_LS2044A ||
237 svr == SVR_LS2081A || svr == SVR_LS2041A)
238 compat = "fsl,ls2088a-pcie";
240 compat = CONFIG_FSL_PCIE_COMPAT;
242 off = fdt_node_offset_by_compat_reg(blob,
243 compat, pcie_rc->dbi_res.start);
249 if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
250 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
252 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
255 static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
258 struct ls_pcie *pcie = pcie_rc->pcie;
260 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
261 pcie_rc->dbi_res.start);
265 if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
266 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
268 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
271 static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
273 ft_pcie_ep_fix(blob, pcie_rc);
274 ft_pcie_rc_fix(blob, pcie_rc);
277 /* Fixup Kernel DT for PCIe */
278 void ft_pci_setup_ls(void *blob, struct bd_info *bd)
280 struct ls_pcie_rc *pcie_rc;
282 list_for_each_entry(pcie_rc, &ls_pcie_list, list)
283 ft_pcie_ls_setup(blob, pcie_rc);
285 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
286 fdt_fixup_pcie_ls(blob);
290 #else /* !CONFIG_OF_BOARD_SETUP */
291 void ft_pci_setup_ls(void *blob, struct bd_info *bd)