1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
13 #include <asm/arch/fsl_serdes.h>
16 #ifdef CONFIG_OF_BOARD_SETUP
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
20 #include <asm/arch/clock.h>
22 #include "pcie_layerscape.h"
23 #include "pcie_layerscape_fixup_common.h"
25 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
27 * Return next available LUT index.
29 static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
31 if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
32 return pcie_rc->next_lut_index++;
34 return -ENOSPC; /* LUT is full */
37 static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
40 struct ls_pcie *pcie = pcie_rc->pcie;
43 out_be32(pcie->lut + offset, value);
45 out_le32(pcie->lut + offset, value);
49 * Program a single LUT entry
51 static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
52 u32 devid, u32 streamid)
54 /* leave mask as all zeroes, want to match all bits */
55 lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
56 lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
60 * An msi-map is a property to be added to the pci controller
61 * node. It is a table, where each entry consists of 4 fields
64 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
65 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
67 static void fdt_pcie_set_msi_map_entry_ls(void *blob,
68 struct ls_pcie_rc *pcie_rc,
69 u32 devid, u32 streamid)
76 struct ls_pcie *pcie = pcie_rc->pcie;
78 /* find pci controller node */
79 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
80 pcie_rc->dbi_res.start);
82 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
83 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
84 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
85 svr == SVR_LS2048A || svr == SVR_LS2044A ||
86 svr == SVR_LS2081A || svr == SVR_LS2041A)
87 compat = "fsl,ls2088a-pcie";
89 compat = CONFIG_FSL_PCIE_COMPAT;
91 nodeoffset = fdt_node_offset_by_compat_reg(blob,
92 compat, pcie_rc->dbi_res.start);
98 /* get phandle to MSI controller */
99 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
101 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
102 __func__, pcie->idx);
105 phandle = fdt32_to_cpu(*prop);
107 /* set one msi-map row */
108 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
109 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
110 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
111 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
115 * An iommu-map is a property to be added to the pci controller
116 * node. It is a table, where each entry consists of 4 fields
119 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
120 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
122 static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
123 struct ls_pcie_rc *pcie_rc,
124 u32 devid, u32 streamid)
132 struct ls_pcie *pcie = pcie_rc->pcie;
134 /* find pci controller node */
135 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
136 pcie_rc->dbi_res.start);
137 if (nodeoffset < 0) {
138 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
139 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
140 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
141 svr == SVR_LS2048A || svr == SVR_LS2044A ||
142 svr == SVR_LS2081A || svr == SVR_LS2041A)
143 compat = "fsl,ls2088a-pcie";
145 compat = CONFIG_FSL_PCIE_COMPAT;
148 nodeoffset = fdt_node_offset_by_compat_reg(blob,
149 compat, pcie_rc->dbi_res.start);
155 /* get phandle to iommu controller */
156 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
158 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
159 __func__, pcie->idx);
163 /* set iommu-map row */
164 iommu_map[0] = cpu_to_fdt32(devid);
165 iommu_map[1] = *++prop;
166 iommu_map[2] = cpu_to_fdt32(streamid);
167 iommu_map[3] = cpu_to_fdt32(1);
170 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
173 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
177 static void fdt_fixup_pcie_ls(void *blob)
179 struct udevice *dev, *bus;
180 struct ls_pcie_rc *pcie_rc;
185 /* Scan all known buses */
186 for (pci_find_first_device(&dev);
188 pci_find_next_device(&dev)) {
189 for (bus = dev; device_is_on_pci_bus(bus);)
191 pcie_rc = dev_get_priv(bus);
193 streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
196 debug("ERROR: no stream ids free\n");
199 pcie_rc->stream_id_cur++;
202 index = ls_pcie_next_lut_index(pcie_rc);
204 debug("ERROR: no LUT indexes free\n");
208 /* the DT fixup must be relative to the hose first_busno */
209 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
210 /* map PCI b.d.f to streamID in LUT */
211 ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
213 /* update msi-map in device tree */
214 fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
216 /* update iommu-map in device tree */
217 fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
220 pcie_board_fix_fdt(blob);
224 static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
229 struct ls_pcie *pcie = pcie_rc->pcie;
231 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
232 pcie_rc->dbi_res.start);
234 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
235 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
236 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
237 svr == SVR_LS2048A || svr == SVR_LS2044A ||
238 svr == SVR_LS2081A || svr == SVR_LS2041A)
239 compat = "fsl,ls2088a-pcie";
241 compat = CONFIG_FSL_PCIE_COMPAT;
243 off = fdt_node_offset_by_compat_reg(blob,
244 compat, pcie_rc->dbi_res.start);
250 if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
251 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
253 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
256 static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
259 struct ls_pcie *pcie = pcie_rc->pcie;
261 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
262 pcie_rc->dbi_res.start);
266 if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
267 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
269 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
272 static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
274 ft_pcie_ep_fix(blob, pcie_rc);
275 ft_pcie_rc_fix(blob, pcie_rc);
278 /* Fixup Kernel DT for PCIe */
279 void ft_pci_setup_ls(void *blob, struct bd_info *bd)
281 struct ls_pcie_rc *pcie_rc;
283 list_for_each_entry(pcie_rc, &ls_pcie_list, list)
284 ft_pcie_ls_setup(blob, pcie_rc);
286 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
287 fdt_fixup_pcie_ls(blob);
291 #else /* !CONFIG_OF_BOARD_SETUP */
292 void ft_pci_setup_ls(void *blob, struct bd_info *bd)