1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
11 #include <asm/arch/fsl_serdes.h>
14 #ifdef CONFIG_OF_BOARD_SETUP
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
18 #include <asm/arch/clock.h>
20 #include "pcie_layerscape.h"
21 #include "pcie_layerscape_fixup_common.h"
23 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
25 * Return next available LUT index.
27 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
29 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
30 return pcie->next_lut_index++;
32 return -ENOSPC; /* LUT is full */
35 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
39 out_be32(pcie->lut + offset, value);
41 out_le32(pcie->lut + offset, value);
45 * Program a single LUT entry
47 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
50 /* leave mask as all zeroes, want to match all bits */
51 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
52 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
56 * An msi-map is a property to be added to the pci controller
57 * node. It is a table, where each entry consists of 4 fields
60 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
61 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
63 static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
64 u32 devid, u32 streamid)
72 /* find pci controller node */
73 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
76 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
77 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
78 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
79 svr == SVR_LS2048A || svr == SVR_LS2044A ||
80 svr == SVR_LS2081A || svr == SVR_LS2041A)
81 compat = "fsl,ls2088a-pcie";
83 compat = CONFIG_FSL_PCIE_COMPAT;
85 nodeoffset = fdt_node_offset_by_compat_reg(blob,
86 compat, pcie->dbi_res.start);
92 /* get phandle to MSI controller */
93 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
95 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
99 phandle = fdt32_to_cpu(*prop);
101 /* set one msi-map row */
102 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
103 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
104 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
105 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
109 * An iommu-map is a property to be added to the pci controller
110 * node. It is a table, where each entry consists of 4 fields
113 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
114 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
116 static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
117 u32 devid, u32 streamid)
126 /* find pci controller node */
127 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
128 pcie->dbi_res.start);
129 if (nodeoffset < 0) {
130 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
131 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
132 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
133 svr == SVR_LS2048A || svr == SVR_LS2044A ||
134 svr == SVR_LS2081A || svr == SVR_LS2041A)
135 compat = "fsl,ls2088a-pcie";
137 compat = CONFIG_FSL_PCIE_COMPAT;
140 nodeoffset = fdt_node_offset_by_compat_reg(blob,
141 compat, pcie->dbi_res.start);
147 /* get phandle to iommu controller */
148 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
150 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
151 __func__, pcie->idx);
155 /* set iommu-map row */
156 iommu_map[0] = cpu_to_fdt32(devid);
157 iommu_map[1] = *++prop;
158 iommu_map[2] = cpu_to_fdt32(streamid);
159 iommu_map[3] = cpu_to_fdt32(1);
162 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
165 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
169 static void fdt_fixup_pcie_ls(void *blob)
171 struct udevice *dev, *bus;
172 struct ls_pcie *pcie;
177 /* Scan all known buses */
178 for (pci_find_first_device(&dev);
180 pci_find_next_device(&dev)) {
181 for (bus = dev; device_is_on_pci_bus(bus);)
183 pcie = dev_get_priv(bus);
185 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
187 debug("ERROR: no stream ids free\n");
190 pcie->stream_id_cur++;
193 index = ls_pcie_next_lut_index(pcie);
195 debug("ERROR: no LUT indexes free\n");
199 /* the DT fixup must be relative to the hose first_busno */
200 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
201 /* map PCI b.d.f to streamID in LUT */
202 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
204 /* update msi-map in device tree */
205 fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
207 /* update iommu-map in device tree */
208 fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
211 pcie_board_fix_fdt(blob);
215 static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
221 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
222 pcie->dbi_res.start);
224 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
225 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
226 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
227 svr == SVR_LS2048A || svr == SVR_LS2044A ||
228 svr == SVR_LS2081A || svr == SVR_LS2041A)
229 compat = "fsl,ls2088a-pcie";
231 compat = CONFIG_FSL_PCIE_COMPAT;
233 off = fdt_node_offset_by_compat_reg(blob,
234 compat, pcie->dbi_res.start);
240 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
241 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
243 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
246 static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
250 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
251 pcie->dbi_res.start);
255 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
256 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
258 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
261 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
263 ft_pcie_ep_fix(blob, pcie);
264 ft_pcie_rc_fix(blob, pcie);
267 /* Fixup Kernel DT for PCIe */
268 void ft_pci_setup_ls(void *blob, bd_t *bd)
270 struct ls_pcie *pcie;
272 list_for_each_entry(pcie, &ls_pcie_list, list)
273 ft_pcie_ls_setup(blob, pcie);
275 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
276 fdt_fixup_pcie_ls(blob);
280 #else /* !CONFIG_OF_BOARD_SETUP */
281 void ft_pci_setup_ls(void *blob, bd_t *bd)