3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * Layerscape PCIe driver
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
16 #include "pcie_layerscape.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 LIST_HEAD(ls_pcie_list);
22 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
24 return in_le32(pcie->dbi + offset);
27 static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
30 out_le32(pcie->dbi + offset, value);
33 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
36 return in_be32(pcie->ctrl + offset);
38 return in_le32(pcie->ctrl + offset);
41 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
45 out_be32(pcie->ctrl + offset, value);
47 out_le32(pcie->ctrl + offset, value);
50 static int ls_pcie_ltssm(struct ls_pcie *pcie)
56 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
57 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
58 state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
60 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
66 static int ls_pcie_link_up(struct ls_pcie *pcie)
70 ltssm = ls_pcie_ltssm(pcie);
71 if (ltssm < LTSSM_PCIE_L0)
77 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
79 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
81 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
84 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
86 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
88 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
91 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
92 u64 phys, u64 bus_addr, pci_size_t size)
94 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
95 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
96 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
97 dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
98 dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
99 dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
100 dbi_writel(pcie, type, PCIE_ATU_CR1);
101 dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
104 /* Use bar match mode and MEM type as default */
105 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
108 dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
109 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
110 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
111 dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
112 dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
113 PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
116 static void ls_pcie_dump_atu(struct ls_pcie *pcie)
120 for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
121 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
123 debug("iATU%d:\n", i);
124 debug("\tLOWER PHYS 0x%08x\n",
125 dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
126 debug("\tUPPER PHYS 0x%08x\n",
127 dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
128 debug("\tLOWER BUS 0x%08x\n",
129 dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
130 debug("\tUPPER BUS 0x%08x\n",
131 dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
132 debug("\tLIMIT 0x%08x\n",
133 readl(pcie->dbi + PCIE_ATU_LIMIT));
134 debug("\tCR1 0x%08x\n",
135 dbi_readl(pcie, PCIE_ATU_CR1));
136 debug("\tCR2 0x%08x\n",
137 dbi_readl(pcie, PCIE_ATU_CR2));
141 static void ls_pcie_setup_atu(struct ls_pcie *pcie)
143 struct pci_region *io, *mem, *pref;
144 unsigned long long offset = 0;
149 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
150 offset = LS1021_PCIE_SPACE_OFFSET +
151 LS1021_PCIE_SPACE_SIZE * pcie->idx;
154 /* ATU 0 : OUTBOUND : CFG0 */
155 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
157 pcie->cfg_res.start + offset,
159 fdt_resource_size(&pcie->cfg_res) / 2);
160 /* ATU 1 : OUTBOUND : CFG1 */
161 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
163 pcie->cfg_res.start + offset +
164 fdt_resource_size(&pcie->cfg_res) / 2,
166 fdt_resource_size(&pcie->cfg_res) / 2);
168 pci_get_regions(pcie->bus, &io, &mem, &pref);
169 idx = PCIE_ATU_REGION_INDEX1 + 1;
171 /* Fix the pcie memory map for LS2088A series SoCs */
172 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
173 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
174 svr == SVR_LS2048A || svr == SVR_LS2044A ||
175 svr == SVR_LS2081A || svr == SVR_LS2041A) {
177 io->phys_start = (io->phys_start &
178 (PCIE_PHYS_SIZE - 1)) +
179 LS2088A_PCIE1_PHYS_ADDR +
180 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
182 mem->phys_start = (mem->phys_start &
183 (PCIE_PHYS_SIZE - 1)) +
184 LS2088A_PCIE1_PHYS_ADDR +
185 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
187 pref->phys_start = (pref->phys_start &
188 (PCIE_PHYS_SIZE - 1)) +
189 LS2088A_PCIE1_PHYS_ADDR +
190 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
194 /* ATU : OUTBOUND : IO */
195 ls_pcie_atu_outbound_set(pcie, idx++,
197 io->phys_start + offset,
202 /* ATU : OUTBOUND : MEM */
203 ls_pcie_atu_outbound_set(pcie, idx++,
205 mem->phys_start + offset,
210 /* ATU : OUTBOUND : pref */
211 ls_pcie_atu_outbound_set(pcie, idx++,
213 pref->phys_start + offset,
217 ls_pcie_dump_atu(pcie);
220 /* Return 0 if the address is valid, -errno if not valid */
221 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
223 struct udevice *bus = pcie->bus;
228 if (PCI_BUS(bdf) < bus->seq)
231 if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
234 if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
240 void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
243 struct udevice *bus = pcie->bus;
246 if (PCI_BUS(bdf) == bus->seq)
247 return pcie->dbi + offset;
249 busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
250 PCIE_ATU_DEV(PCI_DEV(bdf)) |
251 PCIE_ATU_FUNC(PCI_FUNC(bdf));
253 if (PCI_BUS(bdf) == bus->seq + 1) {
254 ls_pcie_cfg0_set_busdev(pcie, busdev);
255 return pcie->cfg0 + offset;
257 ls_pcie_cfg1_set_busdev(pcie, busdev);
258 return pcie->cfg1 + offset;
262 static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
263 uint offset, ulong *valuep,
264 enum pci_size_t size)
266 struct ls_pcie *pcie = dev_get_priv(bus);
269 if (ls_pcie_addr_valid(pcie, bdf)) {
270 *valuep = pci_get_ff(size);
274 address = ls_pcie_conf_address(pcie, bdf, offset);
278 *valuep = readb(address);
281 *valuep = readw(address);
284 *valuep = readl(address);
291 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
292 uint offset, ulong value,
293 enum pci_size_t size)
295 struct ls_pcie *pcie = dev_get_priv(bus);
298 if (ls_pcie_addr_valid(pcie, bdf))
301 address = ls_pcie_conf_address(pcie, bdf, offset);
305 writeb(value, address);
308 writew(value, address);
311 writel(value, address);
318 /* Clear multi-function bit */
319 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
321 writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
324 /* Fix class value */
325 static void ls_pcie_fix_class(struct ls_pcie *pcie)
327 writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
330 /* Drop MSG TLP except for Vendor MSG */
331 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
335 val = dbi_readl(pcie, PCIE_STRFMR1);
337 dbi_writel(pcie, val, PCIE_STRFMR1);
340 /* Disable all bars in RC mode */
341 static void ls_pcie_disable_bars(struct ls_pcie *pcie)
345 sriov = in_le32(pcie->dbi + PCIE_SRIOV);
348 * TODO: For PCIe controller with SRIOV, the method to disable bars
349 * is different and more complex, so will add later.
351 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
354 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
355 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
356 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
359 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
361 ls_pcie_setup_atu(pcie);
363 dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
364 ls_pcie_fix_class(pcie);
365 ls_pcie_clear_multifunction(pcie);
366 ls_pcie_drop_msg_tlp(pcie);
367 dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
369 ls_pcie_disable_bars(pcie);
372 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
374 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
376 /* ATU 0 : INBOUND : map BAR0 */
377 ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
378 /* ATU 1 : INBOUND : map BAR1 */
379 phys += PCIE_BAR1_SIZE;
380 ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
381 /* ATU 2 : INBOUND : map BAR2 */
382 phys += PCIE_BAR2_SIZE;
383 ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
384 /* ATU 3 : INBOUND : map BAR4 */
385 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
386 ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
388 /* ATU 0 : OUTBOUND : map MEM */
389 ls_pcie_atu_outbound_set(pcie, 0,
393 CONFIG_SYS_PCI_MEMORY_SIZE);
396 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
397 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
399 /* The least inbound window is 4KiB */
405 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
408 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
411 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
412 writel(0, bar_base + PCI_BASE_ADDRESS_3);
415 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
416 writel(0, bar_base + PCI_BASE_ADDRESS_5);
423 static void ls_pcie_ep_setup_bars(void *bar_base)
425 /* BAR0 - 32bit - 4K configuration */
426 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
427 /* BAR1 - 32bit - 8K MSIX*/
428 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
429 /* BAR2 - 64bit - 4K MEM desciptor */
430 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
431 /* BAR4 - 64bit - 1M MEM*/
432 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
435 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
437 ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
440 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
444 sriov = readl(pcie->dbi + PCIE_SRIOV);
445 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
448 for (pf = 0; pf < PCIE_PF_NUM; pf++) {
449 for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
450 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
453 ls_pcie_ep_setup_bars(pcie->dbi);
454 ls_pcie_ep_setup_atu(pcie);
458 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
460 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
461 ls_pcie_ep_setup_atu(pcie);
464 ls_pcie_ep_enable_cfg(pcie);
467 static int ls_pcie_probe(struct udevice *dev)
469 struct ls_pcie *pcie = dev_get_priv(dev);
470 const void *fdt = gd->fdt_blob;
471 int node = dev_of_offset(dev);
480 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
481 "dbi", &pcie->dbi_res);
483 printf("ls-pcie: resource \"dbi\" not found\n");
487 pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
489 list_add(&pcie->list, &ls_pcie_list);
491 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
492 if (!pcie->enabled) {
493 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
497 pcie->dbi = map_physmem(pcie->dbi_res.start,
498 fdt_resource_size(&pcie->dbi_res),
501 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
502 "lut", &pcie->lut_res);
504 pcie->lut = map_physmem(pcie->lut_res.start,
505 fdt_resource_size(&pcie->lut_res),
508 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
509 "ctrl", &pcie->ctrl_res);
511 pcie->ctrl = map_physmem(pcie->ctrl_res.start,
512 fdt_resource_size(&pcie->ctrl_res),
515 pcie->ctrl = pcie->lut;
518 printf("%s: NOT find CTRL\n", dev->name);
522 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
523 "config", &pcie->cfg_res);
525 printf("%s: resource \"config\" not found\n", dev->name);
530 * Fix the pcie memory map address and PF control registers address
531 * for LS2088A series SoCs
534 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
535 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
536 svr == SVR_LS2048A || svr == SVR_LS2044A ||
537 svr == SVR_LS2081A || svr == SVR_LS2041A) {
538 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
539 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
540 pcie->ctrl = pcie->lut + 0x40000;
543 pcie->cfg0 = map_physmem(pcie->cfg_res.start,
544 fdt_resource_size(&pcie->cfg_res),
546 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
548 pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
550 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
551 dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
552 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
555 header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
556 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
557 printf("PCIe%u: %s %s", pcie->idx, dev->name,
558 ep_mode ? "Endpoint" : "Root Complex");
561 ls_pcie_setup_ep(pcie);
563 ls_pcie_setup_ctrl(pcie);
565 if (!ls_pcie_link_up(pcie)) {
566 /* Let the user know there's no PCIe link */
567 printf(": no link\n");
571 /* Print the negotiated PCIe link width */
572 link_sta = readw(pcie->dbi + PCIE_LINK_STA);
573 printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
574 link_sta & PCIE_LINK_SPEED_MASK);
579 static const struct dm_pci_ops ls_pcie_ops = {
580 .read_config = ls_pcie_read_config,
581 .write_config = ls_pcie_write_config,
584 static const struct udevice_id ls_pcie_ids[] = {
585 { .compatible = "fsl,ls-pcie" },
589 U_BOOT_DRIVER(pci_layerscape) = {
590 .name = "pci_layerscape",
592 .of_match = ls_pcie_ids,
594 .probe = ls_pcie_probe,
595 .priv_auto_alloc_size = sizeof(struct ls_pcie),