1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2019 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
10 #include <asm/arch/fsl_serdes.h>
16 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
18 #include <asm/arch/clock.h>
20 #include "pcie_layerscape.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 LIST_HEAD(ls_pcie_list);
26 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
28 return in_le32(pcie->dbi + offset);
31 static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
34 out_le32(pcie->dbi + offset, value);
37 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
40 return in_be32(pcie->ctrl + offset);
42 return in_le32(pcie->ctrl + offset);
45 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
49 out_be32(pcie->ctrl + offset, value);
51 out_le32(pcie->ctrl + offset, value);
54 static int ls_pcie_ltssm(struct ls_pcie *pcie)
60 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
61 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
62 state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
64 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
70 static int ls_pcie_link_up(struct ls_pcie *pcie)
74 ltssm = ls_pcie_ltssm(pcie);
75 if (ltssm < LTSSM_PCIE_L0)
81 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
83 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
85 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
88 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
90 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
92 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
95 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
96 u64 phys, u64 bus_addr, pci_size_t size)
98 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
99 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
100 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
101 dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
102 dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
103 dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
104 dbi_writel(pcie, type, PCIE_ATU_CR1);
105 dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
108 /* Use bar match mode and MEM type as default */
109 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
112 dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
113 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
114 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
115 dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
116 dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
117 PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
120 static void ls_pcie_dump_atu(struct ls_pcie *pcie)
124 for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
125 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
127 debug("iATU%d:\n", i);
128 debug("\tLOWER PHYS 0x%08x\n",
129 dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
130 debug("\tUPPER PHYS 0x%08x\n",
131 dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
132 debug("\tLOWER BUS 0x%08x\n",
133 dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
134 debug("\tUPPER BUS 0x%08x\n",
135 dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
136 debug("\tLIMIT 0x%08x\n",
137 readl(pcie->dbi + PCIE_ATU_LIMIT));
138 debug("\tCR1 0x%08x\n",
139 dbi_readl(pcie, PCIE_ATU_CR1));
140 debug("\tCR2 0x%08x\n",
141 dbi_readl(pcie, PCIE_ATU_CR2));
145 static void ls_pcie_setup_atu(struct ls_pcie *pcie)
147 struct pci_region *io, *mem, *pref;
148 unsigned long long offset = 0;
153 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
154 offset = LS1021_PCIE_SPACE_OFFSET +
155 LS1021_PCIE_SPACE_SIZE * pcie->idx;
158 /* ATU 0 : OUTBOUND : CFG0 */
159 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
161 pcie->cfg_res.start + offset,
163 fdt_resource_size(&pcie->cfg_res) / 2);
164 /* ATU 1 : OUTBOUND : CFG1 */
165 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
167 pcie->cfg_res.start + offset +
168 fdt_resource_size(&pcie->cfg_res) / 2,
170 fdt_resource_size(&pcie->cfg_res) / 2);
172 pci_get_regions(pcie->bus, &io, &mem, &pref);
173 idx = PCIE_ATU_REGION_INDEX1 + 1;
175 /* Fix the pcie memory map for LS2088A series SoCs */
176 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
177 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
178 svr == SVR_LS2048A || svr == SVR_LS2044A ||
179 svr == SVR_LS2081A || svr == SVR_LS2041A) {
181 io->phys_start = (io->phys_start &
182 (PCIE_PHYS_SIZE - 1)) +
183 LS2088A_PCIE1_PHYS_ADDR +
184 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
186 mem->phys_start = (mem->phys_start &
187 (PCIE_PHYS_SIZE - 1)) +
188 LS2088A_PCIE1_PHYS_ADDR +
189 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
191 pref->phys_start = (pref->phys_start &
192 (PCIE_PHYS_SIZE - 1)) +
193 LS2088A_PCIE1_PHYS_ADDR +
194 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
198 /* ATU : OUTBOUND : IO */
199 ls_pcie_atu_outbound_set(pcie, idx++,
201 io->phys_start + offset,
206 /* ATU : OUTBOUND : MEM */
207 ls_pcie_atu_outbound_set(pcie, idx++,
209 mem->phys_start + offset,
214 /* ATU : OUTBOUND : pref */
215 ls_pcie_atu_outbound_set(pcie, idx++,
217 pref->phys_start + offset,
221 ls_pcie_dump_atu(pcie);
224 /* Return 0 if the address is valid, -errno if not valid */
225 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
227 struct udevice *bus = pcie->bus;
229 if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
235 if (PCI_BUS(bdf) < bus->seq)
238 if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
241 if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
247 int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
248 uint offset, void **paddress)
250 struct ls_pcie *pcie = dev_get_priv(bus);
253 if (ls_pcie_addr_valid(pcie, bdf))
256 if (PCI_BUS(bdf) == bus->seq) {
257 *paddress = pcie->dbi + offset;
261 busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
262 PCIE_ATU_DEV(PCI_DEV(bdf)) |
263 PCIE_ATU_FUNC(PCI_FUNC(bdf));
265 if (PCI_BUS(bdf) == bus->seq + 1) {
266 ls_pcie_cfg0_set_busdev(pcie, busdev);
267 *paddress = pcie->cfg0 + offset;
269 ls_pcie_cfg1_set_busdev(pcie, busdev);
270 *paddress = pcie->cfg1 + offset;
275 static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
276 uint offset, ulong *valuep,
277 enum pci_size_t size)
279 return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
280 bdf, offset, valuep, size);
283 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
284 uint offset, ulong value,
285 enum pci_size_t size)
287 return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
288 bdf, offset, value, size);
291 /* Clear multi-function bit */
292 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
294 writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
297 /* Fix class value */
298 static void ls_pcie_fix_class(struct ls_pcie *pcie)
300 writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
303 /* Drop MSG TLP except for Vendor MSG */
304 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
308 val = dbi_readl(pcie, PCIE_STRFMR1);
310 dbi_writel(pcie, val, PCIE_STRFMR1);
313 /* Disable all bars in RC mode */
314 static void ls_pcie_disable_bars(struct ls_pcie *pcie)
316 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
317 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
318 dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
321 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
323 ls_pcie_setup_atu(pcie);
325 dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
326 ls_pcie_fix_class(pcie);
327 ls_pcie_clear_multifunction(pcie);
328 ls_pcie_drop_msg_tlp(pcie);
329 dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
331 ls_pcie_disable_bars(pcie);
332 pcie->stream_id_cur = 0;
335 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
337 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
339 /* ATU 0 : INBOUND : map BAR0 */
340 ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
341 /* ATU 1 : INBOUND : map BAR1 */
342 phys += PCIE_BAR1_SIZE;
343 ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
344 /* ATU 2 : INBOUND : map BAR2 */
345 phys += PCIE_BAR2_SIZE;
346 ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
347 /* ATU 3 : INBOUND : map BAR4 */
348 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
349 ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
351 /* ATU 0 : OUTBOUND : map MEM */
352 ls_pcie_atu_outbound_set(pcie, 0,
356 CONFIG_SYS_PCI_MEMORY_SIZE);
359 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
360 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
362 /* The least inbound window is 4KiB */
368 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
371 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
374 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
375 writel(0, bar_base + PCI_BASE_ADDRESS_3);
378 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
379 writel(0, bar_base + PCI_BASE_ADDRESS_5);
386 static void ls_pcie_ep_setup_bars(void *bar_base)
388 /* BAR0 - 32bit - 4K configuration */
389 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
390 /* BAR1 - 32bit - 8K MSIX*/
391 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
392 /* BAR2 - 64bit - 4K MEM desciptor */
393 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
394 /* BAR4 - 64bit - 1M MEM*/
395 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
398 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
402 config = ctrl_readl(pcie, PCIE_PF_CONFIG);
403 config |= PCIE_CONFIG_READY;
404 ctrl_writel(pcie, config, PCIE_PF_CONFIG);
407 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
411 sriov = readl(pcie->dbi + PCIE_SRIOV);
412 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
415 for (pf = 0; pf < PCIE_PF_NUM; pf++) {
416 for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
417 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
420 ls_pcie_ep_setup_bars(pcie->dbi);
421 ls_pcie_ep_setup_atu(pcie);
425 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
427 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
428 ls_pcie_ep_setup_atu(pcie);
431 ls_pcie_ep_enable_cfg(pcie);
434 static int ls_pcie_probe(struct udevice *dev)
436 struct ls_pcie *pcie = dev_get_priv(dev);
437 const void *fdt = gd->fdt_blob;
438 int node = dev_of_offset(dev);
446 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
447 "dbi", &pcie->dbi_res);
449 printf("ls-pcie: resource \"dbi\" not found\n");
453 pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
455 list_add(&pcie->list, &ls_pcie_list);
457 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
458 if (!pcie->enabled) {
459 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
463 pcie->dbi = map_physmem(pcie->dbi_res.start,
464 fdt_resource_size(&pcie->dbi_res),
467 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
468 "lut", &pcie->lut_res);
470 pcie->lut = map_physmem(pcie->lut_res.start,
471 fdt_resource_size(&pcie->lut_res),
474 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
475 "ctrl", &pcie->ctrl_res);
477 pcie->ctrl = map_physmem(pcie->ctrl_res.start,
478 fdt_resource_size(&pcie->ctrl_res),
481 pcie->ctrl = pcie->lut;
484 printf("%s: NOT find CTRL\n", dev->name);
488 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
489 "config", &pcie->cfg_res);
491 printf("%s: resource \"config\" not found\n", dev->name);
496 * Fix the pcie memory map address and PF control registers address
497 * for LS2088A series SoCs
500 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
501 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
502 svr == SVR_LS2048A || svr == SVR_LS2044A ||
503 svr == SVR_LS2081A || svr == SVR_LS2041A) {
504 cfg_size = fdt_resource_size(&pcie->cfg_res);
505 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
506 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
507 pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
508 pcie->ctrl = pcie->lut + 0x40000;
511 pcie->cfg0 = map_physmem(pcie->cfg_res.start,
512 fdt_resource_size(&pcie->cfg_res),
514 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
516 pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
518 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
519 dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
520 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
523 pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
525 if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
526 printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
527 ls_pcie_setup_ep(pcie);
529 printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
530 ls_pcie_setup_ctrl(pcie);
533 if (!ls_pcie_link_up(pcie)) {
534 /* Let the user know there's no PCIe link */
535 printf(": no link\n");
539 /* Print the negotiated PCIe link width */
540 link_sta = readw(pcie->dbi + PCIE_LINK_STA);
541 printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
542 link_sta & PCIE_LINK_SPEED_MASK);
547 static const struct dm_pci_ops ls_pcie_ops = {
548 .read_config = ls_pcie_read_config,
549 .write_config = ls_pcie_write_config,
552 static const struct udevice_id ls_pcie_ids[] = {
553 { .compatible = "fsl,ls-pcie" },
557 U_BOOT_DRIVER(pci_layerscape) = {
558 .name = "pci_layerscape",
560 .of_match = ls_pcie_ids,
562 .probe = ls_pcie_probe,
563 .priv_auto_alloc_size = sizeof(struct ls_pcie),