1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2019 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
9 #include <asm/arch/fsl_serdes.h>
15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
17 #include <asm/arch/clock.h>
19 #include "pcie_layerscape.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 LIST_HEAD(ls_pcie_list);
25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
27 return in_le32(pcie->dbi + offset);
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
33 out_le32(pcie->dbi + offset, value);
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
39 return in_be32(pcie->ctrl + offset);
41 return in_le32(pcie->ctrl + offset);
44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
48 out_be32(pcie->ctrl + offset, value);
50 out_le32(pcie->ctrl + offset, value);
53 static int ls_pcie_ltssm(struct ls_pcie *pcie)
59 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
60 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
61 state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
63 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
69 static int ls_pcie_link_up(struct ls_pcie *pcie)
73 ltssm = ls_pcie_ltssm(pcie);
74 if (ltssm < LTSSM_PCIE_L0)
80 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
82 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
84 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
87 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
89 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
91 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
94 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
95 u64 phys, u64 bus_addr, pci_size_t size)
97 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
98 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
99 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
100 dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
101 dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
102 dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
103 dbi_writel(pcie, type, PCIE_ATU_CR1);
104 dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
107 /* Use bar match mode and MEM type as default */
108 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
111 dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
112 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
113 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
114 dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
115 dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
116 PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
119 static void ls_pcie_dump_atu(struct ls_pcie *pcie)
123 for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
124 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
126 debug("iATU%d:\n", i);
127 debug("\tLOWER PHYS 0x%08x\n",
128 dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
129 debug("\tUPPER PHYS 0x%08x\n",
130 dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
131 debug("\tLOWER BUS 0x%08x\n",
132 dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
133 debug("\tUPPER BUS 0x%08x\n",
134 dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
135 debug("\tLIMIT 0x%08x\n",
136 readl(pcie->dbi + PCIE_ATU_LIMIT));
137 debug("\tCR1 0x%08x\n",
138 dbi_readl(pcie, PCIE_ATU_CR1));
139 debug("\tCR2 0x%08x\n",
140 dbi_readl(pcie, PCIE_ATU_CR2));
144 static void ls_pcie_setup_atu(struct ls_pcie *pcie)
146 struct pci_region *io, *mem, *pref;
147 unsigned long long offset = 0;
152 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
153 offset = LS1021_PCIE_SPACE_OFFSET +
154 LS1021_PCIE_SPACE_SIZE * pcie->idx;
157 /* ATU 0 : OUTBOUND : CFG0 */
158 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
160 pcie->cfg_res.start + offset,
162 fdt_resource_size(&pcie->cfg_res) / 2);
163 /* ATU 1 : OUTBOUND : CFG1 */
164 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
166 pcie->cfg_res.start + offset +
167 fdt_resource_size(&pcie->cfg_res) / 2,
169 fdt_resource_size(&pcie->cfg_res) / 2);
171 pci_get_regions(pcie->bus, &io, &mem, &pref);
172 idx = PCIE_ATU_REGION_INDEX1 + 1;
174 /* Fix the pcie memory map for LS2088A series SoCs */
175 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
176 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
177 svr == SVR_LS2048A || svr == SVR_LS2044A ||
178 svr == SVR_LS2081A || svr == SVR_LS2041A) {
180 io->phys_start = (io->phys_start &
181 (PCIE_PHYS_SIZE - 1)) +
182 LS2088A_PCIE1_PHYS_ADDR +
183 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
185 mem->phys_start = (mem->phys_start &
186 (PCIE_PHYS_SIZE - 1)) +
187 LS2088A_PCIE1_PHYS_ADDR +
188 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
190 pref->phys_start = (pref->phys_start &
191 (PCIE_PHYS_SIZE - 1)) +
192 LS2088A_PCIE1_PHYS_ADDR +
193 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
197 /* ATU : OUTBOUND : IO */
198 ls_pcie_atu_outbound_set(pcie, idx++,
200 io->phys_start + offset,
205 /* ATU : OUTBOUND : MEM */
206 ls_pcie_atu_outbound_set(pcie, idx++,
208 mem->phys_start + offset,
213 /* ATU : OUTBOUND : pref */
214 ls_pcie_atu_outbound_set(pcie, idx++,
216 pref->phys_start + offset,
220 ls_pcie_dump_atu(pcie);
223 /* Return 0 if the address is valid, -errno if not valid */
224 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
226 struct udevice *bus = pcie->bus;
228 if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
234 if (PCI_BUS(bdf) < bus->seq)
237 if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
240 if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
246 int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf,
247 uint offset, void **paddress)
249 struct ls_pcie *pcie = dev_get_priv(bus);
252 if (ls_pcie_addr_valid(pcie, bdf))
255 if (PCI_BUS(bdf) == bus->seq) {
256 *paddress = pcie->dbi + offset;
260 busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
261 PCIE_ATU_DEV(PCI_DEV(bdf)) |
262 PCIE_ATU_FUNC(PCI_FUNC(bdf));
264 if (PCI_BUS(bdf) == bus->seq + 1) {
265 ls_pcie_cfg0_set_busdev(pcie, busdev);
266 *paddress = pcie->cfg0 + offset;
268 ls_pcie_cfg1_set_busdev(pcie, busdev);
269 *paddress = pcie->cfg1 + offset;
274 static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
275 uint offset, ulong *valuep,
276 enum pci_size_t size)
278 return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
279 bdf, offset, valuep, size);
282 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
283 uint offset, ulong value,
284 enum pci_size_t size)
286 return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
287 bdf, offset, value, size);
290 /* Clear multi-function bit */
291 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
293 writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
296 /* Fix class value */
297 static void ls_pcie_fix_class(struct ls_pcie *pcie)
299 writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
302 /* Drop MSG TLP except for Vendor MSG */
303 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
307 val = dbi_readl(pcie, PCIE_STRFMR1);
309 dbi_writel(pcie, val, PCIE_STRFMR1);
312 /* Disable all bars in RC mode */
313 static void ls_pcie_disable_bars(struct ls_pcie *pcie)
315 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
316 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
317 dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
320 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
322 ls_pcie_setup_atu(pcie);
324 dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
325 ls_pcie_fix_class(pcie);
326 ls_pcie_clear_multifunction(pcie);
327 ls_pcie_drop_msg_tlp(pcie);
328 dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
330 ls_pcie_disable_bars(pcie);
331 pcie->stream_id_cur = 0;
334 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
336 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
338 /* ATU 0 : INBOUND : map BAR0 */
339 ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
340 /* ATU 1 : INBOUND : map BAR1 */
341 phys += PCIE_BAR1_SIZE;
342 ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
343 /* ATU 2 : INBOUND : map BAR2 */
344 phys += PCIE_BAR2_SIZE;
345 ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
346 /* ATU 3 : INBOUND : map BAR4 */
347 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
348 ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
350 /* ATU 0 : OUTBOUND : map MEM */
351 ls_pcie_atu_outbound_set(pcie, 0,
355 CONFIG_SYS_PCI_MEMORY_SIZE);
358 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
359 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
361 /* The least inbound window is 4KiB */
367 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
370 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
373 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
374 writel(0, bar_base + PCI_BASE_ADDRESS_3);
377 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
378 writel(0, bar_base + PCI_BASE_ADDRESS_5);
385 static void ls_pcie_ep_setup_bars(void *bar_base)
387 /* BAR0 - 32bit - 4K configuration */
388 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
389 /* BAR1 - 32bit - 8K MSIX*/
390 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
391 /* BAR2 - 64bit - 4K MEM desciptor */
392 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
393 /* BAR4 - 64bit - 1M MEM*/
394 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
397 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
401 config = ctrl_readl(pcie, PCIE_PF_CONFIG);
402 config |= PCIE_CONFIG_READY;
403 ctrl_writel(pcie, config, PCIE_PF_CONFIG);
406 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
410 sriov = readl(pcie->dbi + PCIE_SRIOV);
411 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
414 for (pf = 0; pf < PCIE_PF_NUM; pf++) {
415 for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
416 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
419 ls_pcie_ep_setup_bars(pcie->dbi);
420 ls_pcie_ep_setup_atu(pcie);
424 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
426 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
427 ls_pcie_ep_setup_atu(pcie);
430 ls_pcie_ep_enable_cfg(pcie);
433 static int ls_pcie_probe(struct udevice *dev)
435 struct ls_pcie *pcie = dev_get_priv(dev);
436 const void *fdt = gd->fdt_blob;
437 int node = dev_of_offset(dev);
445 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
446 "dbi", &pcie->dbi_res);
448 printf("ls-pcie: resource \"dbi\" not found\n");
452 pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
454 list_add(&pcie->list, &ls_pcie_list);
456 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
457 if (!pcie->enabled) {
458 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
462 pcie->dbi = map_physmem(pcie->dbi_res.start,
463 fdt_resource_size(&pcie->dbi_res),
466 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
467 "lut", &pcie->lut_res);
469 pcie->lut = map_physmem(pcie->lut_res.start,
470 fdt_resource_size(&pcie->lut_res),
473 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
474 "ctrl", &pcie->ctrl_res);
476 pcie->ctrl = map_physmem(pcie->ctrl_res.start,
477 fdt_resource_size(&pcie->ctrl_res),
480 pcie->ctrl = pcie->lut;
483 printf("%s: NOT find CTRL\n", dev->name);
487 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
488 "config", &pcie->cfg_res);
490 printf("%s: resource \"config\" not found\n", dev->name);
495 * Fix the pcie memory map address and PF control registers address
496 * for LS2088A series SoCs
499 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
500 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
501 svr == SVR_LS2048A || svr == SVR_LS2044A ||
502 svr == SVR_LS2081A || svr == SVR_LS2041A) {
503 cfg_size = fdt_resource_size(&pcie->cfg_res);
504 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
505 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
506 pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
507 pcie->ctrl = pcie->lut + 0x40000;
510 pcie->cfg0 = map_physmem(pcie->cfg_res.start,
511 fdt_resource_size(&pcie->cfg_res),
513 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
515 pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
517 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
518 dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
519 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
522 pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
524 if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
525 printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
526 ls_pcie_setup_ep(pcie);
528 printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
529 ls_pcie_setup_ctrl(pcie);
532 if (!ls_pcie_link_up(pcie)) {
533 /* Let the user know there's no PCIe link */
534 printf(": no link\n");
538 /* Print the negotiated PCIe link width */
539 link_sta = readw(pcie->dbi + PCIE_LINK_STA);
540 printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
541 link_sta & PCIE_LINK_SPEED_MASK);
546 static const struct dm_pci_ops ls_pcie_ops = {
547 .read_config = ls_pcie_read_config,
548 .write_config = ls_pcie_write_config,
551 static const struct udevice_id ls_pcie_ids[] = {
552 { .compatible = "fsl,ls-pcie" },
556 U_BOOT_DRIVER(pci_layerscape) = {
557 .name = "pci_layerscape",
559 .of_match = ls_pcie_ids,
561 .probe = ls_pcie_probe,
562 .priv_auto_alloc_size = sizeof(struct ls_pcie),