2 * Freescale i.MX6 PCI Express Root-Complex driver
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 * Based on upstream Linux kernel driver:
7 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
8 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/arch/clock.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/crm_regs.h>
20 #include <asm/sizes.h>
23 #define PCI_ACCESS_READ 0
24 #define PCI_ACCESS_WRITE 1
26 #define MX6_DBI_ADDR 0x01ffc000
27 #define MX6_DBI_SIZE 0x4000
28 #define MX6_IO_ADDR 0x01000000
29 #define MX6_IO_SIZE 0x100000
30 #define MX6_MEM_ADDR 0x01100000
31 #define MX6_MEM_SIZE 0xe00000
32 #define MX6_ROOT_ADDR 0x01f00000
33 #define MX6_ROOT_SIZE 0xfc000
35 /* PCIe Port Logic registers (memory-mapped) */
36 #define PL_OFFSET 0x700
37 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
38 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
39 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
40 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
42 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
43 #define PCIE_PHY_CTRL_DATA_LOC 0
44 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
45 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
46 #define PCIE_PHY_CTRL_WR_LOC 18
47 #define PCIE_PHY_CTRL_RD_LOC 19
49 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
50 #define PCIE_PHY_STAT_DATA_LOC 0
51 #define PCIE_PHY_STAT_ACK_LOC 16
53 /* PHY registers (not memory-mapped) */
54 #define PCIE_PHY_RX_ASIC_OUT 0x100D
56 #define PHY_RX_OVRD_IN_LO 0x1005
57 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
58 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
61 #define PCIE_ATU_VIEWPORT 0x900
62 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
63 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
64 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
65 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
66 #define PCIE_ATU_CR1 0x904
67 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
68 #define PCIE_ATU_TYPE_IO (0x2 << 0)
69 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
70 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
71 #define PCIE_ATU_CR2 0x908
72 #define PCIE_ATU_ENABLE (0x1 << 31)
73 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
74 #define PCIE_ATU_LOWER_BASE 0x90C
75 #define PCIE_ATU_UPPER_BASE 0x910
76 #define PCIE_ATU_LIMIT 0x914
77 #define PCIE_ATU_LOWER_TARGET 0x918
78 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
79 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
80 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
81 #define PCIE_ATU_UPPER_TARGET 0x91C
84 * PHY access functions
86 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
89 u32 max_iterations = 10;
93 val = readl(dbi_base + PCIE_PHY_STAT);
94 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
101 } while (wait_counter < max_iterations);
106 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
111 val = addr << PCIE_PHY_CTRL_DATA_LOC;
112 writel(val, dbi_base + PCIE_PHY_CTRL);
114 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
115 writel(val, dbi_base + PCIE_PHY_CTRL);
117 ret = pcie_phy_poll_ack(dbi_base, 1);
121 val = addr << PCIE_PHY_CTRL_DATA_LOC;
122 writel(val, dbi_base + PCIE_PHY_CTRL);
124 ret = pcie_phy_poll_ack(dbi_base, 0);
131 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
132 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
137 ret = pcie_phy_wait_ack(dbi_base, addr);
141 /* assert Read signal */
142 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
143 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
145 ret = pcie_phy_poll_ack(dbi_base, 1);
149 val = readl(dbi_base + PCIE_PHY_STAT);
150 *data = val & 0xffff;
152 /* deassert Read signal */
153 writel(0x00, dbi_base + PCIE_PHY_CTRL);
155 ret = pcie_phy_poll_ack(dbi_base, 0);
162 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
169 ret = pcie_phy_wait_ack(dbi_base, addr);
173 var = data << PCIE_PHY_CTRL_DATA_LOC;
174 writel(var, dbi_base + PCIE_PHY_CTRL);
177 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
178 writel(var, dbi_base + PCIE_PHY_CTRL);
180 ret = pcie_phy_poll_ack(dbi_base, 1);
184 /* deassert cap data */
185 var = data << PCIE_PHY_CTRL_DATA_LOC;
186 writel(var, dbi_base + PCIE_PHY_CTRL);
188 /* wait for ack de-assertion */
189 ret = pcie_phy_poll_ack(dbi_base, 0);
193 /* assert wr signal */
194 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
195 writel(var, dbi_base + PCIE_PHY_CTRL);
198 ret = pcie_phy_poll_ack(dbi_base, 1);
202 /* deassert wr signal */
203 var = data << PCIE_PHY_CTRL_DATA_LOC;
204 writel(var, dbi_base + PCIE_PHY_CTRL);
206 /* wait for ack de-assertion */
207 ret = pcie_phy_poll_ack(dbi_base, 0);
211 writel(0x0, dbi_base + PCIE_PHY_CTRL);
216 static int imx6_pcie_link_up(void)
221 /* link is debug bit 36, debug register 1 starts at bit 32 */
222 rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
223 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
224 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
228 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
229 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
230 * If (MAC/LTSSM.state == Recovery.RcvrLock)
231 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
234 pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
235 ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
243 printf("transition to gen2 is stuck, reset PHY!\n");
245 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
246 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
247 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
251 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
252 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
253 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
261 static int imx_pcie_regions_setup(void)
264 * i.MX6 defines 16MB in the AXI address map for PCIe.
266 * That address space excepted the pcie registers is
267 * split and defined into different regions by iATU,
268 * with sizes and offsets as follows:
270 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
271 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
272 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
275 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
276 setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
277 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
279 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
280 setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
281 PCI_CLASS_BRIDGE_PCI << 16);
283 /* Region #0 is used for Outbound CFG space access. */
284 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
286 writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
287 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
288 writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
290 writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
291 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
292 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
293 writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
299 * PCI Express accessors
301 static uint32_t get_bus_address(pci_dev_t d, int where)
305 /* Reconfigure Region #0 */
306 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
309 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
311 writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
313 if (PCI_BUS(d) == 0) {
314 va_address = MX6_DBI_ADDR;
316 writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
317 va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
320 va_address += (where & ~0x3);
325 static int imx_pcie_addr_valid(pci_dev_t d)
327 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
329 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
335 * Replace the original ARM DABT handler with a simple jump-back one.
337 * The problem here is that if we have a PCIe bridge attached to this PCIe
338 * controller, but no PCIe device is connected to the bridges' downstream
339 * port, the attempt to read/write from/to the config space will produce
340 * a DABT. This is a behavior of the controller and can not be disabled
343 * To work around the problem, we backup the current DABT handler address
344 * and replace it with our own DABT handler, which only bounces right back
347 static void imx_pcie_fix_dabt_handler(bool set)
349 extern uint32_t *_data_abort;
350 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
352 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
353 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
355 static uint32_t data_abort_backup;
358 data_abort_backup = *data_abort_addr;
359 *data_abort_addr = data_abort_bounce_addr;
361 *data_abort_addr = data_abort_backup;
365 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
371 ret = imx_pcie_addr_valid(d);
377 va_address = get_bus_address(d, where);
380 * Read the PCIe config space. We must replace the DABT handler
381 * here in case we got data abort from the PCIe controller, see
382 * imx_pcie_fix_dabt_handler() description. Note that writing the
383 * "val" with valid value is also imperative here as in case we
384 * did got DABT, the val would contain random value.
386 imx_pcie_fix_dabt_handler(true);
387 writel(0xffffffff, val);
388 *val = readl(va_address);
389 imx_pcie_fix_dabt_handler(false);
394 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
397 uint32_t va_address = 0;
400 ret = imx_pcie_addr_valid(d);
404 va_address = get_bus_address(d, where);
407 * Write the PCIe config space. We must replace the DABT handler
408 * here in case we got data abort from the PCIe controller, see
409 * imx_pcie_fix_dabt_handler() description.
411 imx_pcie_fix_dabt_handler(true);
412 writel(val, va_address);
413 imx_pcie_fix_dabt_handler(false);
421 static int imx6_pcie_assert_core_reset(void)
423 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
425 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
426 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
431 static int imx6_pcie_init_phy(void)
433 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
435 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
437 clrsetbits_le32(&iomuxc_regs->gpr[12],
438 IOMUXC_GPR12_DEVICE_TYPE_MASK,
439 IOMUXC_GPR12_DEVICE_TYPE_RC);
440 clrsetbits_le32(&iomuxc_regs->gpr[12],
441 IOMUXC_GPR12_LOS_LEVEL_MASK,
442 IOMUXC_GPR12_LOS_LEVEL_9);
444 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
445 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
446 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
447 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
448 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
449 &iomuxc_regs->gpr[8]);
454 __weak int imx6_pcie_toggle_reset(void)
457 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
458 * for detailed understanding of the PCIe CR reset logic.
460 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
461 * design does not conform to the specification. You must wait at
462 * least 20 mS after de-asserting the #PERST so the EP device can
463 * do self-initialisation.
465 * In case your #PERST pin is connected to a plain GPIO pin of the
466 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
467 * configuration file and the condition below will handle the rest
468 * of the reset toggling.
470 * In case your #PERST toggling logic is more complex, for example
471 * connected via CPLD or somesuch, you can override this function
472 * in your board file and implement reset logic as needed. You must
473 * not forget to wait at least 20 mS after de-asserting #PERST in
474 * this case either though.
476 * In case your #PERST line of the PCIe EP device is not connected
477 * at all, your design is broken and you should fix your design,
478 * otherwise you will observe problems like for example the link
479 * not coming up after rebooting the system back from running Linux
480 * that uses the PCIe as well OR the PCIe link might not come up in
481 * Linux at all in the first place since it's in some non-reset
482 * state due to being previously used in U-Boot.
484 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
485 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
487 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
490 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
495 static int imx6_pcie_deassert_core_reset(void)
497 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
499 /* FIXME: Power-up GPIO goes here. */
502 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
503 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
508 * Wait for the clock to settle a bit, when the clock are sourced
509 * from the CPU, we need about 30mS to settle.
513 imx6_pcie_toggle_reset();
518 static int imx_pcie_link_up(void)
520 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
524 imx6_pcie_assert_core_reset();
525 imx6_pcie_init_phy();
526 imx6_pcie_deassert_core_reset();
528 imx_pcie_regions_setup();
531 * FIXME: Force the PCIe RC to Gen1 operation
532 * The RC must be forced into Gen1 mode before bringing the link
533 * up, otherwise no downstream devices are detected. After the
534 * link is up, a managed Gen1->Gen2 transition can be initiated.
536 tmp = readl(MX6_DBI_ADDR + 0x7c);
539 writel(tmp, MX6_DBI_ADDR + 0x7c);
541 /* LTSSM enable, starting link. */
542 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
544 while (!imx6_pcie_link_up()) {
548 debug("phy link never came up\n");
549 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
550 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
551 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
559 void imx_pcie_init(void)
561 /* Static instance of the controller. */
562 static struct pci_controller pcc;
563 struct pci_controller *hose = &pcc;
566 memset(&pcc, 0, sizeof(pcc));
569 pci_set_region(&hose->regions[0],
570 MX6_IO_ADDR, MX6_IO_ADDR,
571 MX6_IO_SIZE, PCI_REGION_IO);
573 /* PCI memory space */
574 pci_set_region(&hose->regions[1],
575 MX6_MEM_ADDR, MX6_MEM_ADDR,
576 MX6_MEM_SIZE, PCI_REGION_MEM);
578 /* System memory space */
579 pci_set_region(&hose->regions[2],
580 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
581 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
583 hose->region_count = 3;
586 pci_hose_read_config_byte_via_dword,
587 pci_hose_read_config_word_via_dword,
588 imx_pcie_read_config,
589 pci_hose_write_config_byte_via_dword,
590 pci_hose_write_config_word_via_dword,
591 imx_pcie_write_config);
593 /* Start the controller. */
594 ret = imx_pcie_link_up();
597 pci_register_hose(hose);
598 hose->last_busno = pci_hose_scan(hose);
602 /* Probe function. */
603 void pci_init_board(void)