1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
6 * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 #include <asm/fsl_pci.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/global_data.h>
18 #include <linux/delay.h>
20 #include <dm/device_compat.h>
22 LIST_HEAD(fsl_pcie_list);
24 static int fsl_pcie_link_up(struct fsl_pcie *pcie);
26 static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
28 struct udevice *bus = pcie->bus;
33 if (PCI_BUS(bdf) < dev_seq(bus))
36 if (PCI_BUS(bdf) > dev_seq(bus) && (!fsl_pcie_link_up(pcie) || pcie->mode))
39 if (PCI_BUS(bdf) == dev_seq(bus) && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
42 if (PCI_BUS(bdf) == (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
48 static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
49 uint offset, ulong *valuep,
52 struct fsl_pcie *pcie = dev_get_priv(bus);
53 ccsr_fsl_pci_t *regs = pcie->regs;
56 if (fsl_pcie_addr_valid(pcie, bdf)) {
57 *valuep = pci_get_ff(size);
61 val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
62 PCI_DEV(bdf), PCI_FUNC(bdf),
64 out_be32(®s->cfg_addr, val);
70 *valuep = in_8((u8 *)®s->cfg_data + (offset & 3));
73 *valuep = in_le16((u16 *)((u8 *)®s->cfg_data +
77 *valuep = in_le32(®s->cfg_data);
84 static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
85 uint offset, ulong value,
88 struct fsl_pcie *pcie = dev_get_priv(bus);
89 ccsr_fsl_pci_t *regs = pcie->regs;
95 if (fsl_pcie_addr_valid(pcie, bdf))
98 val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
99 PCI_DEV(bdf), PCI_FUNC(bdf),
101 out_be32(®s->cfg_addr, val);
108 out_8((u8 *)®s->cfg_data + (offset & 3), val_8);
112 out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16);
116 out_le32(®s->cfg_data, val_32);
123 static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
124 ulong *valuep, enum pci_size_t size)
127 struct udevice *bus = pcie->bus;
129 ret = fsl_pcie_read_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
130 offset, valuep, size);
135 static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
136 ulong value, enum pci_size_t size)
138 struct udevice *bus = pcie->bus;
140 return fsl_pcie_write_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
141 offset, value, size);
144 static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
150 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
156 static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
162 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
168 static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
174 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
180 static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
183 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
186 static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
189 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
192 static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
195 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
198 static int fsl_pcie_link_up(struct fsl_pcie *pcie)
200 ccsr_fsl_pci_t *regs = pcie->regs;
203 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
204 ltssm = (in_be32(®s->pex_csr0)
205 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
206 return ltssm == LTSSM_L0_REV3;
209 fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
211 return ltssm == LTSSM_L0;
214 static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
218 fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
220 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
223 static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
225 struct pci_region *io, *mem, *pref;
227 pci_get_regions(pcie->bus, &io, &mem, &pref);
230 set_next_law(mem->phys_start,
231 law_size_bits(mem->size),
235 set_next_law(io->phys_start,
236 law_size_bits(io->size),
242 static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
244 ccsr_fsl_pci_t *regs = pcie->regs;
246 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
247 setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY);
251 fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
254 static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
255 int type, u64 phys, u64 bus_addr,
258 ccsr_fsl_pci_t *regs = pcie->regs;
259 pot_t *po = ®s->pot[idx];
265 out_be32(&po->powbar, phys >> 12);
266 out_be32(&po->potar, bus_addr >> 12);
267 #ifdef CONFIG_SYS_PCI_64BIT
268 out_be32(&po->potear, bus_addr >> 44);
270 out_be32(&po->potear, 0);
273 sz = (__ilog2_u64((u64)size) - 1);
276 if (type == PCI_REGION_IO)
277 war |= POWAR_IO_READ | POWAR_IO_WRITE;
279 war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
281 out_be32(&po->powar, war);
286 static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
287 bool pf, u64 phys, u64 bus_addr,
290 ccsr_fsl_pci_t *regs = pcie->regs;
291 pit_t *pi = ®s->pit[idx];
292 u32 sz = (__ilog2_u64(size) - 1);
293 u32 flag = PIWAR_LOCAL;
298 out_be32(&pi->pitar, phys >> 12);
299 out_be32(&pi->piwbar, bus_addr >> 12);
301 #ifdef CONFIG_SYS_PCI_64BIT
302 out_be32(&pi->piwbear, bus_addr >> 44);
304 out_be32(&pi->piwbear, 0);
307 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
311 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
314 out_be32(&pi->piwar, flag | sz);
319 static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
321 struct pci_region *io, *mem, *pref;
322 int idx = 1; /* skip 0 */
324 pci_get_regions(pcie->bus, &io, &mem, &pref);
327 /* ATU : OUTBOUND : IO */
328 fsl_pcie_setup_outbound_win(pcie, idx++,
335 /* ATU : OUTBOUND : MEM */
336 fsl_pcie_setup_outbound_win(pcie, idx++,
344 static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
346 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
347 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
348 u64 sz = min((u64)gd->ram_size, (1ull << 32));
352 if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
357 pci_sz = 1ull << __ilog2_u64(sz);
359 dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
360 (u64)bus_start, (u64)phys_start, (u64)sz);
362 /* if we aren't an exact power of two match, pci_sz is smaller
363 * round it up to the next power of two. We report the actual
364 * size to pci region tracking.
367 sz = 2ull << __ilog2_u64(sz);
369 fsl_pcie_setup_inbound_win(pcie, idx--, true,
370 CONFIG_SYS_PCI_MEMORY_PHYS,
371 CONFIG_SYS_PCI_MEMORY_BUS, sz);
372 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
374 * On 64-bit capable systems, set up a mapping for all of DRAM
375 * in high pci address space.
377 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
378 /* round up to the next largest power of two */
379 if (gd->ram_size > pci_sz)
380 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
382 dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
383 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
384 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
386 fsl_pcie_setup_inbound_win(pcie, idx--, true,
387 CONFIG_SYS_PCI_MEMORY_PHYS,
388 CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
394 static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
396 fsl_pcie_setup_outbound_wins(pcie);
397 fsl_pcie_setup_inbound_wins(pcie);
402 static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie,
407 fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val);
412 fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val);
415 static int fsl_pcie_init_port(struct fsl_pcie *pcie)
417 ccsr_fsl_pci_t *regs = pcie->regs;
421 fsl_pcie_init_atmu(pcie);
423 #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
425 fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
427 fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
431 #ifdef CONFIG_FSL_PCIE_RESET
435 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
436 /* assert PCIe reset */
437 setbits_be32(®s->pdb_stat, 0x08000000);
438 (void)in_be32(®s->pdb_stat);
440 /* clear PCIe reset */
441 clrbits_be32(®s->pdb_stat, 0x08000000);
443 for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
446 fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
448 /* assert PCIe reset */
449 setbits_be32(®s->pdb_stat, 0x08000000);
450 (void)in_be32(®s->pdb_stat);
452 /* clear PCIe reset */
453 clrbits_be32(®s->pdb_stat, 0x08000000);
455 for (i = 0; i < 100 &&
456 !fsl_pcie_link_up(pcie); i++)
462 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
463 if (!fsl_pcie_link_up(pcie)) {
464 serdes_corenet_t *srds_regs;
466 srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
467 val_32 = in_be32(&srds_regs->srdspccr0);
469 if ((val_32 >> 28) == 3) {
472 out_be32(&srds_regs->srdspccr0, 2 << 28);
473 setbits_be32(®s->pdb_stat, 0x08000000);
474 in_be32(®s->pdb_stat);
476 clrbits_be32(®s->pdb_stat, 0x08000000);
478 for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
485 * The Read-Only Write Enable bit defaults to 1 instead of 0.
486 * Set to 0 to protect the read-only registers.
488 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
489 fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
493 * Enable All Error Interrupts except
494 * - Master abort (pci)
495 * - Master PERR (pci)
498 out_be32(®s->peer, ~0x20140);
500 /* set URR, FER, NFER (but not CER) */
501 fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
503 fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
505 /* Clear all error indications */
506 out_be32(®s->pme_msg_det, 0xffffffff);
507 out_be32(®s->pme_msg_int_en, 0xffffffff);
508 out_be32(®s->pedr, 0xffffffff);
510 fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
512 fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
514 fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
516 fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
521 static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
526 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
527 classcode_reg = PCI_CLASS_REVISION;
528 fsl_pcie_dbi_read_only_reg_write_enable(pcie, true);
530 classcode_reg = CSR_CLASSCODE;
533 fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
535 val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
536 fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
538 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
539 fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
544 static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
546 return fsl_pcie_fixup_classcode(pcie);
549 static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
551 fsl_pcie_config_ready(pcie);
556 static int fsl_pcie_probe(struct udevice *dev)
558 struct fsl_pcie *pcie = dev_get_priv(dev);
559 ccsr_fsl_pci_t *regs = pcie->regs;
563 pcie->block_rev = in_be32(®s->block_rev1);
565 list_add(&pcie->list, &fsl_pcie_list);
566 pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
567 if (!pcie->enabled) {
568 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
572 fsl_pcie_setup_law(pcie);
574 pcie->mode = fsl_pcie_is_agent(pcie);
576 fsl_pcie_init_port(pcie);
578 printf("PCIe%d: %s ", pcie->idx, dev->name);
582 fsl_pcie_init_ep(pcie);
584 printf("Root Complex");
585 fsl_pcie_init_rc(pcie);
588 if (!fsl_pcie_link_up(pcie)) {
589 printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
593 fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
594 printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
599 static int fsl_pcie_of_to_plat(struct udevice *dev)
601 struct fsl_pcie *pcie = dev_get_priv(dev);
602 struct fsl_pcie_data *info;
605 pcie->regs = dev_remap_addr(dev);
607 pr_err("\"reg\" resource not found\n");
611 ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
613 pr_err("\"law_trgt_if\" not found\n");
617 info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
619 pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
620 info->block_offset) / info->stride;
625 static const struct dm_pci_ops fsl_pcie_ops = {
626 .read_config = fsl_pcie_read_config,
627 .write_config = fsl_pcie_write_config,
630 static struct fsl_pcie_data p1_p2_data = {
631 .block_offset = 0xa000,
632 .block_offset_mask = 0xffff,
636 static struct fsl_pcie_data p2041_data = {
637 .block_offset = 0x200000,
638 .block_offset_mask = 0x3fffff,
642 static struct fsl_pcie_data t2080_data = {
643 .block_offset = 0x240000,
644 .block_offset_mask = 0x3fffff,
648 static const struct udevice_id fsl_pcie_ids[] = {
649 { .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data },
650 { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
651 { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
652 { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
653 { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
654 { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
655 { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
656 { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
657 { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
658 { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
662 U_BOOT_DRIVER(fsl_pcie) = {
665 .of_match = fsl_pcie_ids,
666 .ops = &fsl_pcie_ops,
667 .of_to_plat = fsl_pcie_of_to_plat,
668 .probe = fsl_pcie_probe,
669 .priv_auto = sizeof(struct fsl_pcie),