1 // SPDX-License-Identifier: GPL-2.0
3 * Generic PCIE host provided by e.g. QEMU
5 * Heavily based on drivers/pci/pcie_xilinx.c
7 * Copyright (C) 2016 Imagination Technologies
13 #include <asm/global_data.h>
20 * struct generic_ecam_pcie - generic_ecam PCIe controller state
21 * @cfg_base: The base address of memory mapped configuration space
23 struct generic_ecam_pcie {
30 * pci_generic_ecam_conf_address() - Calculate the address of a config access
31 * @bus: Pointer to the PCI bus
32 * @bdf: Identifies the PCIe device to access
33 * @offset: The offset into the device's configuration space
34 * @paddress: Pointer to the pointer to write the calculates address to
36 * Calculates the address that should be accessed to perform a PCIe
37 * configuration space access for a given device identified by the PCIe
38 * controller device @pcie and the bus, device & function numbers in @bdf. If
39 * access to the device is not valid then the function will return an error
40 * code. Otherwise the address to access will be written to the pointer pointed
43 static int pci_generic_ecam_conf_address(const struct udevice *bus,
44 pci_dev_t bdf, uint offset,
47 struct generic_ecam_pcie *pcie = dev_get_priv(bus);
50 addr = pcie->cfg_base;
52 if (dev_get_driver_data(bus) == TYPE_PCI) {
53 addr += ((PCI_BUS(bdf) - pcie->first_busno) << 16) |
54 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | offset;
56 addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - pcie->first_busno,
57 PCI_DEV(bdf), PCI_FUNC(bdf), offset);
64 static bool pci_generic_ecam_addr_valid(const struct udevice *bus,
67 struct generic_ecam_pcie *pcie = dev_get_priv(bus);
68 int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
70 return (PCI_BUS(bdf) >= pcie->first_busno &&
71 PCI_BUS(bdf) < pcie->first_busno + num_buses);
75 * pci_generic_ecam_read_config() - Read from configuration space
76 * @bus: Pointer to the PCI bus
77 * @bdf: Identifies the PCIe device to access
78 * @offset: The offset into the device's configuration space
79 * @valuep: A pointer at which to store the read value
80 * @size: Indicates the size of access to perform
82 * Read a value of size @size from offset @offset within the configuration
83 * space of the device identified by the bus, device & function numbers in @bdf
84 * on the PCI bus @bus.
86 static int pci_generic_ecam_read_config(const struct udevice *bus,
87 pci_dev_t bdf, uint offset,
88 ulong *valuep, enum pci_size_t size)
90 if (!pci_generic_ecam_addr_valid(bus, bdf)) {
91 *valuep = pci_get_ff(size);
95 return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
96 bdf, offset, valuep, size);
100 * pci_generic_ecam_write_config() - Write to configuration space
101 * @bus: Pointer to the PCI bus
102 * @bdf: Identifies the PCIe device to access
103 * @offset: The offset into the device's configuration space
104 * @value: The value to write
105 * @size: Indicates the size of access to perform
107 * Write the value @value of size @size from offset @offset within the
108 * configuration space of the device identified by the bus, device & function
109 * numbers in @bdf on the PCI bus @bus.
111 static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
112 uint offset, ulong value,
113 enum pci_size_t size)
115 if (!pci_generic_ecam_addr_valid(bus, bdf))
118 return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
119 bdf, offset, value, size);
123 * pci_generic_ecam_of_to_plat() - Translate from DT to device state
124 * @dev: A pointer to the device being operated on
126 * Translate relevant data from the device tree pertaining to device @dev into
127 * state that the driver will later make use of. This state is stored in the
128 * device's private data structure.
130 * Return: 0 on success, else -EINVAL
132 static int pci_generic_ecam_of_to_plat(struct udevice *dev)
134 struct generic_ecam_pcie *pcie = dev_get_priv(dev);
135 struct fdt_resource reg_res;
136 DECLARE_GLOBAL_DATA_PTR;
139 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
142 pr_err("\"reg\" resource not found\n");
146 pcie->size = fdt_resource_size(®_res);
147 pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
152 static int pci_generic_ecam_probe(struct udevice *dev)
154 struct generic_ecam_pcie *pcie = dev_get_priv(dev);
156 pcie->first_busno = dev_seq(dev);
161 static const struct dm_pci_ops pci_generic_ecam_ops = {
162 .read_config = pci_generic_ecam_read_config,
163 .write_config = pci_generic_ecam_write_config,
166 static const struct udevice_id pci_generic_ecam_ids[] = {
167 { .compatible = "pci-host-ecam-generic" /* PCI-E */ },
168 { .compatible = "pci-host-cam-generic", .data = TYPE_PCI },
172 U_BOOT_DRIVER(pci_generic_ecam) = {
173 .name = "pci_generic_ecam",
175 .of_match = pci_generic_ecam_ids,
176 .ops = &pci_generic_ecam_ops,
177 .probe = pci_generic_ecam_probe,
178 .of_to_plat = pci_generic_ecam_of_to_plat,
179 .priv_auto = sizeof(struct generic_ecam_pcie),