1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip DesignWare based PCIe host controller driver
5 * Copyright (c) 2021 Rockchip, Inc.
11 #include <generic-phy.h>
13 #include <power-domain.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/global_data.h>
19 #include <asm-generic/gpio.h>
20 #include <dm/device_compat.h>
21 #include <linux/iopoll.h>
22 #include <linux/delay.h>
23 #include <power/regulator.h>
25 #include "pcie_dw_common.h"
27 DECLARE_GLOBAL_DATA_PTR;
30 * struct rk_pcie - RK DW PCIe controller state
32 * @vpcie3v3: The 3.3v power supply for slot
33 * @apb_base: The base address of vendor regs
34 * @rst_gpio: The #PERST signal for slot
37 /* Must be first member of the struct */
39 struct udevice *vpcie3v3;
43 struct reset_ctl_bulk rsts;
44 struct gpio_desc rst_gpio;
47 /* Parameters for the waiting for iATU enabled routine */
48 #define PCIE_CLIENT_GENERAL_DEBUG 0x104
49 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
50 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
51 #define PCIE_CLIENT_LTSSM_STATUS 0x300
52 #define SMLH_LINKUP BIT(16)
53 #define RDLH_LINKUP BIT(17)
54 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
55 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
56 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
57 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
58 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
59 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
60 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
61 #define PCIE_CLIENT_DBF_EN 0xffff0003
63 /* Parameters for the waiting for #perst signal */
66 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
68 if ((uintptr_t)addr & (size - 1)) {
75 } else if (size == 2) {
77 } else if (size == 1) {
87 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
89 if ((uintptr_t)addr & (size - 1))
104 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base,
105 u32 reg, size_t size)
110 ret = rk_pcie_read(base + reg, size, &val);
112 dev_err(rk_pcie->dw.dev, "Read APB address failed\n");
117 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base,
118 u32 reg, size_t size, u32 val)
122 ret = rk_pcie_write(base + reg, size, val);
124 dev_err(rk_pcie->dw.dev, "Write APB address failed\n");
128 * rk_pcie_readl_apb() - Read vendor regs
130 * @rk_pcie: Pointer to the PCI controller state
131 * @reg: Offset of regs
133 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
135 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4);
139 * rk_pcie_writel_apb() - Write vendor regs
141 * @rk_pcie: Pointer to the PCI controller state
142 * @reg: Offset of regs
143 * @val: Value to be writen
145 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
148 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
152 * rk_pcie_configure() - Configure link capabilities and speed
154 * @rk_pcie: Pointer to the PCI controller state
155 * @cap_speed: The capabilities and speed to configure
157 * Configure the link capabilities and speed in the PCIe root complex.
159 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
161 dw_pcie_dbi_write_enable(&pci->dw, true);
163 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
164 TARGET_LINK_SPEED_MASK, cap_speed);
166 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
167 TARGET_LINK_SPEED_MASK, cap_speed);
169 dw_pcie_dbi_write_enable(&pci->dw, false);
172 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
174 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0,
175 PCIE_CLIENT_DBG_TRANSITION_DATA);
176 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1,
177 PCIE_CLIENT_DBG_TRANSITION_DATA);
178 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0,
179 PCIE_CLIENT_DBG_TRANSITION_DATA);
180 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1,
181 PCIE_CLIENT_DBG_TRANSITION_DATA);
182 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON,
186 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
190 debug("ltssm = 0x%x\n",
191 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
192 for (loop = 0; loop < 64; loop++)
193 debug("fifo_status = 0x%x\n",
194 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
197 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie)
199 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0);
202 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie)
204 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008);
207 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
209 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
212 static int is_link_up(struct rk_pcie *priv)
216 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS);
217 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 &&
218 (val & GENMASK(5, 0)) == 0x11)
225 * rk_pcie_link_up() - Wait for the link to come up
227 * @rk_pcie: Pointer to the PCI controller state
228 * @cap_speed: Desired link speed
230 * Return: 1 (true) for active line and negetive (false) for no link (timeout)
232 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
236 if (is_link_up(priv)) {
237 printf("PCI Link already up before configuration!\n");
241 /* DW pre link configurations */
242 rk_pcie_configure(priv, cap_speed);
244 /* Rest the device */
245 if (dm_gpio_is_valid(&priv->rst_gpio)) {
246 dm_gpio_set_value(&priv->rst_gpio, 0);
248 * Minimal is 100ms from spec but we see
249 * some wired devices need much more, such as 600ms.
250 * Add a enough delay to cover all cases.
252 udelay(MACRO_US * 1000);
253 dm_gpio_set_value(&priv->rst_gpio, 1);
256 rk_pcie_disable_ltssm(priv);
257 rk_pcie_link_status_clear(priv);
258 rk_pcie_enable_debug(priv);
261 rk_pcie_enable_ltssm(priv);
263 for (retries = 0; retries < 5; retries++) {
264 if (is_link_up(priv)) {
265 dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
266 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
267 rk_pcie_debug_dump(priv);
271 dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
272 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
273 rk_pcie_debug_dump(priv);
274 udelay(MACRO_US * 1000);
277 dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
278 /* Link maybe in Gen switch recovery but we need to wait more 1s */
279 udelay(MACRO_US * 1000);
283 static int rockchip_pcie_init_port(struct udevice *dev)
287 struct rk_pcie *priv = dev_get_priv(dev);
289 /* Set power and maybe external ref clk input */
290 if (priv->vpcie3v3) {
291 ret = regulator_set_value(priv->vpcie3v3, 3300000);
293 dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n",
299 udelay(MACRO_US * 1000);
301 ret = generic_phy_init(&priv->phy);
303 dev_err(dev, "failed to init phy (ret=%d)\n", ret);
307 ret = generic_phy_power_on(&priv->phy);
309 dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
313 ret = reset_deassert_bulk(&priv->rsts);
315 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);
316 goto err_power_off_phy;
319 ret = clk_enable_bulk(&priv->clks);
321 dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
322 goto err_deassert_bulk;
325 /* LTSSM EN ctrl mode */
326 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
327 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
328 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val);
331 rk_pcie_writel_apb(priv, 0x0, 0xf00040);
332 pcie_dw_setup_host(&priv->dw);
334 ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
340 clk_disable_bulk(&priv->clks);
342 reset_assert_bulk(&priv->rsts);
344 generic_phy_power_off(&priv->phy);
346 generic_phy_exit(&priv->phy);
351 static int rockchip_pcie_parse_dt(struct udevice *dev)
353 struct rk_pcie *priv = dev_get_priv(dev);
356 priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
357 if (!priv->dw.dbi_base)
360 dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
362 priv->apb_base = (void *)dev_read_addr_index(dev, 1);
366 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
368 ret = gpio_request_by_name(dev, "reset-gpios", 0,
369 &priv->rst_gpio, GPIOD_IS_OUT);
371 dev_err(dev, "failed to find reset-gpios property\n");
375 ret = reset_get_bulk(dev, &priv->rsts);
377 dev_err(dev, "Can't get reset: %d\n", ret);
381 ret = clk_get_bulk(dev, &priv->clks);
383 dev_err(dev, "Can't get clock: %d\n", ret);
387 ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
389 if (ret && ret != -ENOENT) {
390 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
394 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
396 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
404 * rockchip_pcie_probe() - Probe the PCIe bus for active link
406 * @dev: A pointer to the device being operated on
408 * Probe for an active link on the PCIe bus and configure the controller
409 * to enable this port.
411 * Return: 0 on success, else -ENODEV
413 static int rockchip_pcie_probe(struct udevice *dev)
415 struct rk_pcie *priv = dev_get_priv(dev);
416 struct udevice *ctlr = pci_get_controller(dev);
417 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
420 priv->dw.first_busno = dev_seq(dev);
423 ret = rockchip_pcie_parse_dt(dev);
427 ret = rockchip_pcie_init_port(dev);
431 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
432 dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
433 pcie_dw_get_link_width(&priv->dw),
437 return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
438 PCIE_ATU_REGION_INDEX0,
440 priv->dw.mem.phys_start,
441 priv->dw.mem.bus_start,
445 static const struct dm_pci_ops rockchip_pcie_ops = {
446 .read_config = pcie_dw_read_config,
447 .write_config = pcie_dw_write_config,
450 static const struct udevice_id rockchip_pcie_ids[] = {
451 { .compatible = "rockchip,rk3568-pcie" },
455 U_BOOT_DRIVER(rockchip_dw_pcie) = {
456 .name = "pcie_dw_rockchip",
458 .of_match = rockchip_pcie_ids,
459 .ops = &rockchip_pcie_ops,
460 .probe = rockchip_pcie_probe,
461 .priv_auto = sizeof(struct rk_pcie),