1 // SPDX-License-Identifier: GPL-2.0
3 * Broadcom STB PCIe controller driver
5 * Copyright (C) 2020 Samsung Electronics Co., Ltd.
7 * Based on upstream Linux kernel driver:
8 * drivers/pci/controller/pcie-brcmstb.c
9 * Copyright (C) 2009 - 2017 Broadcom
11 * Based driver by Nicolas Saenz Julienne
12 * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
18 #include <dm/ofnode.h>
21 #include <linux/bitfield.h>
22 #include <linux/log2.h>
23 #include <linux/iopoll.h>
25 /* Offset of the mandatory PCIe capability config registers */
26 #define BRCM_PCIE_CAP_REGS 0x00ac
28 /* The PCIe controller register offsets */
29 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
30 #define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
31 #define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
33 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
34 #define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
36 #define PCIE_RC_DL_MDIO_ADDR 0x1100
37 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
38 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
40 #define PCIE_MISC_MISC_CTRL 0x4008
41 #define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
42 #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
43 #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
44 #define MISC_CTRL_MAX_BURST_SIZE_128 0x0
45 #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
47 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
48 #define PCIE_MEM_WIN0_LO(win) \
49 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
51 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
52 #define PCIE_MEM_WIN0_HI(win) \
53 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
55 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
56 #define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
58 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
59 #define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
60 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
62 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
63 #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
65 #define PCIE_MISC_PCIE_STATUS 0x4068
66 #define STATUS_PCIE_PORT_MASK 0x80
67 #define STATUS_PCIE_PORT_SHIFT 7
68 #define STATUS_PCIE_DL_ACTIVE_MASK 0x20
69 #define STATUS_PCIE_DL_ACTIVE_SHIFT 5
70 #define STATUS_PCIE_PHYLINKUP_MASK 0x10
71 #define STATUS_PCIE_PHYLINKUP_SHIFT 4
73 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
74 #define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
75 #define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
76 #define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
77 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
78 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
80 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
81 #define MEM_WIN0_BASE_HI_BASE_MASK 0xff
82 #define PCIE_MEM_WIN0_BASE_HI(win) \
83 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
85 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
86 #define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
87 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
88 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
90 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
91 #define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
92 #define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
94 #define PCIE_MSI_INTR2_CLR 0x4508
95 #define PCIE_MSI_INTR2_MASK_SET 0x4510
97 #define PCIE_EXT_CFG_DATA 0x8000
99 #define PCIE_EXT_CFG_INDEX 0x9000
101 #define PCIE_RGR1_SW_INIT_1 0x9210
102 #define RGR1_SW_INIT_1_PERST_MASK 0x1
103 #define RGR1_SW_INIT_1_INIT_MASK 0x2
105 /* PCIe parameters */
106 #define BRCM_NUM_PCIE_OUT_WINS 4
109 #define MDIO_PORT0 0x0
110 #define MDIO_DATA_MASK 0x7fffffff
111 #define MDIO_DATA_SHIFT 0
112 #define MDIO_PORT_MASK 0xf0000
113 #define MDIO_PORT_SHIFT 16
114 #define MDIO_REGAD_MASK 0xffff
115 #define MDIO_REGAD_SHIFT 0
116 #define MDIO_CMD_MASK 0xfff00000
117 #define MDIO_CMD_SHIFT 20
118 #define MDIO_CMD_READ 0x1
119 #define MDIO_CMD_WRITE 0x0
120 #define MDIO_DATA_DONE_MASK 0x80000000
121 #define SSC_REGS_ADDR 0x1100
122 #define SET_ADDR_OFFSET 0x1f
123 #define SSC_CNTL_OFFSET 0x2
124 #define SSC_CNTL_OVRD_EN_MASK 0x8000
125 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
126 #define SSC_STATUS_OFFSET 0x1
127 #define SSC_STATUS_SSC_MASK 0x400
128 #define SSC_STATUS_SSC_SHIFT 10
129 #define SSC_STATUS_PLL_LOCK_MASK 0x800
130 #define SSC_STATUS_PLL_LOCK_SHIFT 11
133 * struct brcm_pcie - the PCIe controller state
134 * @base: Base address of memory mapped IO registers of the controller
135 * @gen: Non-zero value indicates limitation of the PCIe controller operation
136 * to a specific generation (1, 2 or 3)
137 * @ssc: true indicates active Spread Spectrum Clocking operation
147 * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
148 * @size: The inbound region size
150 * This function converts size of the inbound "BAR" region to the non-linear
151 * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
153 * Return: The encoded inbound region size
155 static int brcm_pcie_encode_ibar_size(u64 size)
157 int log2_in = ilog2(size);
159 if (log2_in >= 12 && log2_in <= 15)
160 /* Covers 4KB to 32KB (inclusive) */
161 return (log2_in - 12) + 0x1c;
162 else if (log2_in >= 16 && log2_in <= 37)
163 /* Covers 64KB to 32GB, (inclusive) */
166 /* Something is awry so disable */
171 * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
172 * @pcie: Pointer to the PCIe controller state
174 * The controller is capable of serving in both RC and EP roles.
176 * Return: true for RC mode, false for EP mode.
178 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
182 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
184 return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
188 * brcm_pcie_link_up() - Check whether the PCIe link is up
189 * @pcie: Pointer to the PCIe controller state
191 * Return: true if the link is up, false otherwise.
193 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
197 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
198 dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
199 plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
204 static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
205 uint offset, void **paddress)
207 struct brcm_pcie *pcie = dev_get_priv(dev);
208 unsigned int pci_bus = PCI_BUS(bdf);
209 unsigned int pci_dev = PCI_DEV(bdf);
210 unsigned int pci_func = PCI_FUNC(bdf);
214 * Busses 0 (host PCIe bridge) and 1 (its immediate child)
215 * are limited to a single device each
217 if (pci_bus < 2 && pci_dev > 0)
220 /* Accesses to the RC go right to the RC registers */
222 *paddress = pcie->base + offset;
226 /* For devices, write to the config space index register */
227 idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0);
229 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
230 *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
235 static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
236 uint offset, ulong *valuep,
237 enum pci_size_t size)
239 return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
240 bdf, offset, valuep, size);
243 static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
244 uint offset, ulong value,
245 enum pci_size_t size)
247 return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
248 bdf, offset, value, size);
251 static const char *link_speed_to_str(unsigned int cls)
254 case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
255 case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
256 case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
264 static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
269 pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
270 pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
271 pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
277 * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
278 * @base: Pointer to the PCIe controller IO registers
279 * @port: The MDIO port number
280 * @regad: The register address
281 * @val: A pointer at which to store the read value
283 * Return: 0 on success and register value in @val, negative error value
286 static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
287 unsigned int regad, u32 *val)
292 addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
293 writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
294 readl(base + PCIE_RC_DL_MDIO_ADDR);
296 ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
297 (data & MDIO_DATA_DONE_MASK), 100);
299 *val = data & MDIO_DATA_MASK;
305 * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
306 * @base: Pointer to the PCIe controller IO registers
307 * @port: The MDIO port number
308 * @regad: Address of the register
309 * @wrdata: The value to write
311 * Return: 0 on success, negative error value on failure.
313 static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
314 unsigned int regad, u16 wrdata)
318 addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
319 writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
320 readl(base + PCIE_RC_DL_MDIO_ADDR);
321 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
323 return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
324 !(data & MDIO_DATA_DONE_MASK), 100);
328 * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
329 * @base: pointer to the PCIe controller IO registers
331 * Return: 0 on success, negative error value on failure.
333 static int brcm_pcie_set_ssc(void __iomem *base)
339 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
344 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
348 tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
350 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
355 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
359 ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
360 pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
362 return ssc && pll ? 0 : -EIO;
366 * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
367 * @pcie: pointer to the PCIe controller state
368 * @gen: PCIe generation to limit the controller's operation to
370 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
372 void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
374 u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
375 u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
377 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
378 writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
380 lnkctl2 = (lnkctl2 & ~0xf) | gen;
381 writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
384 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
385 unsigned int win, u64 phys_addr,
386 u64 pcie_addr, u64 size)
388 void __iomem *base = pcie->base;
389 u32 phys_addr_mb_high, limit_addr_mb_high;
390 phys_addr_t phys_addr_mb, limit_addr_mb;
394 /* Set the base of the pcie_addr window */
395 writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
396 writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
398 /* Write the addr base & limit lower bits (in MBs) */
399 phys_addr_mb = phys_addr / SZ_1M;
400 limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
402 tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
403 u32p_replace_bits(&tmp, phys_addr_mb,
404 MEM_WIN0_BASE_LIMIT_BASE_MASK);
405 u32p_replace_bits(&tmp, limit_addr_mb,
406 MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
407 writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
409 /* Write the cpu & limit addr upper bits */
410 high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
411 phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
412 tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
413 u32p_replace_bits(&tmp, phys_addr_mb_high,
414 MEM_WIN0_BASE_HI_BASE_MASK);
415 writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
417 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
418 tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
419 u32p_replace_bits(&tmp, limit_addr_mb_high,
420 PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
421 writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
424 static int brcm_pcie_probe(struct udevice *dev)
426 struct udevice *ctlr = pci_get_controller(dev);
427 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
428 struct brcm_pcie *pcie = dev_get_priv(dev);
429 void __iomem *base = pcie->base;
430 struct pci_region region;
431 bool ssc_good = false;
432 int num_out_wins = 0;
433 u64 rc_bar2_offset, rc_bar2_size;
434 unsigned int scb_size_val;
436 u16 nlw, cls, lnksta;
440 * Reset the bridge, assert the fundamental reset. Note for some SoCs,
441 * e.g. BCM7278, the fundamental reset should not be asserted here.
442 * This will need to be changed when support for other SoCs is added.
444 setbits_le32(base + PCIE_RGR1_SW_INIT_1,
445 RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
447 * The delay is a safety precaution to preclude the reset signal
448 * from looking like a glitch.
452 /* Take the bridge out of reset */
453 clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
455 clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
456 PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
458 /* Wait for SerDes to be stable */
461 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
462 clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
463 MISC_CTRL_MAX_BURST_SIZE_MASK,
464 MISC_CTRL_SCB_ACCESS_EN_MASK |
465 MISC_CTRL_CFG_READ_UR_MODE_MASK |
466 MISC_CTRL_MAX_BURST_SIZE_128);
468 pci_get_dma_regions(dev, ®ion, 0);
469 rc_bar2_offset = region.bus_start - region.phys_start;
470 rc_bar2_size = 1ULL << fls64(region.size - 1);
472 tmp = lower_32_bits(rc_bar2_offset);
473 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
474 RC_BAR2_CONFIG_LO_SIZE_MASK);
475 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
476 writel(upper_32_bits(rc_bar2_offset),
477 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
479 scb_size_val = rc_bar2_size ?
480 ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
482 tmp = readl(base + PCIE_MISC_MISC_CTRL);
483 u32p_replace_bits(&tmp, scb_size_val,
484 MISC_CTRL_SCB0_SIZE_MASK);
485 writel(tmp, base + PCIE_MISC_MISC_CTRL);
487 /* Disable the PCIe->GISB memory window (RC_BAR1) */
488 clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
489 RC_BAR1_CONFIG_LO_SIZE_MASK);
491 /* Disable the PCIe->SCB memory window (RC_BAR3) */
492 clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
493 RC_BAR3_CONFIG_LO_SIZE_MASK);
495 /* Mask all interrupts since we are not handling any yet */
496 writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
498 /* Clear any interrupts we find on boot */
499 writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
502 brcm_pcie_set_gen(pcie, pcie->gen);
504 /* Unassert the fundamental reset */
505 clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
506 RGR1_SW_INIT_1_PERST_MASK);
508 /* Give the RC/EP time to wake up, before trying to configure RC.
509 * Intermittently check status for link-up, up to a total of 100ms.
511 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
514 if (!brcm_pcie_link_up(pcie)) {
515 printf("PCIe BRCM: link down\n");
519 if (!brcm_pcie_rc_mode(pcie)) {
520 printf("PCIe misconfigured; is in EP mode\n");
524 for (i = 0; i < hose->region_count; i++) {
525 struct pci_region *reg = &hose->regions[i];
527 if (reg->flags != PCI_REGION_MEM)
530 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
533 brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
534 reg->bus_start, reg->size);
540 * For config space accesses on the RC, show the right class for
541 * a PCIe-PCIe bridge (the default setting is to be EP mode).
543 clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
544 CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
547 ret = brcm_pcie_set_ssc(pcie->base);
551 printf("PCIe BRCM: failed attempt to enter SSC mode\n");
554 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
555 cls = lnksta & PCI_EXP_LNKSTA_CLS;
556 nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
558 printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
559 nlw, ssc_good ? "(SSC)" : "(!SSC)");
561 /* PCIe->SCB endian mode for BAR */
562 clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
563 VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
564 VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
566 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
567 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
569 setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
570 PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
575 static int brcm_pcie_remove(struct udevice *dev)
577 struct brcm_pcie *pcie = dev_get_priv(dev);
578 void __iomem *base = pcie->base;
580 /* Assert fundamental reset */
581 setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);
583 /* Turn off SerDes */
584 setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
585 PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
587 /* Shutdown bridge */
588 setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
593 static int brcm_pcie_of_to_plat(struct udevice *dev)
595 struct brcm_pcie *pcie = dev_get_priv(dev);
596 ofnode dn = dev_ofnode(dev);
600 /* Get the controller base address */
601 pcie->base = dev_read_addr_ptr(dev);
605 pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
607 ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
608 if (ret < 0 || max_link_speed > 4)
611 pcie->gen = max_link_speed;
616 static const struct dm_pci_ops brcm_pcie_ops = {
617 .read_config = brcm_pcie_read_config,
618 .write_config = brcm_pcie_write_config,
621 static const struct udevice_id brcm_pcie_ids[] = {
622 { .compatible = "brcm,bcm2711-pcie" },
626 U_BOOT_DRIVER(pcie_brcm_base) = {
629 .ops = &brcm_pcie_ops,
630 .of_match = brcm_pcie_ids,
631 .probe = brcm_pcie_probe,
632 .remove = brcm_pcie_remove,
633 .of_to_plat = brcm_pcie_of_to_plat,
634 .priv_auto = sizeof(struct brcm_pcie),
635 .flags = DM_FLAG_OS_PREPARE,