1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010, CompuLab, Ltd.
4 * Author: Mike Rapoport <mike@compulab.co.il>
6 * Based on NVIDIA PCIe driver
7 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 * Copyright (c) 2013-2014, NVIDIA Corporation.
12 #define pr_fmt(fmt) "tegra-pcie: " fmt
21 #include <pci_tegra.h>
22 #include <power-domain.h>
28 #include <linux/ioport.h>
29 #include <linux/list.h>
31 #ifndef CONFIG_TEGRA186
32 #include <asm/arch/clock.h>
33 #include <asm/arch/powergate.h>
34 #include <asm/arch-tegra/xusb-padctl.h>
35 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
39 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
40 * should not be present. These are needed because newer Tegra SoCs support
41 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
42 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
43 * fixed to implement the standard APIs, and all drivers converted to solely
44 * use the new standard APIs, with no ifdefs.
47 #define AFI_AXI_BAR0_SZ 0x00
48 #define AFI_AXI_BAR1_SZ 0x04
49 #define AFI_AXI_BAR2_SZ 0x08
50 #define AFI_AXI_BAR3_SZ 0x0c
51 #define AFI_AXI_BAR4_SZ 0x10
52 #define AFI_AXI_BAR5_SZ 0x14
54 #define AFI_AXI_BAR0_START 0x18
55 #define AFI_AXI_BAR1_START 0x1c
56 #define AFI_AXI_BAR2_START 0x20
57 #define AFI_AXI_BAR3_START 0x24
58 #define AFI_AXI_BAR4_START 0x28
59 #define AFI_AXI_BAR5_START 0x2c
61 #define AFI_FPCI_BAR0 0x30
62 #define AFI_FPCI_BAR1 0x34
63 #define AFI_FPCI_BAR2 0x38
64 #define AFI_FPCI_BAR3 0x3c
65 #define AFI_FPCI_BAR4 0x40
66 #define AFI_FPCI_BAR5 0x44
68 #define AFI_CACHE_BAR0_SZ 0x48
69 #define AFI_CACHE_BAR0_ST 0x4c
70 #define AFI_CACHE_BAR1_SZ 0x50
71 #define AFI_CACHE_BAR1_ST 0x54
73 #define AFI_MSI_BAR_SZ 0x60
74 #define AFI_MSI_FPCI_BAR_ST 0x64
75 #define AFI_MSI_AXI_BAR_ST 0x68
77 #define AFI_CONFIGURATION 0xac
78 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
80 #define AFI_FPCI_ERROR_MASKS 0xb0
82 #define AFI_INTR_MASK 0xb4
83 #define AFI_INTR_MASK_INT_MASK (1 << 0)
84 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
86 #define AFI_SM_INTR_ENABLE 0xc4
87 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
88 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
89 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
90 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
91 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
92 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
93 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
94 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
96 #define AFI_AFI_INTR_ENABLE 0xc8
97 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
98 #define AFI_INTR_EN_INI_DECERR (1 << 1)
99 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
100 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
101 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
102 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
103 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
104 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
105 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
107 #define AFI_PCIE_CONFIG 0x0f8
108 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
109 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
110 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
119 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
120 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
122 #define AFI_FUSE 0x104
123 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
125 #define AFI_PEX0_CTRL 0x110
126 #define AFI_PEX1_CTRL 0x118
127 #define AFI_PEX2_CTRL 0x128
128 #define AFI_PEX2_CTRL_T186 0x19c
129 #define AFI_PEX_CTRL_RST (1 << 0)
130 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
131 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
132 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
134 #define AFI_PLLE_CONTROL 0x160
135 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
136 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
138 #define AFI_PEXBIAS_CTRL_0 0x168
140 #define PADS_CTL_SEL 0x0000009C
142 #define PADS_CTL 0x000000A0
143 #define PADS_CTL_IDDQ_1L (1 << 0)
144 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
145 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
147 #define PADS_PLL_CTL_TEGRA20 0x000000B8
148 #define PADS_PLL_CTL_TEGRA30 0x000000B4
149 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
150 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
151 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
152 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
153 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
154 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
155 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
156 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
157 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
158 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
160 #define PADS_REFCLK_CFG0 0x000000C8
161 #define PADS_REFCLK_CFG1 0x000000CC
164 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
165 * entries, one entry per PCIe port. These field definitions and desired
166 * values aren't in the TRM, but do come from NVIDIA.
168 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
169 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
170 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
171 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
173 #define RP_VEND_XP 0x00000F00
174 #define RP_VEND_XP_DL_UP (1 << 30)
176 #define RP_VEND_CTL2 0x00000FA8
177 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
179 #define RP_PRIV_MISC 0x00000FE0
180 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
181 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
183 #define RP_LINK_CONTROL_STATUS 0x00000090
184 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
185 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
195 struct tegra_pcie_port {
196 struct tegra_pcie *pcie;
198 struct fdt_resource regs;
199 unsigned int num_lanes;
202 struct list_head list;
205 struct tegra_pcie_soc {
206 unsigned int num_ports;
207 unsigned long pads_pll_ctl;
208 unsigned long tx_ref_sel;
209 unsigned long afi_pex2_ctrl;
210 u32 pads_refclk_cfg0;
211 u32 pads_refclk_cfg1;
212 bool has_pex_clkreq_en;
213 bool has_pex_bias_ctrl;
216 bool force_pca_enable;
220 struct resource pads;
224 struct list_head ports;
227 const struct tegra_pcie_soc *soc;
229 #ifdef CONFIG_TEGRA186
232 struct reset_ctl reset_afi;
233 struct reset_ctl reset_pex;
234 struct reset_ctl reset_pcie_x;
235 struct power_domain pwrdom;
237 struct tegra_xusb_phy *phy;
241 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
242 unsigned long offset)
244 writel(value, pcie->afi.start + offset);
247 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
249 return readl(pcie->afi.start + offset);
252 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
253 unsigned long offset)
255 writel(value, pcie->pads.start + offset);
258 #ifndef CONFIG_TEGRA186
259 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
261 return readl(pcie->pads.start + offset);
265 static unsigned long rp_readl(struct tegra_pcie_port *port,
266 unsigned long offset)
268 return readl(port->regs.start + offset);
271 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
272 unsigned long offset)
274 writel(value, port->regs.start + offset);
277 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
279 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
280 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
284 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
285 int where, unsigned long *address)
287 unsigned int bus = PCI_BUS(bdf);
290 unsigned int dev = PCI_DEV(bdf);
291 struct tegra_pcie_port *port;
293 list_for_each_entry(port, &pcie->ports, list) {
294 if (port->index + 1 == dev) {
295 *address = port->regs.start + (where & ~3);
301 #ifdef CONFIG_TEGRA20
302 unsigned int dev = PCI_DEV(bdf);
307 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
312 static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
313 uint offset, ulong *valuep,
314 enum pci_size_t size)
316 struct tegra_pcie *pcie = dev_get_priv(bus);
317 unsigned long address, value;
320 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
326 value = readl(address);
328 #ifdef CONFIG_TEGRA20
329 /* fixup root port class */
330 if (PCI_BUS(bdf) == 0) {
331 if ((offset & ~3) == PCI_CLASS_REVISION) {
332 value &= ~0x00ff0000;
333 value |= PCI_CLASS_BRIDGE_PCI << 16;
339 *valuep = pci_conv_32_to_size(value, offset, size);
344 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
345 uint offset, ulong value,
346 enum pci_size_t size)
348 struct tegra_pcie *pcie = dev_get_priv(bus);
349 unsigned long address;
353 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
357 old = readl(address);
358 value = pci_conv_size_to_32(old, value, offset, size);
359 writel(value, address);
364 static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
369 addr = ofnode_get_property(node, "assigned-addresses", &len);
371 pr_err("property \"assigned-addresses\" not found");
372 return -FDT_ERR_NOTFOUND;
375 port->regs.start = fdt32_to_cpu(addr[2]);
376 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
381 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
382 enum tegra_pci_id id, unsigned long *xbar)
388 debug("single-mode configuration\n");
389 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
393 debug("dual-mode configuration\n");
394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
401 debug("4x1, 2x1 configuration\n");
402 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
406 debug("2x3 configuration\n");
407 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
411 debug("4x1, 1x2 configuration\n");
412 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
420 debug("4x1, 1x1 configuration\n");
421 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
425 debug("2x1, 1x1 configuration\n");
426 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
433 debug("x4 x1 configuration\n");
434 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
438 debug("x2 x1 x1 configuration\n");
439 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
443 debug("x1 x1 x1 configuration\n");
444 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
452 return -FDT_ERR_NOTFOUND;
455 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
457 struct fdt_pci_addr addr;
460 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
462 pr_err("failed to parse \"nvidia,num-lanes\" property");
468 err = ofnode_read_pci_addr(node, 0, "reg", &addr);
470 pr_err("failed to parse \"reg\" property");
474 *index = PCI_DEV(addr.phys_hi) - 1;
479 int __weak tegra_pcie_board_init(void)
484 static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
485 struct tegra_pcie *pcie)
491 err = dev_read_resource(dev, 0, &pcie->pads);
493 pr_err("resource \"pads\" not found");
497 err = dev_read_resource(dev, 1, &pcie->afi);
499 pr_err("resource \"afi\" not found");
503 err = dev_read_resource(dev, 2, &pcie->cs);
505 pr_err("resource \"cs\" not found");
509 err = tegra_pcie_board_init();
511 pr_err("tegra_pcie_board_init() failed: err=%d", err);
515 #ifndef CONFIG_TEGRA186
516 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
518 err = tegra_xusb_phy_prepare(pcie->phy);
520 pr_err("failed to prepare PHY: %d", err);
526 dev_for_each_subnode(subnode, dev) {
527 unsigned int index = 0, num_lanes = 0;
528 struct tegra_pcie_port *port;
530 err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
532 pr_err("failed to obtain root port info");
536 lanes |= num_lanes << (index << 3);
538 if (!ofnode_is_available(subnode))
541 port = malloc(sizeof(*port));
545 memset(port, 0, sizeof(*port));
546 port->num_lanes = num_lanes;
549 err = tegra_pcie_port_parse_dt(subnode, port);
555 list_add_tail(&port->list, &pcie->ports);
559 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
562 pr_err("invalid lane configuration");
569 #ifdef CONFIG_TEGRA186
570 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
574 ret = power_domain_on(&pcie->pwrdom);
576 pr_err("power_domain_on() failed: %d\n", ret);
580 ret = clk_enable(&pcie->clk_afi);
582 pr_err("clk_enable(afi) failed: %d\n", ret);
586 ret = clk_enable(&pcie->clk_pex);
588 pr_err("clk_enable(pex) failed: %d\n", ret);
592 ret = reset_deassert(&pcie->reset_afi);
594 pr_err("reset_deassert(afi) failed: %d\n", ret);
598 ret = reset_deassert(&pcie->reset_pex);
600 pr_err("reset_deassert(pex) failed: %d\n", ret);
607 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
609 const struct tegra_pcie_soc *soc = pcie->soc;
613 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
614 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
615 reset_set_enable(PERIPH_ID_AFI, 1);
616 reset_set_enable(PERIPH_ID_PCIE, 1);
618 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
620 pr_err("failed to power off PCIe partition: %d", err);
624 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
627 pr_err("failed to power up PCIe partition: %d", err);
631 /* take AFI controller out of reset */
632 reset_set_enable(PERIPH_ID_AFI, 0);
634 /* enable AFI clock */
635 clock_enable(PERIPH_ID_AFI);
637 if (soc->has_cml_clk) {
638 /* enable CML clock */
639 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
642 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
645 err = tegra_plle_enable();
647 pr_err("failed to enable PLLE: %d\n", err);
654 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
656 const struct tegra_pcie_soc *soc = pcie->soc;
657 unsigned long start = get_timer(0);
660 while (get_timer(start) < timeout) {
661 value = pads_readl(pcie, soc->pads_pll_ctl);
662 if (value & PADS_PLL_CTL_LOCKDET)
669 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
671 const struct tegra_pcie_soc *soc = pcie->soc;
675 /* initialize internal PHY, enable up to 16 PCIe lanes */
676 pads_writel(pcie, 0, PADS_CTL_SEL);
678 /* override IDDQ to 1 on all 4 lanes */
679 value = pads_readl(pcie, PADS_CTL);
680 value |= PADS_CTL_IDDQ_1L;
681 pads_writel(pcie, value, PADS_CTL);
684 * Set up PHY PLL inputs select PLLE output as refclock, set TX
685 * ref sel to div10 (not div5).
687 value = pads_readl(pcie, soc->pads_pll_ctl);
688 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
689 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
690 pads_writel(pcie, value, soc->pads_pll_ctl);
693 value = pads_readl(pcie, soc->pads_pll_ctl);
694 value &= ~PADS_PLL_CTL_RST_B4SM;
695 pads_writel(pcie, value, soc->pads_pll_ctl);
699 /* take PLL out of reset */
700 value = pads_readl(pcie, soc->pads_pll_ctl);
701 value |= PADS_PLL_CTL_RST_B4SM;
702 pads_writel(pcie, value, soc->pads_pll_ctl);
704 /* wait for the PLL to lock */
705 err = tegra_pcie_pll_wait(pcie, 500);
707 pr_err("PLL failed to lock: %d", err);
711 /* turn off IDDQ override */
712 value = pads_readl(pcie, PADS_CTL);
713 value &= ~PADS_CTL_IDDQ_1L;
714 pads_writel(pcie, value, PADS_CTL);
716 /* enable TX/RX data */
717 value = pads_readl(pcie, PADS_CTL);
718 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
719 pads_writel(pcie, value, PADS_CTL);
725 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
727 const struct tegra_pcie_soc *soc = pcie->soc;
728 struct tegra_pcie_port *port;
732 #ifdef CONFIG_TEGRA186
737 value = afi_readl(pcie, AFI_PLLE_CONTROL);
738 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
739 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
740 afi_writel(pcie, value, AFI_PLLE_CONTROL);
743 if (soc->has_pex_bias_ctrl)
744 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
746 value = afi_readl(pcie, AFI_PCIE_CONFIG);
747 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
748 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
750 list_for_each_entry(port, &pcie->ports, list)
751 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
753 afi_writel(pcie, value, AFI_PCIE_CONFIG);
755 value = afi_readl(pcie, AFI_FUSE);
758 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
760 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
762 afi_writel(pcie, value, AFI_FUSE);
764 #ifndef CONFIG_TEGRA186
766 err = tegra_xusb_phy_enable(pcie->phy);
768 err = tegra_pcie_phy_enable(pcie);
771 pr_err("failed to power on PHY: %d\n", err);
776 /* take the PCIEXCLK logic out of reset */
777 #ifdef CONFIG_TEGRA186
778 err = reset_deassert(&pcie->reset_pcie_x);
780 pr_err("reset_deassert(pcie_x) failed: %d\n", err);
784 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
787 /* finally enable PCIe */
788 value = afi_readl(pcie, AFI_CONFIGURATION);
789 value |= AFI_CONFIGURATION_EN_FPCI;
790 afi_writel(pcie, value, AFI_CONFIGURATION);
792 /* disable all interrupts */
793 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
794 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
795 afi_writel(pcie, 0, AFI_INTR_MASK);
796 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
801 static int tegra_pcie_setup_translations(struct udevice *bus)
803 struct tegra_pcie *pcie = dev_get_priv(bus);
804 unsigned long fpci, axi, size;
805 struct pci_region *io, *mem, *pref;
808 /* BAR 0: type 1 extended configuration space */
810 size = resource_size(&pcie->cs);
811 axi = pcie->cs.start;
813 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
814 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
815 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
817 count = pci_get_regions(bus, &io, &mem, &pref);
821 /* BAR 1: downstream I/O */
824 axi = io->phys_start;
826 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
827 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
828 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
830 /* BAR 2: prefetchable memory */
831 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
833 axi = pref->phys_start;
835 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
836 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
837 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
839 /* BAR 3: non-prefetchable memory */
840 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
842 axi = mem->phys_start;
844 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
845 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
846 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
848 /* NULL out the remaining BARs as they are not used */
849 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
850 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
851 afi_writel(pcie, 0, AFI_FPCI_BAR4);
853 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
854 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
855 afi_writel(pcie, 0, AFI_FPCI_BAR5);
857 /* map all upstream transactions as uncached */
858 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
859 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
860 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
861 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
863 /* MSI translations are setup only when needed */
864 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
865 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
866 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
867 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
872 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
874 unsigned long ret = 0;
876 switch (port->index) {
886 ret = port->pcie->soc->afi_pex2_ctrl;
893 void tegra_pcie_port_reset(struct tegra_pcie_port *port)
895 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
898 /* pulse reset signel */
899 value = afi_readl(port->pcie, ctrl);
900 value &= ~AFI_PEX_CTRL_RST;
901 afi_writel(port->pcie, value, ctrl);
905 value = afi_readl(port->pcie, ctrl);
906 value |= AFI_PEX_CTRL_RST;
907 afi_writel(port->pcie, value, ctrl);
910 int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port)
915 void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
917 tegra_pcie_port_reset(port);
920 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
922 struct tegra_pcie *pcie = port->pcie;
923 const struct tegra_pcie_soc *soc = pcie->soc;
924 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
927 /* enable reference clock */
928 value = afi_readl(pcie, ctrl);
929 value |= AFI_PEX_CTRL_REFCLK_EN;
931 if (pcie->soc->has_pex_clkreq_en)
932 value |= AFI_PEX_CTRL_CLKREQ_EN;
934 value |= AFI_PEX_CTRL_OVERRIDE_EN;
936 afi_writel(pcie, value, ctrl);
938 tegra_pcie_board_port_reset(port);
940 if (soc->force_pca_enable) {
941 value = rp_readl(port, RP_VEND_CTL2);
942 value |= RP_VEND_CTL2_PCA_ENABLE;
943 rp_writel(port, value, RP_VEND_CTL2);
946 /* configure the reference clock driver */
947 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
948 if (soc->num_ports > 2)
949 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
952 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
954 unsigned int retries = 3;
957 value = rp_readl(port, RP_PRIV_MISC);
958 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
959 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
960 rp_writel(port, value, RP_PRIV_MISC);
963 unsigned int timeout = 200;
966 value = rp_readl(port, RP_VEND_XP);
967 if (value & RP_VEND_XP_DL_UP)
974 debug("link %u down, retrying\n", port->index);
981 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
982 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
989 tegra_pcie_board_port_reset(port);
995 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
997 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
1000 /* assert port reset */
1001 value = afi_readl(port->pcie, ctrl);
1002 value &= ~AFI_PEX_CTRL_RST;
1003 afi_writel(port->pcie, value, ctrl);
1005 /* disable reference clock */
1006 value = afi_readl(port->pcie, ctrl);
1007 value &= ~AFI_PEX_CTRL_REFCLK_EN;
1008 afi_writel(port->pcie, value, ctrl);
1011 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
1013 list_del(&port->list);
1017 static int tegra_pcie_enable(struct tegra_pcie *pcie)
1019 struct tegra_pcie_port *port, *tmp;
1021 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1022 debug("probing port %u, using %u lanes\n", port->index,
1025 tegra_pcie_port_enable(port);
1027 if (tegra_pcie_port_check_link(port))
1030 debug("link %u down, ignoring\n", port->index);
1032 tegra_pcie_port_disable(port);
1033 tegra_pcie_port_free(port);
1039 static const struct tegra_pcie_soc pci_tegra_soc[] = {
1042 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1043 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1044 .pads_refclk_cfg0 = 0xfa5cfa5c,
1045 .has_pex_clkreq_en = false,
1046 .has_pex_bias_ctrl = false,
1047 .has_cml_clk = false,
1052 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1053 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1054 .afi_pex2_ctrl = AFI_PEX2_CTRL,
1055 .pads_refclk_cfg0 = 0xfa5cfa5c,
1056 .pads_refclk_cfg1 = 0xfa5cfa5c,
1057 .has_pex_clkreq_en = true,
1058 .has_pex_bias_ctrl = true,
1059 .has_cml_clk = true,
1064 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1065 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1066 .pads_refclk_cfg0 = 0x44ac44ac,
1067 .has_pex_clkreq_en = true,
1068 .has_pex_bias_ctrl = true,
1069 .has_cml_clk = true,
1074 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1075 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1076 .pads_refclk_cfg0 = 0x90b890b8,
1077 .has_pex_clkreq_en = true,
1078 .has_pex_bias_ctrl = true,
1079 .has_cml_clk = true,
1081 .force_pca_enable = true,
1085 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
1086 .pads_refclk_cfg0 = 0x80b880b8,
1087 .pads_refclk_cfg1 = 0x000480b8,
1088 .has_pex_clkreq_en = true,
1089 .has_pex_bias_ctrl = true,
1094 static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
1096 struct tegra_pcie *pcie = dev_get_priv(dev);
1097 enum tegra_pci_id id;
1099 id = dev_get_driver_data(dev);
1100 pcie->soc = &pci_tegra_soc[id];
1102 INIT_LIST_HEAD(&pcie->ports);
1104 if (tegra_pcie_parse_dt(dev, id, pcie))
1110 static int pci_tegra_probe(struct udevice *dev)
1112 struct tegra_pcie *pcie = dev_get_priv(dev);
1115 #ifdef CONFIG_TEGRA186
1116 err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1118 debug("clk_get_by_name(afi) failed: %d\n", err);
1122 err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1124 debug("clk_get_by_name(pex) failed: %d\n", err);
1128 err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1130 debug("reset_get_by_name(afi) failed: %d\n", err);
1134 err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1136 debug("reset_get_by_name(pex) failed: %d\n", err);
1140 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1142 debug("reset_get_by_name(pcie_x) failed: %d\n", err);
1146 err = power_domain_get(dev, &pcie->pwrdom);
1148 debug("power_domain_get() failed: %d\n", err);
1153 err = tegra_pcie_power_on(pcie);
1155 pr_err("failed to power on");
1159 err = tegra_pcie_enable_controller(pcie);
1161 pr_err("failed to enable controller");
1165 err = tegra_pcie_setup_translations(dev);
1167 pr_err("failed to decode ranges");
1171 err = tegra_pcie_enable(pcie);
1173 pr_err("failed to enable PCIe");
1180 static const struct dm_pci_ops pci_tegra_ops = {
1181 .read_config = pci_tegra_read_config,
1182 .write_config = pci_tegra_write_config,
1185 static const struct udevice_id pci_tegra_ids[] = {
1186 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1187 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1188 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1189 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1190 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
1194 U_BOOT_DRIVER(pci_tegra) = {
1195 .name = "pci_tegra",
1197 .of_match = pci_tegra_ids,
1198 .ops = &pci_tegra_ops,
1199 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
1200 .probe = pci_tegra_probe,
1201 .priv_auto_alloc_size = sizeof(struct tegra_pcie),