1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
10 * Pali Rohár <pali@kernel.org>
17 #include <dm/device-internal.h>
19 #include <dm/of_access.h>
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/soc.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/mbus.h>
30 #include <linux/sizes.h>
32 /* PCIe unit register offsets */
33 #define SELECT(x, n) ((x >> n) & 1UL)
35 #define PCIE_DEV_ID_OFF 0x0000
36 #define PCIE_CMD_OFF 0x0004
37 #define PCIE_DEV_REV_OFF 0x0008
38 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
39 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
40 #define PCIE_EXP_ROM_BAR_OFF 0x0030
41 #define PCIE_CAPAB_OFF 0x0060
42 #define PCIE_CTRL_STAT_OFF 0x0068
43 #define PCIE_HEADER_LOG_4_OFF 0x0128
44 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
45 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
46 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
47 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
48 #define PCIE_WIN5_CTRL_OFF 0x1880
49 #define PCIE_WIN5_BASE_OFF 0x1884
50 #define PCIE_WIN5_REMAP_OFF 0x188c
51 #define PCIE_CONF_ADDR_OFF 0x18f8
52 #define PCIE_CONF_DATA_OFF 0x18fc
53 #define PCIE_MASK_OFF 0x1910
54 #define PCIE_MASK_ENABLE_INTS (0xf << 24)
55 #define PCIE_CTRL_OFF 0x1a00
56 #define PCIE_CTRL_X1_MODE BIT(0)
57 #define PCIE_CTRL_RC_MODE BIT(1)
58 #define PCIE_STAT_OFF 0x1a04
59 #define PCIE_STAT_BUS (0xff << 8)
60 #define PCIE_STAT_DEV (0x1f << 16)
61 #define PCIE_STAT_LINK_DOWN BIT(0)
62 #define PCIE_DEBUG_CTRL 0x1a60
63 #define PCIE_DEBUG_SOFT_RESET BIT(20)
65 #define LINK_WAIT_RETRIES 100
66 #define LINK_WAIT_TIMEOUT 1000
69 struct pci_controller hose;
71 void __iomem *membase;
83 unsigned int mem_target;
84 unsigned int mem_attr;
85 unsigned int io_target;
87 u32 cfgcache[(0x3c - 0x10) / 4];
90 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
93 val = readl(pcie->base + PCIE_STAT_OFF);
94 return !(val & PCIE_STAT_LINK_DOWN);
97 static void mvebu_pcie_wait_for_link(struct mvebu_pcie *pcie)
101 /* check if the link is up or not */
102 for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
103 if (mvebu_pcie_link_up(pcie)) {
104 printf("%s: Link up\n", pcie->name);
108 udelay(LINK_WAIT_TIMEOUT);
111 printf("%s: Link down\n", pcie->name);
114 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
118 stat = readl(pcie->base + PCIE_STAT_OFF);
119 stat &= ~PCIE_STAT_BUS;
121 writel(stat, pcie->base + PCIE_STAT_OFF);
124 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
128 stat = readl(pcie->base + PCIE_STAT_OFF);
129 stat &= ~PCIE_STAT_DEV;
131 writel(stat, pcie->base + PCIE_STAT_OFF);
134 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
136 return container_of(hose, struct mvebu_pcie, hose);
139 static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
140 int busno, int dev, int func)
142 /* On the root bus is only one PCI Bridge */
143 if (busno == 0 && (dev != 0 || func != 0))
146 /* Access to other buses is possible when link is up */
147 if (busno != 0 && !mvebu_pcie_link_up(pcie))
150 /* On secondary bus can be only one PCIe device */
151 if (busno == pcie->sec_busno && dev != 0)
157 static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
158 uint offset, ulong *valuep,
159 enum pci_size_t size)
161 struct mvebu_pcie *pcie = dev_get_plat(bus);
162 int busno = PCI_BUS(bdf) - dev_seq(bus);
165 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
166 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
168 if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
169 debug("- out of range\n");
170 *valuep = pci_get_ff(size);
175 * The configuration space of the PCI Bridge on the root bus (zero) is
176 * of Type 0 but the BAR registers (including ROM BAR) don't have the
177 * same meaning as in the PCIe specification. Therefore do not access
178 * BAR registers and non-common registers (those which have different
179 * meaning for Type 0 and Type 1 config space) of the PCI Bridge and
180 * instead read their content from driver virtual cfgcache[].
182 if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
183 (offset >= 0x38 && offset < 0x3c))) {
184 data = pcie->cfgcache[(offset - 0x10) / 4];
185 debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
187 *valuep = pci_conv_32_to_size(data, offset, size);
192 * PCI bridge is device 0 at the root bus (zero) but mvebu has it
193 * mapped on secondary bus with device number 1.
196 addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
198 addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
201 writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
206 data = readb(pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
209 data = readw(pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
212 data = readl(pcie->base + PCIE_CONF_DATA_OFF);
218 if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
220 * Change Header Type of PCI Bridge device to Type 1
221 * (0x01, used by PCI Bridges) because mvebu reports
222 * Type 0 (0x00, used by Upstream and Endpoint devices).
224 data = pci_conv_size_to_32(data, 0, offset, size);
226 data |= PCI_HEADER_TYPE_BRIDGE << 16;
227 data = pci_conv_32_to_size(data, offset, size);
230 debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
236 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
237 uint offset, ulong value,
238 enum pci_size_t size)
240 struct mvebu_pcie *pcie = dev_get_plat(bus);
241 int busno = PCI_BUS(bdf) - dev_seq(bus);
244 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
245 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
246 debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
248 if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
249 debug("- out of range\n");
254 * As explained in mvebu_pcie_read_config(), PCI Bridge Type 1 specific
255 * config registers are not available, so we write their content only
256 * into driver virtual cfgcache[].
257 * And as explained in mvebu_pcie_probe(), mvebu has its own specific
258 * way for configuring secondary bus number.
260 if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
261 (offset >= 0x38 && offset < 0x3c))) {
262 debug("Writing to cfgcache only\n");
263 data = pcie->cfgcache[(offset - 0x10) / 4];
264 data = pci_conv_size_to_32(data, value, offset, size);
265 /* mvebu PCI bridge does not have configurable bars */
266 if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
267 (offset & ~3) == PCI_BASE_ADDRESS_1 ||
268 (offset & ~3) == PCI_ROM_ADDRESS1)
270 pcie->cfgcache[(offset - 0x10) / 4] = data;
271 /* mvebu has its own way how to set PCI secondary bus number */
272 if (offset == PCI_SECONDARY_BUS ||
273 (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
274 pcie->sec_busno = (data >> 8) & 0xff;
275 mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno);
276 debug("Secondary bus number was changed to %d\n",
283 * PCI bridge is device 0 at the root bus (zero) but mvebu has it
284 * mapped on secondary bus with device number 1.
287 addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
289 addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
292 writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
297 writeb(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
300 writew(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
303 writel(value, pcie->base + PCIE_CONF_DATA_OFF);
313 * Setup PCIE BARs and Address Decode Wins:
314 * BAR[0] -> internal registers
315 * BAR[1] -> covers all DRAM banks
317 * WIN[0-3] -> DRAM bank[0-3]
319 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
321 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
325 /* First, disable and clear BARs and windows. */
326 for (i = 1; i < 3; i++) {
327 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
328 writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
329 writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
332 for (i = 0; i < 5; i++) {
333 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
334 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
335 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
338 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
339 writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
340 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
342 /* Setup windows for DDR banks. Count total DDR size on the fly. */
344 for (i = 0; i < dram->num_cs; i++) {
345 const struct mbus_dram_window *cs = dram->cs + i;
347 writel(cs->base & 0xffff0000,
348 pcie->base + PCIE_WIN04_BASE_OFF(i));
349 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
350 writel(((cs->size - 1) & 0xffff0000) |
351 (cs->mbus_attr << 8) |
352 (dram->mbus_dram_target_id << 4) | 1,
353 pcie->base + PCIE_WIN04_CTRL_OFF(i));
358 /* Round up 'size' to the nearest power of two. */
359 if ((size & (size - 1)) != 0)
360 size = 1 << fls(size);
362 /* Setup BAR[1] to all DRAM banks. */
363 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
364 writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
365 writel(((size - 1) & 0xffff0000) | 0x1,
366 pcie->base + PCIE_BAR_CTRL_OFF(1));
368 /* Setup BAR[0] to internal registers. */
369 writel(pcie->intregs, pcie->base + PCIE_BAR_LO_OFF(0));
370 writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
373 /* Only enable PCIe link, do not setup it */
374 static int mvebu_pcie_enable_link(struct mvebu_pcie *pcie, ofnode node)
376 struct reset_ctl rst;
379 ret = reset_get_by_index_nodev(node, 0, &rst);
380 if (ret == -ENOENT) {
382 } else if (ret < 0) {
383 printf("%s: cannot get reset controller: %d\n", pcie->name, ret);
387 ret = reset_request(&rst);
389 printf("%s: cannot request reset controller: %d\n", pcie->name, ret);
393 ret = reset_deassert(&rst);
396 printf("%s: cannot enable PCIe port: %d\n", pcie->name, ret);
403 /* Setup PCIe link but do not enable it */
404 static void mvebu_pcie_setup_link(struct mvebu_pcie *pcie)
408 /* Setup PCIe controller to Root Complex mode */
409 reg = readl(pcie->base + PCIE_CTRL_OFF);
410 reg |= PCIE_CTRL_RC_MODE;
411 writel(reg, pcie->base + PCIE_CTRL_OFF);
414 * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link
415 * Capability register. This register is defined by PCIe specification
416 * as read-only but this mvebu controller has it as read-write and must
417 * be set to number of SerDes PCIe lanes (1 or 4). If this register is
418 * not set correctly then link with endpoint card is not established.
420 reg = readl(pcie->base + PCIE_CAPAB_OFF + PCI_EXP_LNKCAP);
421 reg &= ~PCI_EXP_LNKCAP_MLW;
422 reg |= (pcie->is_x4 ? 4 : 1) << 4;
423 writel(reg, pcie->base + PCIE_CAPAB_OFF + PCI_EXP_LNKCAP);
426 static int mvebu_pcie_probe(struct udevice *dev)
428 struct mvebu_pcie *pcie = dev_get_plat(dev);
429 struct udevice *ctlr = pci_get_controller(dev);
430 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
434 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
435 * because default value is Memory controller (0x508000) which
436 * U-Boot cannot recognize as P2P Bridge.
438 * Note that this mvebu PCI Bridge does not have compliant Type 1
439 * Configuration Space. Header Type is reported as Type 0 and it
440 * has format of Type 0 config space.
442 * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
443 * have the same format in Marvell's specification as in PCIe
444 * specification, but their meaning is totally different and they do
445 * different things: they are aliased into internal mvebu registers
446 * (e.g. PCIE_BAR_LO_OFF) and these should not be changed or
447 * reconfigured by pci device drivers.
449 * So our driver converts Type 0 config space to Type 1 and reports
450 * Header Type as Type 1. Access to BAR registers and to non-existent
451 * Type 1 registers is redirected to the virtual cfgcache[] buffer,
452 * which avoids changing unrelated registers.
454 reg = readl(pcie->base + PCIE_DEV_REV_OFF);
456 reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
457 writel(reg, pcie->base + PCIE_DEV_REV_OFF);
460 * mvebu uses local bus number and local device number to determinate
461 * type of config request. Type 0 is used if target bus number equals
462 * local bus number and target device number differs from local device
463 * number. Type 1 is used if target bus number differs from local bus
464 * number. And when target bus number equals local bus number and
465 * target device equals local device number then request is routed to
466 * PCI Bridge which represent local PCIe Root Port.
468 * It means that PCI root and secondary buses shares one bus number
469 * which is configured via local bus number. Determination if config
470 * request should go to root or secondary bus is done based on local
473 * PCIe is point-to-point bus, so at secondary bus is always exactly one
474 * device with number 0. So set local device number to 1, it would not
475 * conflict with any device on secondary bus number and will ensure that
476 * accessing secondary bus and all buses behind secondary would work
477 * automatically and correctly. Therefore this configuration of local
478 * device number implies that setting of local bus number configures
479 * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
480 * later configure it via config write requests to the correct value.
481 * mvebu_pcie_write_config() catches config write requests which tries
482 * to change secondary bus number and correctly updates local bus number
483 * based on new secondary bus number.
485 * With this configuration is PCI Bridge available at secondary bus as
486 * device number 1. But it must be available at root bus (zero) as device
487 * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
488 * functions rewrite address to the real one when accessing the root bus.
490 mvebu_pcie_set_local_bus_nr(pcie, 0);
491 mvebu_pcie_set_local_dev_nr(pcie, 1);
494 * Kirkwood arch code already maps mbus windows for PCIe IO and MEM.
495 * So skip calling mvebu_mbus_add_window_by_id() function as it would
496 * fail on error "conflicts with another window" which means conflict
497 * with existing PCIe window mappings.
499 #ifndef CONFIG_ARCH_KIRKWOOD
500 if (resource_size(&pcie->mem) &&
501 mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
502 (phys_addr_t)pcie->mem.start,
503 resource_size(&pcie->mem))) {
504 printf("%s: unable to add mbus window for mem at %08x+%08x\n",
506 (u32)pcie->mem.start, (unsigned)resource_size(&pcie->mem));
511 if (resource_size(&pcie->io) &&
512 mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
513 (phys_addr_t)pcie->io.start,
514 resource_size(&pcie->io))) {
515 printf("%s: unable to add mbus window for IO at %08x+%08x\n",
517 (u32)pcie->io.start, (unsigned)resource_size(&pcie->io));
523 /* Setup windows and configure host bridge */
524 mvebu_pcie_setup_wins(pcie);
526 /* PCI memory space */
527 pci_set_region(hose->regions + 0, pcie->mem.start,
528 pcie->mem.start, resource_size(&pcie->mem), PCI_REGION_MEM);
529 hose->region_count = 1;
531 if (resource_size(&pcie->mem)) {
532 pci_set_region(hose->regions + hose->region_count,
533 pcie->mem.start, pcie->mem.start,
534 resource_size(&pcie->mem),
536 hose->region_count++;
539 if (resource_size(&pcie->io)) {
540 pci_set_region(hose->regions + hose->region_count,
541 pcie->io.start, pcie->io.start,
542 resource_size(&pcie->io),
544 hose->region_count++;
547 /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
548 pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
549 PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
550 pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
551 PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
553 mvebu_pcie_wait_for_link(pcie);
558 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
559 #define DT_TYPE_IO 0x1
560 #define DT_TYPE_MEM32 0x2
561 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
562 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
564 static int mvebu_get_tgt_attr(ofnode node, int devfn,
569 const int na = 3, ns = 2;
571 int rlen, nranges, rangesz, pna, i;
576 range = ofnode_get_property(node, "ranges", &rlen);
581 * Linux uses of_n_addr_cells() to get the number of address cells
582 * here. Currently this function is only available in U-Boot when
583 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
584 * general, lets't hardcode the "pna" value in the U-Boot code.
586 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
587 rangesz = pna + na + ns;
588 nranges = rlen / sizeof(__be32) / rangesz;
590 for (i = 0; i < nranges; i++, range += rangesz) {
591 u32 flags = of_read_number(range, 1);
592 u32 slot = of_read_number(range + 1, 1);
593 u64 cpuaddr = of_read_number(range + na, pna);
596 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
597 rtype = IORESOURCE_IO;
598 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
599 rtype = IORESOURCE_MEM;
604 * The Linux code used PCI_SLOT() here, which expects devfn
605 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
606 * only expects devfn in 15..8, where its saved in this driver.
608 if (slot == PCI_DEV(devfn) && type == rtype) {
609 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
610 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
618 static int mvebu_pcie_port_parse_dt(ofnode node, ofnode parent, struct mvebu_pcie *pcie)
620 struct fdt_pci_addr pci_addr;
626 /* Get port number, lane number and memory target / attr */
627 if (ofnode_read_u32(node, "marvell,pcie-port",
633 if (ofnode_read_u32(node, "marvell,pcie-lane", &pcie->lane))
636 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
638 if (!ofnode_read_u32(node, "num-lanes", &num_lanes) && num_lanes == 4)
641 /* devfn is in bits [15:8], see PCI_DEV usage */
642 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg", &pci_addr);
644 printf("%s: property \"reg\" is invalid\n", pcie->name);
647 pcie->devfn = pci_addr.phys_hi & 0xff00;
649 ret = mvebu_get_tgt_attr(parent, pcie->devfn,
651 &pcie->mem_target, &pcie->mem_attr);
653 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
657 ret = mvebu_get_tgt_attr(parent, pcie->devfn,
659 &pcie->io_target, &pcie->io_attr);
661 printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
665 /* Parse PCIe controller register base from DT */
666 addr = ofnode_get_property(node, "assigned-addresses", &len);
668 printf("%s: property \"assigned-addresses\" not found\n", pcie->name);
669 ret = -FDT_ERR_NOTFOUND;
673 pcie->base = (void *)(u32)ofnode_translate_address(node, addr);
674 pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]);
682 static const struct dm_pci_ops mvebu_pcie_ops = {
683 .read_config = mvebu_pcie_read_config,
684 .write_config = mvebu_pcie_write_config,
687 static struct driver pcie_mvebu_drv = {
688 .name = "pcie_mvebu",
690 .ops = &mvebu_pcie_ops,
691 .probe = mvebu_pcie_probe,
692 .plat_auto = sizeof(struct mvebu_pcie),
696 * Use a MISC device to bind the n instances (child nodes) of the
697 * PCIe base controller in UCLASS_PCI.
699 static int mvebu_pcie_bind(struct udevice *parent)
701 struct mvebu_pcie **ports_pcie;
702 struct mvebu_pcie *pcie;
703 struct uclass_driver *drv;
711 /* Lookup pci driver */
712 drv = lists_uclass_lookup(UCLASS_PCI);
714 puts("Cannot find PCI driver\n");
718 ports_count = ofnode_get_child_count(dev_ofnode(parent));
719 ports_pcie = calloc(ports_count, sizeof(*ports_pcie));
720 ports_nodes = calloc(ports_count, sizeof(*ports_nodes));
721 if (!ports_pcie || !ports_nodes) {
728 #ifdef CONFIG_ARCH_KIRKWOOD
729 mem.start = KW_DEFADR_PCI_MEM;
730 mem.end = KW_DEFADR_PCI_MEM + KW_DEFADR_PCI_MEM_SIZE - 1;
731 io.start = KW_DEFADR_PCI_IO;
732 io.end = KW_DEFADR_PCI_IO + KW_DEFADR_PCI_IO_SIZE - 1;
734 mem.start = MBUS_PCI_MEM_BASE;
735 mem.end = MBUS_PCI_MEM_BASE + MBUS_PCI_MEM_SIZE - 1;
736 io.start = MBUS_PCI_IO_BASE;
737 io.end = MBUS_PCI_IO_BASE + MBUS_PCI_IO_SIZE - 1;
740 /* First phase: Fill mvebu_pcie struct for each port */
741 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
742 if (!ofnode_is_available(subnode))
745 pcie = calloc(1, sizeof(*pcie));
749 if (mvebu_pcie_port_parse_dt(subnode, dev_ofnode(parent), pcie) < 0) {
755 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
756 * into SoCs address space. Each controller will map 128M of MEM
757 * and 64K of I/O space when registered.
760 if (resource_size(&mem) >= SZ_128M) {
761 pcie->mem.start = mem.start;
762 pcie->mem.end = mem.start + SZ_128M - 1;
763 mem.start += SZ_128M;
765 printf("%s: unable to assign mbus window for mem\n", pcie->name);
770 if (resource_size(&io) >= SZ_64K) {
771 pcie->io.start = io.start;
772 pcie->io.end = io.start + SZ_64K - 1;
775 printf("%s: unable to assign mbus window for io\n", pcie->name);
780 ports_pcie[ports_count] = pcie;
781 ports_nodes[ports_count] = subnode;
785 /* Second phase: Setup all PCIe links (do not enable them yet) */
786 for (i = 0; i < ports_count; i++)
787 mvebu_pcie_setup_link(ports_pcie[i]);
789 /* Third phase: Enable all PCIe links and create for each UCLASS_PCI device */
790 for (i = 0; i < ports_count; i++) {
791 pcie = ports_pcie[i];
792 subnode = ports_nodes[i];
795 * PCIe link can be enabled only after all PCIe links were
796 * properly configured. This is because more PCIe links shares
797 * one enable bit and some PCIe links cannot be enabled
800 if (mvebu_pcie_enable_link(pcie, subnode) < 0) {
805 /* Create child device UCLASS_PCI and bind it */
806 device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
816 static const struct udevice_id mvebu_pcie_ids[] = {
817 { .compatible = "marvell,armada-xp-pcie" },
818 { .compatible = "marvell,armada-370-pcie" },
819 { .compatible = "marvell,kirkwood-pcie" },
823 U_BOOT_DRIVER(pcie_mvebu_base) = {
824 .name = "pcie_mvebu_base",
826 .of_match = mvebu_pcie_ids,
827 .bind = mvebu_pcie_bind,