1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
16 #include <asm/global_data.h>
17 #include <dm/device-internal.h>
19 #include <dm/of_access.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/soc.h>
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/mbus.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* PCIe unit register offsets */
32 #define SELECT(x, n) ((x >> n) & 1UL)
34 #define PCIE_DEV_ID_OFF 0x0000
35 #define PCIE_CMD_OFF 0x0004
36 #define PCIE_DEV_REV_OFF 0x0008
37 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
38 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
39 #define PCIE_EXP_ROM_BAR_OFF 0x0030
40 #define PCIE_CAPAB_OFF 0x0060
41 #define PCIE_CTRL_STAT_OFF 0x0068
42 #define PCIE_HEADER_LOG_4_OFF 0x0128
43 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
44 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
45 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
46 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
47 #define PCIE_WIN5_CTRL_OFF 0x1880
48 #define PCIE_WIN5_BASE_OFF 0x1884
49 #define PCIE_WIN5_REMAP_OFF 0x188c
50 #define PCIE_CONF_ADDR_OFF 0x18f8
51 #define PCIE_CONF_ADDR_EN BIT(31)
52 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
53 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
54 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
55 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
56 #define PCIE_CONF_ADDR(b, d, f, reg) \
57 (PCIE_CONF_BUS(b) | PCIE_CONF_DEV(d) | \
58 PCIE_CONF_FUNC(f) | PCIE_CONF_REG(reg) | \
60 #define PCIE_CONF_DATA_OFF 0x18fc
61 #define PCIE_MASK_OFF 0x1910
62 #define PCIE_MASK_ENABLE_INTS (0xf << 24)
63 #define PCIE_CTRL_OFF 0x1a00
64 #define PCIE_CTRL_X1_MODE BIT(0)
65 #define PCIE_CTRL_RC_MODE BIT(1)
66 #define PCIE_STAT_OFF 0x1a04
67 #define PCIE_STAT_BUS (0xff << 8)
68 #define PCIE_STAT_DEV (0x1f << 16)
69 #define PCIE_STAT_LINK_DOWN BIT(0)
70 #define PCIE_DEBUG_CTRL 0x1a60
71 #define PCIE_DEBUG_SOFT_RESET BIT(20)
74 struct pci_controller hose;
76 void __iomem *membase;
87 unsigned int mem_target;
88 unsigned int mem_attr;
89 unsigned int io_target;
91 u32 cfgcache[(0x34 - 0x10) / 4];
95 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
96 * into SoCs address space. Each controller will map 128M of MEM
97 * and 64K of I/O space when registered.
99 static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
100 static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
102 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
105 val = readl(pcie->base + PCIE_STAT_OFF);
106 return !(val & PCIE_STAT_LINK_DOWN);
109 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
113 stat = readl(pcie->base + PCIE_STAT_OFF);
114 stat &= ~PCIE_STAT_BUS;
116 writel(stat, pcie->base + PCIE_STAT_OFF);
119 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
123 stat = readl(pcie->base + PCIE_STAT_OFF);
124 stat &= ~PCIE_STAT_DEV;
126 writel(stat, pcie->base + PCIE_STAT_OFF);
129 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
131 return container_of(hose, struct mvebu_pcie, hose);
134 static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
135 int busno, int dev, int func)
137 /* On primary bus is only one PCI Bridge */
138 if (busno == pcie->first_busno && (dev != 0 || func != 0))
141 /* Access to other buses is possible when link is up */
142 if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
145 /* On secondary bus can be only one PCIe device */
146 if (busno == pcie->sec_busno && dev != 0)
152 static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
153 uint offset, ulong *valuep,
154 enum pci_size_t size)
156 struct mvebu_pcie *pcie = dev_get_plat(bus);
157 int busno = PCI_BUS(bdf) - dev_seq(bus);
160 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
161 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
163 if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
164 debug("- out of range\n");
165 *valuep = pci_get_ff(size);
170 * mvebu has different internal registers mapped into PCI config space
171 * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
172 * for this range and instead read content from driver virtual cfgcache
174 if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
175 data = pcie->cfgcache[(offset - 0x10) / 4];
176 debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
178 *valuep = pci_conv_32_to_size(data, offset, size);
180 } else if (busno == pcie->first_busno &&
181 (offset & ~3) == PCI_ROM_ADDRESS1) {
182 /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
183 offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
187 * PCI bridge is device 0 at primary bus but mvebu has it mapped on
188 * secondary bus with device number 1.
190 if (busno == pcie->first_busno)
191 addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
193 addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
196 writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
201 data = readb(pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
204 data = readw(pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
207 data = readl(pcie->base + PCIE_CONF_DATA_OFF);
213 if (busno == pcie->first_busno &&
214 (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
216 * Change Header Type of PCI Bridge device to Type 1
217 * (0x01, used by PCI Bridges) because mvebu reports
218 * Type 0 (0x00, used by Upstream and Endpoint devices).
220 data = pci_conv_size_to_32(data, 0, offset, size);
222 data |= PCI_HEADER_TYPE_BRIDGE << 16;
223 data = pci_conv_32_to_size(data, offset, size);
226 debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
232 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
233 uint offset, ulong value,
234 enum pci_size_t size)
236 struct mvebu_pcie *pcie = dev_get_plat(bus);
237 int busno = PCI_BUS(bdf) - dev_seq(bus);
240 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
241 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
242 debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
244 if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
245 debug("- out of range\n");
250 * mvebu has different internal registers mapped into PCI config space
251 * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
252 * for this range and instead write content to driver virtual cfgcache
254 if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
255 debug("Writing to cfgcache only\n");
256 data = pcie->cfgcache[(offset - 0x10) / 4];
257 data = pci_conv_size_to_32(data, value, offset, size);
258 /* mvebu PCI bridge does not have configurable bars */
259 if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
260 (offset & ~3) == PCI_BASE_ADDRESS_1)
262 pcie->cfgcache[(offset - 0x10) / 4] = data;
263 /* mvebu has its own way how to set PCI primary bus number */
264 if (offset == PCI_PRIMARY_BUS) {
265 pcie->first_busno = data & 0xff;
266 debug("Primary bus number was changed to %d\n",
269 /* mvebu has its own way how to set PCI secondary bus number */
270 if (offset == PCI_SECONDARY_BUS ||
271 (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
272 pcie->sec_busno = (data >> 8) & 0xff;
273 mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno);
274 debug("Secondary bus number was changed to %d\n",
278 } else if (busno == pcie->first_busno &&
279 (offset & ~3) == PCI_ROM_ADDRESS1) {
280 /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
281 offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
285 * PCI bridge is device 0 at primary bus but mvebu has it mapped on
286 * secondary bus with device number 1.
288 if (busno == pcie->first_busno)
289 addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset);
291 addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
294 writel(addr, pcie->base + PCIE_CONF_ADDR_OFF);
299 writeb(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
302 writew(value, pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
305 writel(value, pcie->base + PCIE_CONF_DATA_OFF);
315 * Setup PCIE BARs and Address Decode Wins:
316 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
317 * WIN[0-3] -> DRAM bank[0-3]
319 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
321 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
325 /* First, disable and clear BARs and windows. */
326 for (i = 1; i < 3; i++) {
327 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
328 writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
329 writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
332 for (i = 0; i < 5; i++) {
333 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
334 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
335 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
338 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
339 writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
340 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
342 /* Setup windows for DDR banks. Count total DDR size on the fly. */
344 for (i = 0; i < dram->num_cs; i++) {
345 const struct mbus_dram_window *cs = dram->cs + i;
347 writel(cs->base & 0xffff0000,
348 pcie->base + PCIE_WIN04_BASE_OFF(i));
349 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
350 writel(((cs->size - 1) & 0xffff0000) |
351 (cs->mbus_attr << 8) |
352 (dram->mbus_dram_target_id << 4) | 1,
353 pcie->base + PCIE_WIN04_CTRL_OFF(i));
358 /* Round up 'size' to the nearest power of two. */
359 if ((size & (size - 1)) != 0)
360 size = 1 << fls(size);
362 /* Setup BAR[1] to all DRAM banks. */
363 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
364 writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
365 writel(((size - 1) & 0xffff0000) | 0x1,
366 pcie->base + PCIE_BAR_CTRL_OFF(1));
369 static int mvebu_pcie_probe(struct udevice *dev)
371 struct mvebu_pcie *pcie = dev_get_plat(dev);
372 struct udevice *ctlr = pci_get_controller(dev);
373 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
376 /* Setup PCIe controller to Root Complex mode */
377 reg = readl(pcie->base + PCIE_CTRL_OFF);
378 reg |= PCIE_CTRL_RC_MODE;
379 writel(reg, pcie->base + PCIE_CTRL_OFF);
382 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
383 * because default value is Memory controller (0x508000) which
384 * U-Boot cannot recognize as P2P Bridge.
386 * Note that this mvebu PCI Bridge does not have compliant Type 1
387 * Configuration Space. Header Type is reported as Type 0 and in
388 * range 0x10-0x34 it has aliased internal mvebu registers 0x10-0x34
389 * (e.g. PCIE_BAR_LO_OFF) and register 0x38 is reserved.
391 * Driver for this range redirects access to virtual cfgcache[] buffer
392 * which avoids changing internal mvebu registers. And changes Header
393 * Type response value to Type 1.
395 reg = readl(pcie->base + PCIE_DEV_REV_OFF);
397 reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
398 writel(reg, pcie->base + PCIE_DEV_REV_OFF);
401 * mvebu uses local bus number and local device number to determinate
402 * type of config request. Type 0 is used if target bus number equals
403 * local bus number and target device number differs from local device
404 * number. Type 1 is used if target bus number differs from local bus
405 * number. And when target bus number equals local bus number and
406 * target device equals local device number then request is routed to
407 * PCI Bridge which represent local PCIe Root Port.
409 * It means that PCI primary and secondary buses shares one bus number
410 * which is configured via local bus number. Determination if config
411 * request should go to primary or secondary bus is done based on local
414 * PCIe is point-to-point bus, so at secondary bus is always exactly one
415 * device with number 0. So set local device number to 1, it would not
416 * conflict with any device on secondary bus number and will ensure that
417 * accessing secondary bus and all buses behind secondary would work
418 * automatically and correctly. Therefore this configuration of local
419 * device number implies that setting of local bus number configures
420 * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
421 * later configure it via config write requests to the correct value.
422 * mvebu_pcie_write_config() catches config write requests which tries
423 * to change primary/secondary bus number and correctly updates local
424 * bus number based on new secondary bus number.
426 * With this configuration is PCI Bridge available at secondary bus as
427 * device number 1. But it must be available at primary bus as device
428 * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
429 * functions rewrite address to the real one when accessing primary bus.
431 mvebu_pcie_set_local_bus_nr(pcie, 0);
432 mvebu_pcie_set_local_dev_nr(pcie, 1);
434 pcie->mem.start = (u32)mvebu_pcie_membase;
435 pcie->mem.end = pcie->mem.start + MBUS_PCI_MEM_SIZE - 1;
436 mvebu_pcie_membase += MBUS_PCI_MEM_SIZE;
438 if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
439 (phys_addr_t)pcie->mem.start,
440 MBUS_PCI_MEM_SIZE)) {
441 printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
442 (u32)pcie->mem.start, MBUS_PCI_MEM_SIZE);
445 pcie->io.start = (u32)mvebu_pcie_iobase;
446 pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
447 mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
449 if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
450 (phys_addr_t)pcie->io.start,
452 printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
453 (u32)pcie->io.start, MBUS_PCI_IO_SIZE);
456 /* Setup windows and configure host bridge */
457 mvebu_pcie_setup_wins(pcie);
459 /* PCI memory space */
460 pci_set_region(hose->regions + 0, pcie->mem.start,
461 pcie->mem.start, MBUS_PCI_MEM_SIZE, PCI_REGION_MEM);
462 pci_set_region(hose->regions + 1,
465 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
466 pci_set_region(hose->regions + 2, pcie->io.start,
467 pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
468 hose->region_count = 3;
470 /* Set BAR0 to internal registers */
471 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
472 writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
474 /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
475 pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
476 PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
477 pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
478 PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
483 static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
488 addr = ofnode_get_property(node, "assigned-addresses", &len);
490 pr_err("property \"assigned-addresses\" not found");
491 return -FDT_ERR_NOTFOUND;
494 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
499 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
500 #define DT_TYPE_IO 0x1
501 #define DT_TYPE_MEM32 0x2
502 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
503 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
505 static int mvebu_get_tgt_attr(ofnode node, int devfn,
510 const int na = 3, ns = 2;
512 int rlen, nranges, rangesz, pna, i;
517 range = ofnode_get_property(node, "ranges", &rlen);
522 * Linux uses of_n_addr_cells() to get the number of address cells
523 * here. Currently this function is only available in U-Boot when
524 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
525 * general, lets't hardcode the "pna" value in the U-Boot code.
527 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
528 rangesz = pna + na + ns;
529 nranges = rlen / sizeof(__be32) / rangesz;
531 for (i = 0; i < nranges; i++, range += rangesz) {
532 u32 flags = of_read_number(range, 1);
533 u32 slot = of_read_number(range + 1, 1);
534 u64 cpuaddr = of_read_number(range + na, pna);
537 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
538 rtype = IORESOURCE_IO;
539 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
540 rtype = IORESOURCE_MEM;
545 * The Linux code used PCI_SLOT() here, which expects devfn
546 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
547 * only expects devfn in 15..8, where its saved in this driver.
549 if (slot == PCI_DEV(devfn) && type == rtype) {
550 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
551 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
559 static int mvebu_pcie_of_to_plat(struct udevice *dev)
561 struct mvebu_pcie *pcie = dev_get_plat(dev);
564 /* Get port number, lane number and memory target / attr */
565 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
571 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
574 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
576 /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
577 pcie->devfn = pci_get_devfn(dev);
578 if (pcie->devfn < 0) {
583 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
585 &pcie->mem_target, &pcie->mem_attr);
587 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
591 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
593 &pcie->io_target, &pcie->io_attr);
595 printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
599 /* Parse PCIe controller register base from DT */
600 ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
610 static const struct dm_pci_ops mvebu_pcie_ops = {
611 .read_config = mvebu_pcie_read_config,
612 .write_config = mvebu_pcie_write_config,
615 static struct driver pcie_mvebu_drv = {
616 .name = "pcie_mvebu",
618 .ops = &mvebu_pcie_ops,
619 .probe = mvebu_pcie_probe,
620 .of_to_plat = mvebu_pcie_of_to_plat,
621 .plat_auto = sizeof(struct mvebu_pcie),
625 * Use a MISC device to bind the n instances (child nodes) of the
626 * PCIe base controller in UCLASS_PCI.
628 static int mvebu_pcie_bind(struct udevice *parent)
630 struct mvebu_pcie *pcie;
631 struct uclass_driver *drv;
635 /* Lookup pci driver */
636 drv = lists_uclass_lookup(UCLASS_PCI);
638 puts("Cannot find PCI driver\n");
642 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
643 if (!ofnode_is_available(subnode))
646 pcie = calloc(1, sizeof(*pcie));
650 /* Create child device UCLASS_PCI and bind it */
651 device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
658 static const struct udevice_id mvebu_pcie_ids[] = {
659 { .compatible = "marvell,armada-xp-pcie" },
660 { .compatible = "marvell,armada-370-pcie" },
664 U_BOOT_DRIVER(pcie_mvebu_base) = {
665 .name = "pcie_mvebu_base",
667 .of_match = mvebu_pcie_ids,
668 .bind = mvebu_pcie_bind,