1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
11 #include <pci_msc01.h>
14 #define PCI_ACCESS_READ 0
15 #define PCI_ACCESS_WRITE 1
17 struct msc01_pci_controller {
18 struct pci_controller hose;
22 static inline struct msc01_pci_controller *
23 hose_to_msc01(struct pci_controller *hose)
25 return container_of(hose, struct msc01_pci_controller, hose);
28 static int msc01_config_access(struct msc01_pci_controller *msc01,
29 unsigned char access_type, pci_dev_t bdf,
32 const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
33 void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
34 void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
35 unsigned int bus = PCI_BUS(bdf);
36 unsigned int dev = PCI_DEV(bdf);
37 unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
39 /* clear abort status */
40 __raw_writel(aborts, intstat);
43 __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
44 (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
45 (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
46 ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
47 msc01->base + MSC01_PCI_CFGADDR_OFS);
50 if (access_type == PCI_ACCESS_WRITE)
51 __raw_writel(*data, cfgdata);
53 *data = __raw_readl(cfgdata);
55 /* check for aborts */
56 if (__raw_readl(intstat) & aborts) {
57 /* clear abort status */
58 __raw_writel(aborts, intstat);
65 static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
66 uint where, ulong *val, enum pci_size_t size)
68 struct msc01_pci_controller *msc01 = dev_get_priv(dev);
71 if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
72 *val = pci_get_ff(size);
76 *val = pci_conv_32_to_size(data, where, size);
81 static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
82 uint where, ulong val, enum pci_size_t size)
84 struct msc01_pci_controller *msc01 = dev_get_priv(dev);
87 if (size == PCI_SIZE_32) {
92 if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
95 data = pci_conv_size_to_32(old, val, where, size);
98 msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
103 static int msc01_pci_probe(struct udevice *dev)
105 struct msc01_pci_controller *msc01 = dev_get_priv(dev);
107 msc01->base = dev_remap_addr(dev);
114 static const struct dm_pci_ops msc01_pci_ops = {
115 .read_config = msc01_pci_read_config,
116 .write_config = msc01_pci_write_config,
119 static const struct udevice_id msc01_pci_ids[] = {
120 { .compatible = "mips,pci-msc01" },
124 U_BOOT_DRIVER(msc01_pci) = {
127 .of_match = msc01_pci_ids,
128 .ops = &msc01_pci_ops,
129 .probe = msc01_pci_probe,
130 .priv_auto = sizeof(struct msc01_pci_controller),