1 // SPDX-License-Identifier: GPL-2.0
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 #include <asm/bitops.h>
11 #include <asm/fsl_law.h>
13 struct mpc85xx_pci_priv {
14 void __iomem *cfg_addr;
15 void __iomem *cfg_data;
18 static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
19 uint offset, ulong *value,
22 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
25 addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
26 out_be32(priv->cfg_addr, addr);
28 *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
33 static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
34 uint offset, ulong value,
37 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
40 addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
41 out_be32(priv->cfg_addr, addr);
43 out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
50 mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
51 struct pci_region *pre)
54 * Unfortunately we have defines for this addresse,
55 * as we have to setup the TLB, and at this stage
56 * we have no access to DT ... may we check here
57 * if the value in the define is the same ?
60 set_next_law(mem->phys_start, law_size_bits(mem->size),
63 set_next_law(io->phys_start, law_size_bits(io->size),
66 set_next_law(pre->phys_start, law_size_bits(pre->size),
73 static int mpc85xx_pci_dm_probe(struct udevice *dev)
75 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
76 struct pci_region *io;
77 struct pci_region *mem;
78 struct pci_region *pre;
82 count = pci_get_regions(dev, &io, &mem, &pre);
84 printf("%s: wrong count of regions %d only 2 allowed\n",
90 mpc85xx_pci_dm_setup_laws(io, mem, pre);
93 pcix = priv->cfg_addr;
95 out_be32(&pcix->potar1, mem->bus_start >> 12);
96 out_be32(&pcix->potear1, (u64)mem->bus_start >> 44);
97 out_be32(&pcix->powbar1, mem->phys_start >> 12);
98 out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44);
99 out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
100 POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
103 out_be32(&pcix->potar2, io->bus_start >> 12);
104 out_be32(&pcix->potear2, (u64)io->bus_start >> 44);
105 out_be32(&pcix->powbar2, io->phys_start >> 12);
106 out_be32(&pcix->powbear2, (u64)io->phys_start >> 44);
107 out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
108 POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
110 out_be32(&pcix->pitar1, 0);
111 out_be32(&pcix->piwbar1, 0);
112 out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
113 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
115 out_be32(&pcix->powar3, 0);
116 out_be32(&pcix->powar4, 0);
117 out_be32(&pcix->piwar2, 0);
118 out_be32(&pcix->piwar3, 0);
123 static int mpc85xx_pci_dm_remove(struct udevice *dev)
128 static int mpc85xx_pci_of_to_plat(struct udevice *dev)
130 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
133 addr = devfdt_get_addr_index(dev, 0);
134 if (addr == FDT_ADDR_T_NONE)
136 priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE);
137 priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4);
142 static const struct dm_pci_ops mpc85xx_pci_ops = {
143 .read_config = mpc85xx_pci_dm_read_config,
144 .write_config = mpc85xx_pci_dm_write_config,
147 static const struct udevice_id mpc85xx_pci_ids[] = {
148 { .compatible = "fsl,mpc8540-pci" },
152 U_BOOT_DRIVER(mpc85xx_pci) = {
153 .name = "mpc85xx_pci",
155 .of_match = mpc85xx_pci_ids,
156 .ops = &mpc85xx_pci_ops,
157 .probe = mpc85xx_pci_dm_probe,
158 .remove = mpc85xx_pci_dm_remove,
159 .of_to_plat = mpc85xx_pci_of_to_plat,
160 .priv_auto = sizeof(struct mpc85xx_pci_priv),