1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
5 * Based on the Linux implementation.
6 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
7 * Authors: Carsten Langgaard <carstenl@mips.com>
8 * Maciej W. Rozycki <macro@mips.com>
16 #include <pci_gt64120.h>
20 #define PCI_ACCESS_READ 0
21 #define PCI_ACCESS_WRITE 1
31 struct gt64120_pci_controller {
32 struct pci_controller hose;
33 struct gt64120_regs *regs;
36 static inline struct gt64120_pci_controller *
37 hose_to_gt64120(struct pci_controller *hose)
39 return container_of(hose, struct gt64120_pci_controller, hose);
42 #define GT_INTRCAUSE_ABORT_BITS \
43 (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
45 static int gt_config_access(struct gt64120_pci_controller *gt,
46 unsigned char access_type, pci_dev_t bdf,
49 unsigned int bus = PCI_BUS(bdf);
50 unsigned int dev = PCI_DEV(bdf);
51 unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
56 if (bus == 0 && dev >= 31) {
57 /* Because of a bug in the galileo (for slot 31). */
61 if (access_type == PCI_ACCESS_WRITE)
62 debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
63 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
65 /* Clear cause register bits */
66 writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause);
68 addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
69 addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
70 addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
71 addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
74 writel(addr, >->regs->pci0_cfgaddr);
76 if (access_type == PCI_ACCESS_WRITE) {
77 if (bus == 0 && dev == 0) {
79 * The Galileo system controller is acting
80 * differently than other devices.
84 val = cpu_to_le32(*data);
87 writel(val, >->regs->pci0_cfgdata);
89 val = readl(>->regs->pci0_cfgdata);
91 if (bus == 0 && dev == 0) {
93 * The Galileo system controller is acting
94 * differently than other devices.
98 *data = le32_to_cpu(val);
102 /* Check for master or target abort */
103 intr = readl(>->regs->intrcause);
104 if (intr & GT_INTRCAUSE_ABORT_BITS) {
105 /* Error occurred, clear abort bits */
106 writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause);
110 if (access_type == PCI_ACCESS_READ)
111 debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
112 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
117 static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
118 int where, u32 *value)
120 struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
123 return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
126 static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
127 int where, u32 value)
129 struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
132 return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
135 void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
136 unsigned long sys_size, unsigned long mem_bus,
137 unsigned long mem_phys, unsigned long mem_size,
138 unsigned long io_bus, unsigned long io_phys,
139 unsigned long io_size)
141 static struct gt64120_pci_controller global_gt;
142 struct gt64120_pci_controller *gt;
143 struct pci_controller *hose;
150 hose->first_busno = 0;
151 hose->last_busno = 0;
153 /* System memory space */
154 pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
155 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
157 /* PCI memory space */
158 pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
162 pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
165 hose->region_count = 3;
168 pci_hose_read_config_byte_via_dword,
169 pci_hose_read_config_word_via_dword,
170 gt_read_config_dword,
171 pci_hose_write_config_byte_via_dword,
172 pci_hose_write_config_word_via_dword,
173 gt_write_config_dword);
175 pci_register_hose(hose);
176 hose->last_busno = pci_hose_scan(hose);