1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
5 * Based on the Linux implementation.
6 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
7 * Authors: Carsten Langgaard <carstenl@mips.com>
8 * Maciej W. Rozycki <macro@mips.com>
16 #include <pci_gt64120.h>
20 #define PCI_ACCESS_READ 0
21 #define PCI_ACCESS_WRITE 1
31 struct gt64120_pci_controller {
32 struct pci_controller hose;
33 struct gt64120_regs *regs;
36 static inline struct gt64120_pci_controller *
37 hose_to_gt64120(struct pci_controller *hose)
39 return container_of(hose, struct gt64120_pci_controller, hose);
42 #define GT_INTRCAUSE_ABORT_BITS \
43 (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
45 static int gt_config_access(struct gt64120_pci_controller *gt,
46 unsigned char access_type, pci_dev_t bdf,
49 unsigned int bus = PCI_BUS(bdf);
50 unsigned int dev = PCI_DEV(bdf);
51 unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
56 if (bus == 0 && dev >= 31) {
57 /* Because of a bug in the galileo (for slot 31). */
61 if (access_type == PCI_ACCESS_WRITE)
62 debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
63 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
65 /* Clear cause register bits */
66 writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause);
68 addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
69 addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
70 addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
71 addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
74 writel(addr, >->regs->pci0_cfgaddr);
76 if (access_type == PCI_ACCESS_WRITE) {
77 if (bus == 0 && dev == 0) {
79 * The Galileo system controller is acting
80 * differently than other devices.
84 val = cpu_to_le32(*data);
87 writel(val, >->regs->pci0_cfgdata);
89 val = readl(>->regs->pci0_cfgdata);
91 if (bus == 0 && dev == 0) {
93 * The Galileo system controller is acting
94 * differently than other devices.
98 *data = le32_to_cpu(val);
102 /* Check for master or target abort */
103 intr = readl(>->regs->intrcause);
104 if (intr & GT_INTRCAUSE_ABORT_BITS) {
105 /* Error occurred, clear abort bits */
106 writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause);
110 if (access_type == PCI_ACCESS_READ)
111 debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
112 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
117 static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
118 uint where, ulong *val,
119 enum pci_size_t size)
121 struct gt64120_pci_controller *gt = dev_get_priv(dev);
124 if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
125 *val = pci_get_ff(size);
129 *val = pci_conv_32_to_size(data, where, size);
134 static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
135 uint where, ulong val,
136 enum pci_size_t size)
138 struct gt64120_pci_controller *gt = dev_get_priv(dev);
141 if (size == PCI_SIZE_32) {
146 if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
149 data = pci_conv_size_to_32(old, val, where, size);
152 gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
157 static int gt64120_pci_probe(struct udevice *dev)
159 struct gt64120_pci_controller *gt = dev_get_priv(dev);
161 gt->regs = dev_remap_addr(dev);
168 static const struct dm_pci_ops gt64120_pci_ops = {
169 .read_config = gt64120_pci_read_config,
170 .write_config = gt64120_pci_write_config,
173 static const struct udevice_id gt64120_pci_ids[] = {
174 { .compatible = "marvell,pci-gt64120" },
178 U_BOOT_DRIVER(gt64120_pci) = {
179 .name = "gt64120_pci",
181 .of_match = gt64120_pci_ids,
182 .ops = >64120_pci_ops,
183 .probe = gt64120_pci_probe,
184 .priv_auto = sizeof(struct gt64120_pci_controller),