drivers/pci/pci_gt64120.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
   4  *
   5  * Based on the Linux implementation.
   6  *   Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
   7  *   Authors: Carsten Langgaard <carstenl@mips.com>
   8  *            Maciej W. Rozycki <macro@mips.com>
   9  */
  10
  11 #include <dm.h>
  12 #include <gt64120.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <pci.h>
  16 #include <pci_gt64120.h>
  17
  18 #include <asm/io.h>
  19
  20 #define PCI_ACCESS_READ  0
  21 #define PCI_ACCESS_WRITE 1
  22
  23 struct gt64120_regs {
  24         u8      unused_000[0xc18];
  25         u32     intrcause;
  26         u8      unused_c1c[0x0dc];
  27         u32     pci0_cfgaddr;
  28         u32     pci0_cfgdata;
  29 };
  30
  31 struct gt64120_pci_controller {
  32         struct pci_controller hose;
  33         struct gt64120_regs *regs;
  34 };
  35
  36 static inline struct gt64120_pci_controller *
  37 hose_to_gt64120(struct pci_controller *hose)
  38 {
  39         return container_of(hose, struct gt64120_pci_controller, hose);
  40 }
  41
  42 #define GT_INTRCAUSE_ABORT_BITS \
  43                 (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
  44
  45 static int gt_config_access(struct gt64120_pci_controller *gt,
  46                             unsigned char access_type, pci_dev_t bdf,
  47                             int where, u32 *data)
  48 {
  49         unsigned int bus = PCI_BUS(bdf);
  50         unsigned int dev = PCI_DEV(bdf);
  51         unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  52         u32 intr;
  53         u32 addr;
  54         u32 val;
  55
  56         if (bus == 0 && dev >= 31) {
  57                 /* Because of a bug in the galileo (for slot 31). */
  58                 return -1;
  59         }
  60
  61         if (access_type == PCI_ACCESS_WRITE)
  62                 debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
  63                       PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
  64
  65         /* Clear cause register bits */
  66         writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
  67
  68         addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
  69         addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
  70         addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
  71         addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
  72
  73         /* Setup address */
  74         writel(addr, &gt->regs->pci0_cfgaddr);
  75
  76         if (access_type == PCI_ACCESS_WRITE) {
  77                 if (bus == 0 && dev == 0) {
  78                         /*
  79                          * The Galileo system controller is acting
  80                          * differently than other devices.
  81                          */
  82                         val = *data;
  83                 } else {
  84                         val = cpu_to_le32(*data);
  85                 }
  86
  87                 writel(val, &gt->regs->pci0_cfgdata);
  88         } else {
  89                 val = readl(&gt->regs->pci0_cfgdata);
  90
  91                 if (bus == 0 && dev == 0) {
  92                         /*
  93                          * The Galileo system controller is acting
  94                          * differently than other devices.
  95                          */
  96                         *data = val;
  97                 } else {
  98                         *data = le32_to_cpu(val);
  99                 }
 100         }
 101
 102         /* Check for master or target abort */
 103         intr = readl(&gt->regs->intrcause);
 104         if (intr & GT_INTRCAUSE_ABORT_BITS) {
 105                 /* Error occurred, clear abort bits */
 106                 writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
 107                 return -1;
 108         }
 109
 110         if (access_type == PCI_ACCESS_READ)
 111                 debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
 112                       PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
 113
 114         return 0;
 115 }
 116
 117 static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
 118                                    uint where, ulong *val,
 119                                    enum pci_size_t size)
 120 {
 121         struct gt64120_pci_controller *gt = dev_get_priv(dev);
 122         u32 data = 0;
 123
 124         if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
 125                 *val = pci_get_ff(size);
 126                 return 0;
 127         }
 128
 129         *val = pci_conv_32_to_size(data, where, size);
 130
 131         return 0;
 132 }
 133
 134 static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
 135                                     uint where, ulong val,
 136                                     enum pci_size_t size)
 137 {
 138         struct gt64120_pci_controller *gt = dev_get_priv(dev);
 139         u32 data = 0;
 140
 141         if (size == PCI_SIZE_32) {
 142                 data = val;
 143         } else {
 144                 u32 old;
 145
 146                 if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
 147                         return 0;
 148
 149                 data = pci_conv_size_to_32(old, val, where, size);
 150         }
 151
 152         gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
 153
 154         return 0;
 155 }
 156
 157 static int gt64120_pci_probe(struct udevice *dev)
 158 {
 159         struct gt64120_pci_controller *gt = dev_get_priv(dev);
 160
 161         gt->regs = dev_remap_addr(dev);
 162         if (!gt->regs)
 163                 return -EINVAL;
 164
 165         return 0;
 166 }
 167
 168 static const struct dm_pci_ops gt64120_pci_ops = {
 169         .read_config    = gt64120_pci_read_config,
 170         .write_config   = gt64120_pci_write_config,
 171 };
 172
 173 static const struct udevice_id gt64120_pci_ids[] = {
 174         { .compatible = "marvell,pci-gt64120" },
 175         { }
 176 };
 177
 178 U_BOOT_DRIVER(gt64120_pci) = {
 179         .name           = "gt64120_pci",
 180         .id             = UCLASS_PCI,
 181         .of_match       = gt64120_pci_ids,
 182         .ops            = &gt64120_pci_ops,
 183         .probe          = gt64120_pci_probe,
 184         .priv_auto      = sizeof(struct gt64120_pci_controller),
 185 };