1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI autoconfiguration library
5 * Author: Matt Porter <mporter@mvista.com>
7 * Copyright 2000 MontaVista Software Inc.
15 #include "pci_internal.h"
17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
22 static void dm_pciauto_setup_device(struct udevice *dev,
23 struct pci_region *mem,
24 struct pci_region *prefetch,
25 struct pci_region *io)
35 struct pci_region *bar_res = NULL;
39 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
40 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
43 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
46 switch (header_type) {
47 case PCI_HEADER_TYPE_NORMAL:
50 case PCI_HEADER_TYPE_BRIDGE:
53 case PCI_HEADER_TYPE_CARDBUS:
54 /* CardBus header does not have any BAR */
58 /* Skip configuring BARs for unknown header types */
63 for (bar = PCI_BASE_ADDRESS_0;
64 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
67 /* Tickle the BAR and get the response */
68 dm_pci_write_config32(dev, bar, 0xffffffff);
69 dm_pci_read_config32(dev, bar, &bar_response);
71 /* If BAR is not implemented (or invalid) go to the next BAR */
72 if (!bar_response || bar_response == 0xffffffff)
77 /* Check the BAR type and set our address mask */
78 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
79 bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
80 bar_size &= ~(bar_size - 1);
84 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
85 bar_nr, (unsigned long long)bar_size);
87 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
88 PCI_BASE_ADDRESS_MEM_TYPE_64) {
89 u32 bar_response_upper;
92 dm_pci_write_config32(dev, bar + 4, 0xffffffff);
93 dm_pci_read_config32(dev, bar + 4,
96 bar64 = ((u64)bar_response_upper << 32) |
99 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
103 bar_size = (u32)(~(bar_response &
104 PCI_BASE_ADDRESS_MEM_MASK) + 1);
108 (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
113 debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
114 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
115 found_mem64 ? "64" : "",
116 (unsigned long long)bar_size);
119 ret = pciauto_region_allocate(bar_res, bar_size,
120 &bar_value, found_mem64);
122 printf("PCI: Failed autoconfig bar %x\n", bar);
125 /* Write it out and update our limit */
126 dm_pci_write_config32(dev, bar, (u32)bar_value);
130 #ifdef CONFIG_SYS_PCI_64BIT
131 dm_pci_write_config32(dev, bar,
132 (u32)(bar_value >> 32));
135 * If we are a 64-bit decoder then increment to
136 * the upper 32 bits of the bar and force it to
137 * locate in the lower 4GB of memory.
139 dm_pci_write_config32(dev, bar, 0x00000000);
144 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
145 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
152 /* Configure the expansion ROM address */
153 if (header_type == PCI_HEADER_TYPE_NORMAL ||
154 header_type == PCI_HEADER_TYPE_BRIDGE) {
155 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
156 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
157 dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
158 dm_pci_read_config32(dev, rom_addr, &bar_response);
160 bar_size = -(bar_response & ~1);
161 debug("PCI Autoconfig: ROM, size=%#x, ",
162 (unsigned int)bar_size);
163 if (pciauto_region_allocate(mem, bar_size, &bar_value,
165 dm_pci_write_config32(dev, rom_addr, bar_value);
167 cmdstat |= PCI_COMMAND_MEMORY;
172 /* PCI_COMMAND_IO must be set for VGA device */
173 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
174 if (class == PCI_CLASS_DISPLAY_VGA)
175 cmdstat |= PCI_COMMAND_IO;
177 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
178 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
179 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
180 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
183 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
185 struct pci_region *pci_mem;
186 struct pci_region *pci_prefetch;
187 struct pci_region *pci_io;
188 u16 cmdstat, prefechable_64;
190 struct udevice *ctlr = pci_get_controller(dev);
191 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
193 pci_mem = ctlr_hose->pci_mem;
194 pci_prefetch = ctlr_hose->pci_prefetch;
195 pci_io = ctlr_hose->pci_io;
197 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
198 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
199 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
200 dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
201 io_32 &= PCI_IO_RANGE_TYPE_MASK;
203 /* Configure bus number registers */
204 dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
205 PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
206 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
207 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
210 /* Round memory allocator to 1MB boundary */
211 pciauto_region_align(pci_mem, 0x100000);
214 * Set up memory and I/O filter limits, assume 32-bit
217 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
218 ((pci_mem->bus_lower & 0xfff00000) >> 16) &
219 PCI_MEMORY_RANGE_MASK);
221 cmdstat |= PCI_COMMAND_MEMORY;
225 /* Round memory allocator to 1MB boundary */
226 pciauto_region_align(pci_prefetch, 0x100000);
229 * Set up memory and I/O filter limits, assume 32-bit
232 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
233 (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
234 PCI_PREF_RANGE_MASK) | prefechable_64);
235 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
236 #ifdef CONFIG_SYS_PCI_64BIT
237 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
238 pci_prefetch->bus_lower >> 32);
240 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
243 cmdstat |= PCI_COMMAND_MEMORY;
245 /* We don't support prefetchable memory for now, so disable */
246 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 |
248 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
250 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
251 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
252 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
257 /* Round I/O allocator to 4KB boundary */
258 pciauto_region_align(pci_io, 0x1000);
260 dm_pci_write_config8(dev, PCI_IO_BASE,
261 (((pci_io->bus_lower & 0x0000f000) >> 8) &
262 PCI_IO_RANGE_MASK) | io_32);
263 if (io_32 == PCI_IO_RANGE_TYPE_32)
264 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
265 (pci_io->bus_lower & 0xffff0000) >> 16);
267 cmdstat |= PCI_COMMAND_IO;
269 /* Disable I/O if unsupported */
270 dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32);
271 dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32);
272 if (io_32 == PCI_IO_RANGE_TYPE_32) {
273 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0);
274 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0);
278 /* Enable memory and I/O accesses, enable bus master */
279 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
282 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
284 struct pci_region *pci_mem;
285 struct pci_region *pci_prefetch;
286 struct pci_region *pci_io;
287 struct udevice *ctlr = pci_get_controller(dev);
288 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
290 pci_mem = ctlr_hose->pci_mem;
291 pci_prefetch = ctlr_hose->pci_prefetch;
292 pci_io = ctlr_hose->pci_io;
294 /* Configure bus number registers */
295 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
298 /* Round memory allocator to 1MB boundary */
299 pciauto_region_align(pci_mem, 0x100000);
301 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
302 ((pci_mem->bus_lower - 1) >> 16) &
303 PCI_MEMORY_RANGE_MASK);
309 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
311 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
313 /* Round memory allocator to 1MB boundary */
314 pciauto_region_align(pci_prefetch, 0x100000);
316 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
317 (((pci_prefetch->bus_lower - 1) >> 16) &
318 PCI_PREF_RANGE_MASK) | prefechable_64);
319 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
320 #ifdef CONFIG_SYS_PCI_64BIT
321 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
322 (pci_prefetch->bus_lower - 1) >> 32);
324 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
331 dm_pci_read_config8(dev, PCI_IO_LIMIT,
333 io_32 &= PCI_IO_RANGE_TYPE_MASK;
335 /* Round I/O allocator to 4KB boundary */
336 pciauto_region_align(pci_io, 0x1000);
338 dm_pci_write_config8(dev, PCI_IO_LIMIT,
339 ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
340 PCI_IO_RANGE_MASK) | io_32);
341 if (io_32 == PCI_IO_RANGE_TYPE_32)
342 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
343 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
348 * HJF: Changed this to return int. I think this is required
349 * to get the correct result when scanning bridges
351 int dm_pciauto_config_device(struct udevice *dev)
353 struct pci_region *pci_mem;
354 struct pci_region *pci_prefetch;
355 struct pci_region *pci_io;
356 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
357 unsigned short class;
358 struct udevice *ctlr = pci_get_controller(dev);
359 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
362 pci_mem = ctlr_hose->pci_mem;
363 pci_prefetch = ctlr_hose->pci_prefetch;
364 pci_io = ctlr_hose->pci_io;
366 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
369 case PCI_CLASS_BRIDGE_PCI:
370 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
371 PCI_DEV(dm_pci_get_bdf(dev)));
373 dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
375 ret = dm_pci_hose_probe_bus(dev);
377 return log_msg_ret("probe", ret);
381 case PCI_CLASS_BRIDGE_CARDBUS:
383 * just do a minimal setup of the bridge,
384 * let the OS take care of the rest
386 dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
388 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
389 PCI_DEV(dm_pci_get_bdf(dev)));
393 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
394 case PCI_CLASS_BRIDGE_OTHER:
395 debug("PCI Autoconfig: Skipping bridge device %d\n",
396 PCI_DEV(dm_pci_get_bdf(dev)));
399 #if defined(CONFIG_ARCH_MPC834X)
400 case PCI_CLASS_BRIDGE_OTHER:
402 * The host/PCI bridge 1 seems broken in 8349 - it presents
403 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
404 * device claiming resources io/mem/irq.. we only allow for
405 * the PIMMR window to be allocated (BAR0 - 1MB size)
407 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
408 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
409 hose->pci_prefetch, hose->pci_io);
413 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
414 debug("PCI AutoConfig: Found PowerPC device\n");
418 dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);