drivers/pci/pci_auto.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <errno.h>
  15 #include <pci.h>
  16
  17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  20 #endif
  21
  22 /*
  23  *
  24  */
  25
  26 void pciauto_region_init(struct pci_region *res)
  27 {
  28         /*
  29          * Avoid allocating PCI resources from address 0 -- this is illegal
  30          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  31          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  32          */
  33         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  34 }
  35
  36 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  37 {
  38         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  39 }
  40
  41 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  42         pci_addr_t *bar)
  43 {
  44         pci_addr_t addr;
  45
  46         if (!res) {
  47                 debug("No resource");
  48                 goto error;
  49         }
  50
  51         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  52
  53         if (addr - res->bus_start + size > res->size) {
  54                 debug("No room in resource");
  55                 goto error;
  56         }
  57
  58         res->bus_lower = addr + size;
  59
  60         debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr,
  61               (unsigned long long)res->bus_lower);
  62
  63         *bar = addr;
  64         return 0;
  65
  66  error:
  67         *bar = (pci_addr_t)-1;
  68         return -1;
  69 }
  70
  71 /*
  72  *
  73  */
  74
  75 void pciauto_setup_device(struct pci_controller *hose,
  76                           pci_dev_t dev, int bars_num,
  77                           struct pci_region *mem,
  78                           struct pci_region *prefetch,
  79                           struct pci_region *io)
  80 {
  81         u32 bar_response;
  82         pci_size_t bar_size;
  83         u16 cmdstat = 0;
  84         int bar, bar_nr = 0;
  85 #ifndef CONFIG_PCI_ENUM_ONLY
  86         u8 header_type;
  87         int rom_addr;
  88         pci_addr_t bar_value;
  89         struct pci_region *bar_res;
  90         int found_mem64 = 0;
  91 #endif
  92         u16 class;
  93
  94         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  95         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  96
  97         for (bar = PCI_BASE_ADDRESS_0;
  98                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  99                 /* Tickle the BAR and get the response */
 100 #ifndef CONFIG_PCI_ENUM_ONLY
 101                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 102 #endif
 103                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 104
 105                 /* If BAR is not implemented go to the next BAR */
 106                 if (!bar_response)
 107                         continue;
 108
 109 #ifndef CONFIG_PCI_ENUM_ONLY
 110                 found_mem64 = 0;
 111 #endif
 112
 113                 /* Check the BAR type and set our address mask */
 114                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 115                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 116                                    & 0xffff) + 1;
 117 #ifndef CONFIG_PCI_ENUM_ONLY
 118                         bar_res = io;
 119 #endif
 120
 121                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
 122                               bar_nr, (unsigned long long)bar_size);
 123                 } else {
 124                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 125                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 126                                 u32 bar_response_upper;
 127                                 u64 bar64;
 128
 129 #ifndef CONFIG_PCI_ENUM_ONLY
 130                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 131                                         0xffffffff);
 132 #endif
 133                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 134                                         &bar_response_upper);
 135
 136                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 137
 138                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 139 #ifndef CONFIG_PCI_ENUM_ONLY
 140                                 found_mem64 = 1;
 141 #endif
 142                         } else {
 143                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 144                         }
 145 #ifndef CONFIG_PCI_ENUM_ONLY
 146                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 147                                 bar_res = prefetch;
 148                         else
 149                                 bar_res = mem;
 150 #endif
 151
 152                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
 153                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
 154                               (unsigned long long)bar_size);
 155                 }
 156
 157 #ifndef CONFIG_PCI_ENUM_ONLY
 158                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 159                         /* Write it out and update our limit */
 160                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 161
 162                         if (found_mem64) {
 163                                 bar += 4;
 164 #ifdef CONFIG_SYS_PCI_64BIT
 165                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 166 #else
 167                                 /*
 168                                  * If we are a 64-bit decoder then increment to the
 169                                  * upper 32 bits of the bar and force it to locate
 170                                  * in the lower 4GB of memory.
 171                                  */
 172                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 173 #endif
 174                         }
 175
 176                 }
 177 #endif
 178                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 179                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 180
 181                 debug("\n");
 182
 183                 bar_nr++;
 184         }
 185
 186 #ifndef CONFIG_PCI_ENUM_ONLY
 187         /* Configure the expansion ROM address */
 188         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 189         header_type &= 0x7f;
 190         if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 191                 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 192                            PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 193                 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
 194                 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
 195                 if (bar_response) {
 196                         bar_size = -(bar_response & ~1);
 197                         debug("PCI Autoconfig: ROM, size=%#x, ",
 198                               (unsigned int)bar_size);
 199                         if (pciauto_region_allocate(mem, bar_size,
 200                                                     &bar_value) == 0) {
 201                                 pci_hose_write_config_dword(hose, dev, rom_addr,
 202                                                             bar_value);
 203                         }
 204                         cmdstat |= PCI_COMMAND_MEMORY;
 205                         debug("\n");
 206                 }
 207         }
 208 #endif
 209
 210         /* PCI_COMMAND_IO must be set for VGA device */
 211         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 212         if (class == PCI_CLASS_DISPLAY_VGA)
 213                 cmdstat |= PCI_COMMAND_IO;
 214
 215         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 216         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 217                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 218         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 219 }
 220
 221 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 222                                          pci_dev_t dev, int sub_bus)
 223 {
 224         struct pci_region *pci_mem;
 225         struct pci_region *pci_prefetch;
 226         struct pci_region *pci_io;
 227         u16 cmdstat, prefechable_64;
 228
 229 #ifdef CONFIG_DM_PCI
 230         /* The root controller has the region information */
 231         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 232
 233         pci_mem = ctlr_hose->pci_mem;
 234         pci_prefetch = ctlr_hose->pci_prefetch;
 235         pci_io = ctlr_hose->pci_io;
 236 #else
 237         pci_mem = hose->pci_mem;
 238         pci_prefetch = hose->pci_prefetch;
 239         pci_io = hose->pci_io;
 240 #endif
 241
 242         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 243         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 244                                 &prefechable_64);
 245         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 246
 247         /* Configure bus number registers */
 248 #ifdef CONFIG_DM_PCI
 249         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
 250         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
 251 #else
 252         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 253                                    PCI_BUS(dev) - hose->first_busno);
 254         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 255                                    sub_bus - hose->first_busno);
 256 #endif
 257         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 258
 259         if (pci_mem) {
 260                 /* Round memory allocator to 1MB boundary */
 261                 pciauto_region_align(pci_mem, 0x100000);
 262
 263                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 264                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 265                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 266
 267                 cmdstat |= PCI_COMMAND_MEMORY;
 268         }
 269
 270         if (pci_prefetch) {
 271                 /* Round memory allocator to 1MB boundary */
 272                 pciauto_region_align(pci_prefetch, 0x100000);
 273
 274                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 275                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 276                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 277                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 278 #ifdef CONFIG_SYS_PCI_64BIT
 279                         pci_hose_write_config_dword(hose, dev,
 280                                         PCI_PREF_BASE_UPPER32,
 281                                         pci_prefetch->bus_lower >> 32);
 282 #else
 283                         pci_hose_write_config_dword(hose, dev,
 284                                         PCI_PREF_BASE_UPPER32,
 285                                         0x0);
 286 #endif
 287
 288                 cmdstat |= PCI_COMMAND_MEMORY;
 289         } else {
 290                 /* We don't support prefetchable memory for now, so disable */
 291                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 292                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 293                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 294                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 295                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 296                 }
 297         }
 298
 299         if (pci_io) {
 300                 /* Round I/O allocator to 4KB boundary */
 301                 pciauto_region_align(pci_io, 0x1000);
 302
 303                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 304                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 305                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 306                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 307
 308                 cmdstat |= PCI_COMMAND_IO;
 309         }
 310
 311         /* Enable memory and I/O accesses, enable bus master */
 312         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 313                                         cmdstat | PCI_COMMAND_MASTER);
 314 }
 315
 316 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 317                                           pci_dev_t dev, int sub_bus)
 318 {
 319         struct pci_region *pci_mem;
 320         struct pci_region *pci_prefetch;
 321         struct pci_region *pci_io;
 322
 323 #ifdef CONFIG_DM_PCI
 324         /* The root controller has the region information */
 325         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 326
 327         pci_mem = ctlr_hose->pci_mem;
 328         pci_prefetch = ctlr_hose->pci_prefetch;
 329         pci_io = ctlr_hose->pci_io;
 330 #else
 331         pci_mem = hose->pci_mem;
 332         pci_prefetch = hose->pci_prefetch;
 333         pci_io = hose->pci_io;
 334 #endif
 335
 336         /* Configure bus number registers */
 337 #ifdef CONFIG_DM_PCI
 338         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
 339 #else
 340         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 341                                    sub_bus - hose->first_busno);
 342 #endif
 343
 344         if (pci_mem) {
 345                 /* Round memory allocator to 1MB boundary */
 346                 pciauto_region_align(pci_mem, 0x100000);
 347
 348                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 349                                 (pci_mem->bus_lower - 1) >> 16);
 350         }
 351
 352         if (pci_prefetch) {
 353                 u16 prefechable_64;
 354
 355                 pci_hose_read_config_word(hose, dev,
 356                                         PCI_PREF_MEMORY_LIMIT,
 357                                         &prefechable_64);
 358                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 359
 360                 /* Round memory allocator to 1MB boundary */
 361                 pciauto_region_align(pci_prefetch, 0x100000);
 362
 363                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 364                                 (pci_prefetch->bus_lower - 1) >> 16);
 365                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 366 #ifdef CONFIG_SYS_PCI_64BIT
 367                         pci_hose_write_config_dword(hose, dev,
 368                                         PCI_PREF_LIMIT_UPPER32,
 369                                         (pci_prefetch->bus_lower - 1) >> 32);
 370 #else
 371                         pci_hose_write_config_dword(hose, dev,
 372                                         PCI_PREF_LIMIT_UPPER32,
 373                                         0x0);
 374 #endif
 375         }
 376
 377         if (pci_io) {
 378                 /* Round I/O allocator to 4KB boundary */
 379                 pciauto_region_align(pci_io, 0x1000);
 380
 381                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 382                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 383                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 384                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 385         }
 386 }
 387
 388 /*
 389  *
 390  */
 391
 392 void pciauto_config_init(struct pci_controller *hose)
 393 {
 394         int i;
 395
 396         hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
 397
 398         for (i = 0; i < hose->region_count; i++) {
 399                 switch(hose->regions[i].flags) {
 400                 case PCI_REGION_IO:
 401                         if (!hose->pci_io ||
 402                             hose->pci_io->size < hose->regions[i].size)
 403                                 hose->pci_io = hose->regions + i;
 404                         break;
 405                 case PCI_REGION_MEM:
 406                         if (!hose->pci_mem ||
 407                             hose->pci_mem->size < hose->regions[i].size)
 408                                 hose->pci_mem = hose->regions + i;
 409                         break;
 410                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 411                         if (!hose->pci_prefetch ||
 412                             hose->pci_prefetch->size < hose->regions[i].size)
 413                                 hose->pci_prefetch = hose->regions + i;
 414                         break;
 415                 }
 416         }
 417
 418
 419         if (hose->pci_mem) {
 420                 pciauto_region_init(hose->pci_mem);
 421
 422                 debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 423                        "\t\tPhysical Memory [%llx-%llxx]\n",
 424                     (u64)hose->pci_mem->bus_start,
 425                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 426                     (u64)hose->pci_mem->phys_start,
 427                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 428         }
 429
 430         if (hose->pci_prefetch) {
 431                 pciauto_region_init(hose->pci_prefetch);
 432
 433                 debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 434                        "\t\tPhysical Memory [%llx-%llx]\n",
 435                     (u64)hose->pci_prefetch->bus_start,
 436                     (u64)(hose->pci_prefetch->bus_start +
 437                             hose->pci_prefetch->size - 1),
 438                     (u64)hose->pci_prefetch->phys_start,
 439                     (u64)(hose->pci_prefetch->phys_start +
 440                             hose->pci_prefetch->size - 1));
 441         }
 442
 443         if (hose->pci_io) {
 444                 pciauto_region_init(hose->pci_io);
 445
 446                 debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 447                        "\t\tPhysical Memory: [%llx-%llx]\n",
 448                     (u64)hose->pci_io->bus_start,
 449                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 450                     (u64)hose->pci_io->phys_start,
 451                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 452
 453         }
 454 }
 455
 456 /*
 457  * HJF: Changed this to return int. I think this is required
 458  * to get the correct result when scanning bridges
 459  */
 460 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 461 {
 462         struct pci_region *pci_mem;
 463         struct pci_region *pci_prefetch;
 464         struct pci_region *pci_io;
 465         unsigned int sub_bus = PCI_BUS(dev);
 466         unsigned short class;
 467         int n;
 468
 469 #ifdef CONFIG_DM_PCI
 470         /* The root controller has the region information */
 471         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 472
 473         pci_mem = ctlr_hose->pci_mem;
 474         pci_prefetch = ctlr_hose->pci_prefetch;
 475         pci_io = ctlr_hose->pci_io;
 476 #else
 477         pci_mem = hose->pci_mem;
 478         pci_prefetch = hose->pci_prefetch;
 479         pci_io = hose->pci_io;
 480 #endif
 481
 482         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 483
 484         switch (class) {
 485         case PCI_CLASS_BRIDGE_PCI:
 486                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 487                       PCI_DEV(dev));
 488
 489                 pciauto_setup_device(hose, dev, 2, pci_mem,
 490                                      pci_prefetch, pci_io);
 491
 492 #ifdef CONFIG_DM_PCI
 493                 n = dm_pci_hose_probe_bus(hose, dev);
 494                 if (n < 0)
 495                         return n;
 496                 sub_bus = (unsigned int)n;
 497 #else
 498                 /* Passing in current_busno allows for sibling P2P bridges */
 499                 hose->current_busno++;
 500                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 501                 /*
 502                  * need to figure out if this is a subordinate bridge on the bus
 503                  * to be able to properly set the pri/sec/sub bridge registers.
 504                  */
 505                 n = pci_hose_scan_bus(hose, hose->current_busno);
 506
 507                 /* figure out the deepest we've gone for this leg */
 508                 sub_bus = max((unsigned int)n, sub_bus);
 509                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 510
 511                 sub_bus = hose->current_busno;
 512 #endif
 513                 break;
 514
 515         case PCI_CLASS_BRIDGE_CARDBUS:
 516                 /*
 517                  * just do a minimal setup of the bridge,
 518                  * let the OS take care of the rest
 519                  */
 520                 pciauto_setup_device(hose, dev, 0, pci_mem,
 521                                      pci_prefetch, pci_io);
 522
 523                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 524                       PCI_DEV(dev));
 525
 526 #ifndef CONFIG_DM_PCI
 527                 hose->current_busno++;
 528 #endif
 529                 break;
 530
 531 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 532         case PCI_CLASS_BRIDGE_OTHER:
 533                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 534                       PCI_DEV(dev));
 535                 break;
 536 #endif
 537 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 538         case PCI_CLASS_BRIDGE_OTHER:
 539                 /*
 540                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 541                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 542                  * device claiming resources io/mem/irq.. we only allow for
 543                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 544                  */
 545                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 546                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 547                         hose->pci_prefetch, hose->pci_io);
 548                 break;
 549 #endif
 550
 551         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 552                 debug("PCI AutoConfig: Found PowerPC device\n");
 553
 554         default:
 555                 pciauto_setup_device(hose, dev, 6, pci_mem,
 556                                      pci_prefetch, pci_io);
 557                 break;
 558         }
 559
 560         return sub_bus;
 561 }