1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3hot_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3hot_delay;
69 if (delay < pci_pm_d3hot_delay)
70 delay = pci_pm_d3hot_delay;
76 bool pci_reset_supported(struct pci_dev *dev)
78 return dev->reset_methods[0] != 0;
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported = 1;
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
89 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
101 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
102 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
118 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
127 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
128 u8 pci_cache_line_size;
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
134 unsigned int pcibios_max_latency = 255;
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled;
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled;
142 /* If set, the PCI config space of each device is printed during boot. */
145 bool pci_ats_disabled(void)
147 return pcie_ats_disabled;
149 EXPORT_SYMBOL_GPL(pci_ats_disabled);
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force;
156 static int __init pcie_port_pm_setup(char *str)
158 if (!strcmp(str, "off"))
159 pci_bridge_d3_disable = true;
160 else if (!strcmp(str, "force"))
161 pci_bridge_d3_force = true;
164 __setup("pcie_port_pm=", pcie_port_pm_setup);
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
171 * @bus: pointer to PCI bus structure to search
173 * Given a PCI bus, returns the highest PCI bus number present in the set
174 * including the given PCI bus and its list of child PCI buses.
176 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
179 unsigned char max, n;
181 max = bus->busn_res.end;
182 list_for_each_entry(tmp, &bus->children, node) {
183 n = pci_bus_max_busnr(tmp);
189 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
193 * @pdev: the PCI device
195 * Returns error bits set in PCI_STATUS and clears them.
197 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
202 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
203 if (ret != PCIBIOS_SUCCESSFUL)
206 status &= PCI_STATUS_ERROR_BITS;
208 pci_write_config_word(pdev, PCI_STATUS, status);
212 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
214 #ifdef CONFIG_HAS_IOMEM
215 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
218 struct resource *res = &pdev->resource[bar];
219 resource_size_t start = res->start;
220 resource_size_t size = resource_size(res);
223 * Make sure the BAR is actually a memory resource, not an IO resource
225 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
226 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
231 return ioremap_wc(start, size);
233 return ioremap(start, size);
236 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
238 return __pci_ioremap_resource(pdev, bar, false);
240 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
242 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
244 return __pci_ioremap_resource(pdev, bar, true);
246 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
250 * pci_dev_str_match_path - test if a path string matches a device
251 * @dev: the PCI device to test
252 * @path: string to match the device against
253 * @endptr: pointer to the string after the match
255 * Test if a string (typically from a kernel parameter) formatted as a
256 * path of device/function addresses matches a PCI device. The string must
259 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
261 * A path for a device can be obtained using 'lspci -t'. Using a path
262 * is more robust against bus renumbering than using only a single bus,
263 * device and function address.
265 * Returns 1 if the string matches the device, 0 if it does not and
266 * a negative error code if it fails to parse the string.
268 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
272 int seg, bus, slot, func;
276 *endptr = strchrnul(path, ';');
278 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
283 p = strrchr(wpath, '/');
286 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
292 if (dev->devfn != PCI_DEVFN(slot, func)) {
298 * Note: we don't need to get a reference to the upstream
299 * bridge because we hold a reference to the top level
300 * device which should hold a reference to the bridge,
303 dev = pci_upstream_bridge(dev);
312 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
316 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
323 ret = (seg == pci_domain_nr(dev->bus) &&
324 bus == dev->bus->number &&
325 dev->devfn == PCI_DEVFN(slot, func));
333 * pci_dev_str_match - test if a string matches a device
334 * @dev: the PCI device to test
335 * @p: string to match the device against
336 * @endptr: pointer to the string after the match
338 * Test if a string (typically from a kernel parameter) matches a specified
339 * PCI device. The string may be of one of the following formats:
341 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
342 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
344 * The first format specifies a PCI bus/device/function address which
345 * may change if new hardware is inserted, if motherboard firmware changes,
346 * or due to changes caused in kernel parameters. If the domain is
347 * left unspecified, it is taken to be 0. In order to be robust against
348 * bus renumbering issues, a path of PCI device/function numbers may be used
349 * to address the specific device. The path for a device can be determined
350 * through the use of 'lspci -t'.
352 * The second format matches devices using IDs in the configuration
353 * space which may match multiple devices in the system. A value of 0
354 * for any field will match all devices. (Note: this differs from
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
356 * legacy reasons and convenience so users don't have to specify
357 * FFFFFFFFs on the command line.)
359 * Returns 1 if the string matches the device, 0 if it does not and
360 * a negative error code if the string cannot be parsed.
362 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
367 unsigned short vendor, device, subsystem_vendor, subsystem_device;
369 if (strncmp(p, "pci:", 4) == 0) {
370 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
372 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
373 &subsystem_vendor, &subsystem_device, &count);
375 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
379 subsystem_vendor = 0;
380 subsystem_device = 0;
385 if ((!vendor || vendor == dev->vendor) &&
386 (!device || device == dev->device) &&
387 (!subsystem_vendor ||
388 subsystem_vendor == dev->subsystem_vendor) &&
389 (!subsystem_device ||
390 subsystem_device == dev->subsystem_device))
394 * PCI Bus, Device, Function IDs are specified
395 * (optionally, may include a path of devfns following it)
397 ret = pci_dev_str_match_path(dev, p, &p);
412 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
413 u8 pos, int cap, int *ttl)
418 pci_bus_read_config_byte(bus, devfn, pos, &pos);
424 pci_bus_read_config_word(bus, devfn, pos, &ent);
436 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
439 int ttl = PCI_FIND_CAP_TTL;
441 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
444 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
446 return __pci_find_next_cap(dev->bus, dev->devfn,
447 pos + PCI_CAP_LIST_NEXT, cap);
449 EXPORT_SYMBOL_GPL(pci_find_next_capability);
451 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
452 unsigned int devfn, u8 hdr_type)
456 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
457 if (!(status & PCI_STATUS_CAP_LIST))
461 case PCI_HEADER_TYPE_NORMAL:
462 case PCI_HEADER_TYPE_BRIDGE:
463 return PCI_CAPABILITY_LIST;
464 case PCI_HEADER_TYPE_CARDBUS:
465 return PCI_CB_CAPABILITY_LIST;
472 * pci_find_capability - query for devices' capabilities
473 * @dev: PCI device to query
474 * @cap: capability code
476 * Tell if a device supports a given PCI capability.
477 * Returns the address of the requested capability structure within the
478 * device's PCI configuration space or 0 in case the device does not
479 * support it. Possible values for @cap include:
481 * %PCI_CAP_ID_PM Power Management
482 * %PCI_CAP_ID_AGP Accelerated Graphics Port
483 * %PCI_CAP_ID_VPD Vital Product Data
484 * %PCI_CAP_ID_SLOTID Slot Identification
485 * %PCI_CAP_ID_MSI Message Signalled Interrupts
486 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
487 * %PCI_CAP_ID_PCIX PCI-X
488 * %PCI_CAP_ID_EXP PCI Express
490 u8 pci_find_capability(struct pci_dev *dev, int cap)
494 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
496 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
500 EXPORT_SYMBOL(pci_find_capability);
503 * pci_bus_find_capability - query for devices' capabilities
504 * @bus: the PCI bus to query
505 * @devfn: PCI device to query
506 * @cap: capability code
508 * Like pci_find_capability() but works for PCI devices that do not have a
509 * pci_dev structure set up yet.
511 * Returns the address of the requested capability structure within the
512 * device's PCI configuration space or 0 in case the device does not
515 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
519 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
521 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
523 pos = __pci_find_next_cap(bus, devfn, pos, cap);
527 EXPORT_SYMBOL(pci_bus_find_capability);
530 * pci_find_next_ext_capability - Find an extended capability
531 * @dev: PCI device to query
532 * @start: address at which to start looking (0 to start at beginning of list)
533 * @cap: capability code
535 * Returns the address of the next matching extended capability structure
536 * within the device's PCI configuration space or 0 if the device does
537 * not support it. Some capabilities can occur several times, e.g., the
538 * vendor-specific capability, and this provides a way to find them all.
540 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
544 u16 pos = PCI_CFG_SPACE_SIZE;
546 /* minimum 8 bytes per capability */
547 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
549 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
555 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
559 * If we have no capabilities, this is indicated by cap ID,
560 * cap version and next pointer all being 0.
566 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
569 pos = PCI_EXT_CAP_NEXT(header);
570 if (pos < PCI_CFG_SPACE_SIZE)
573 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
579 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
582 * pci_find_ext_capability - Find an extended capability
583 * @dev: PCI device to query
584 * @cap: capability code
586 * Returns the address of the requested extended capability structure
587 * within the device's PCI configuration space or 0 if the device does
588 * not support it. Possible values for @cap include:
590 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
591 * %PCI_EXT_CAP_ID_VC Virtual Channel
592 * %PCI_EXT_CAP_ID_DSN Device Serial Number
593 * %PCI_EXT_CAP_ID_PWR Power Budgeting
595 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
597 return pci_find_next_ext_capability(dev, 0, cap);
599 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
603 * @dev: PCI device to query
605 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
608 * Returns the DSN, or zero if the capability does not exist.
610 u64 pci_get_dsn(struct pci_dev *dev)
616 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
621 * The Device Serial Number is two dwords offset 4 bytes from the
622 * capability position. The specification says that the first dword is
623 * the lower half, and the second dword is the upper half.
626 pci_read_config_dword(dev, pos, &dword);
628 pci_read_config_dword(dev, pos + 4, &dword);
629 dsn |= ((u64)dword) << 32;
633 EXPORT_SYMBOL_GPL(pci_get_dsn);
635 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
637 int rc, ttl = PCI_FIND_CAP_TTL;
640 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
641 mask = HT_3BIT_CAP_MASK;
643 mask = HT_5BIT_CAP_MASK;
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
646 PCI_CAP_ID_HT, &ttl);
648 rc = pci_read_config_byte(dev, pos + 3, &cap);
649 if (rc != PCIBIOS_SUCCESSFUL)
652 if ((cap & mask) == ht_cap)
655 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
656 pos + PCI_CAP_LIST_NEXT,
657 PCI_CAP_ID_HT, &ttl);
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
665 * @dev: PCI device to query
666 * @pos: Position from which to continue searching
667 * @ht_cap: HyperTransport capability code
669 * To be used in conjunction with pci_find_ht_capability() to search for
670 * all capabilities matching @ht_cap. @pos should always be a value returned
671 * from pci_find_ht_capability().
673 * NB. To be 100% safe against broken PCI devices, the caller should take
674 * steps to avoid an infinite loop.
676 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
678 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
680 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
684 * @dev: PCI device to query
685 * @ht_cap: HyperTransport capability code
687 * Tell if a device supports a given HyperTransport capability.
688 * Returns an address within the device's PCI configuration space
689 * or 0 in case the device does not support the request capability.
690 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
691 * which has a HyperTransport capability matching @ht_cap.
693 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
697 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
699 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
703 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
707 * @dev: PCI device to query
708 * @vendor: Vendor ID for which capability is defined
709 * @cap: Vendor-specific capability ID
711 * If @dev has Vendor ID @vendor, search for a VSEC capability with
712 * VSEC ID @cap. If found, return the capability offset in
713 * config space; otherwise return 0.
715 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
720 if (vendor != dev->vendor)
723 while ((vsec = pci_find_next_ext_capability(dev, vsec,
724 PCI_EXT_CAP_ID_VNDR))) {
725 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
726 &header) == PCIBIOS_SUCCESSFUL &&
727 PCI_VNDR_HEADER_ID(header) == cap)
733 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
736 * pci_find_parent_resource - return resource region of parent bus of given
738 * @dev: PCI device structure contains resources to be searched
739 * @res: child resource record for which parent is sought
741 * For given resource region of given device, return the resource region of
742 * parent bus the given region is contained in.
744 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
745 struct resource *res)
747 const struct pci_bus *bus = dev->bus;
751 pci_bus_for_each_resource(bus, r, i) {
754 if (resource_contains(r, res)) {
757 * If the window is prefetchable but the BAR is
758 * not, the allocator made a mistake.
760 if (r->flags & IORESOURCE_PREFETCH &&
761 !(res->flags & IORESOURCE_PREFETCH))
765 * If we're below a transparent bridge, there may
766 * be both a positively-decoded aperture and a
767 * subtractively-decoded region that contain the BAR.
768 * We want the positively-decoded one, so this depends
769 * on pci_bus_for_each_resource() giving us those
777 EXPORT_SYMBOL(pci_find_parent_resource);
780 * pci_find_resource - Return matching PCI device resource
781 * @dev: PCI device to query
782 * @res: Resource to look for
784 * Goes over standard PCI resources (BARs) and checks if the given resource
785 * is partially or fully contained in any of them. In that case the
786 * matching resource is returned, %NULL otherwise.
788 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
792 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
793 struct resource *r = &dev->resource[i];
795 if (r->start && resource_contains(r, res))
801 EXPORT_SYMBOL(pci_find_resource);
804 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
805 * @dev: the PCI device to operate on
806 * @pos: config space offset of status word
807 * @mask: mask of bit(s) to care about in status word
809 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
811 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
815 /* Wait for Transaction Pending bit clean */
816 for (i = 0; i < 4; i++) {
819 msleep((1 << (i - 1)) * 100);
821 pci_read_config_word(dev, pos, &status);
822 if (!(status & mask))
829 static int pci_acs_enable;
832 * pci_request_acs - ask for ACS to be enabled if supported
834 void pci_request_acs(void)
839 static const char *disable_acs_redir_param;
842 * pci_disable_acs_redir - disable ACS redirect capabilities
843 * @dev: the PCI device
845 * For only devices specified in the disable_acs_redir parameter.
847 static void pci_disable_acs_redir(struct pci_dev *dev)
854 if (!disable_acs_redir_param)
857 p = disable_acs_redir_param;
859 ret = pci_dev_str_match(dev, p, &p);
861 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
862 disable_acs_redir_param);
865 } else if (ret == 1) {
870 if (*p != ';' && *p != ',') {
871 /* End of param or invalid format */
880 if (!pci_dev_specific_disable_acs_redir(dev))
885 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
889 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
891 /* P2P Request & Completion Redirect */
892 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
894 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
896 pci_info(dev, "disabled ACS redirect\n");
900 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
901 * @dev: the PCI device
903 static void pci_std_enable_acs(struct pci_dev *dev)
913 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
914 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
916 /* Source Validation */
917 ctrl |= (cap & PCI_ACS_SV);
919 /* P2P Request Redirect */
920 ctrl |= (cap & PCI_ACS_RR);
922 /* P2P Completion Redirect */
923 ctrl |= (cap & PCI_ACS_CR);
925 /* Upstream Forwarding */
926 ctrl |= (cap & PCI_ACS_UF);
928 /* Enable Translation Blocking for external devices and noats */
929 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
930 ctrl |= (cap & PCI_ACS_TB);
932 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
936 * pci_enable_acs - enable ACS if hardware support it
937 * @dev: the PCI device
939 static void pci_enable_acs(struct pci_dev *dev)
942 goto disable_acs_redir;
944 if (!pci_dev_specific_enable_acs(dev))
945 goto disable_acs_redir;
947 pci_std_enable_acs(dev);
951 * Note: pci_disable_acs_redir() must be called even if ACS was not
952 * enabled by the kernel because it may have been enabled by
953 * platform firmware. So if we are told to disable it, we should
954 * always disable it after setting the kernel's default
957 pci_disable_acs_redir(dev);
961 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
962 * @dev: PCI device to have its BARs restored
964 * Restore the BAR values for a given device, so as to make it
965 * accessible by its driver.
967 static void pci_restore_bars(struct pci_dev *dev)
971 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
972 pci_update_resource(dev, i);
975 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
977 if (pci_use_mid_pm())
980 return acpi_pci_power_manageable(dev);
983 static inline int platform_pci_set_power_state(struct pci_dev *dev,
986 if (pci_use_mid_pm())
987 return mid_pci_set_power_state(dev, t);
989 return acpi_pci_set_power_state(dev, t);
992 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
994 if (pci_use_mid_pm())
995 return mid_pci_get_power_state(dev);
997 return acpi_pci_get_power_state(dev);
1000 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1002 if (!pci_use_mid_pm())
1003 acpi_pci_refresh_power_state(dev);
1006 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1008 if (pci_use_mid_pm())
1009 return PCI_POWER_ERROR;
1011 return acpi_pci_choose_state(dev);
1014 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1016 if (pci_use_mid_pm())
1017 return PCI_POWER_ERROR;
1019 return acpi_pci_wakeup(dev, enable);
1022 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1024 if (pci_use_mid_pm())
1027 return acpi_pci_need_resume(dev);
1030 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1032 if (pci_use_mid_pm())
1035 return acpi_pci_bridge_d3(dev);
1039 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1041 * @dev: PCI device to handle.
1042 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1045 * -EINVAL if the requested state is invalid.
1046 * -EIO if device does not support PCI PM or its PM capabilities register has a
1047 * wrong version, or device doesn't support the requested state.
1048 * 0 if device already is in the requested state.
1049 * 0 if device's power state has been successfully changed.
1051 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1054 bool need_restore = false;
1056 /* Check if we're already there */
1057 if (dev->current_state == state)
1063 if (state < PCI_D0 || state > PCI_D3hot)
1067 * Validate transition: We can enter D0 from any state, but if
1068 * we're already in a low-power state, we can only go deeper. E.g.,
1069 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1070 * we'd have to go from D3 to D0, then to D1.
1072 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1073 && dev->current_state > state) {
1074 pci_err(dev, "invalid power transition (from %s to %s)\n",
1075 pci_power_name(dev->current_state),
1076 pci_power_name(state));
1080 /* Check if this device supports the desired state */
1081 if ((state == PCI_D1 && !dev->d1_support)
1082 || (state == PCI_D2 && !dev->d2_support))
1085 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1086 if (pmcsr == (u16) ~0) {
1087 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1088 pci_power_name(dev->current_state),
1089 pci_power_name(state));
1094 * If we're (effectively) in D3, force entire word to 0.
1095 * This doesn't affect PME_Status, disables PME_En, and
1096 * sets PowerState to 0.
1098 switch (dev->current_state) {
1102 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1107 case PCI_UNKNOWN: /* Boot-up */
1108 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1109 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1110 need_restore = true;
1111 fallthrough; /* force to D0 */
1117 /* Enter specified state */
1118 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1121 * Mandatory power management transition delays; see PCI PM 1.1
1124 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1125 pci_dev_d3_sleep(dev);
1126 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1127 udelay(PCI_PM_D2_DELAY);
1129 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1130 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1131 if (dev->current_state != state)
1132 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1133 pci_power_name(dev->current_state),
1134 pci_power_name(state));
1137 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1138 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1139 * from D3hot to D0 _may_ perform an internal reset, thereby
1140 * going to "D0 Uninitialized" rather than "D0 Initialized".
1141 * For example, at least some versions of the 3c905B and the
1142 * 3c556B exhibit this behaviour.
1144 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1145 * devices in a D3hot state at boot. Consequently, we need to
1146 * restore at least the BARs so that the device will be
1147 * accessible to its driver.
1150 pci_restore_bars(dev);
1153 pcie_aspm_pm_state_change(dev->bus->self);
1159 * pci_update_current_state - Read power state of given device and cache it
1160 * @dev: PCI device to handle.
1161 * @state: State to cache in case the device doesn't have the PM capability
1163 * The power state is read from the PMCSR register, which however is
1164 * inaccessible in D3cold. The platform firmware is therefore queried first
1165 * to detect accessibility of the register. In case the platform firmware
1166 * reports an incorrect state or the device isn't power manageable by the
1167 * platform at all, we try to detect D3cold by testing accessibility of the
1168 * vendor ID in config space.
1170 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1172 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1173 !pci_device_is_present(dev)) {
1174 dev->current_state = PCI_D3cold;
1175 } else if (dev->pm_cap) {
1178 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1179 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1181 dev->current_state = state;
1186 * pci_refresh_power_state - Refresh the given device's power state data
1187 * @dev: Target PCI device.
1189 * Ask the platform to refresh the devices power state information and invoke
1190 * pci_update_current_state() to update its current PCI power state.
1192 void pci_refresh_power_state(struct pci_dev *dev)
1194 platform_pci_refresh_power_state(dev);
1195 pci_update_current_state(dev, dev->current_state);
1199 * pci_platform_power_transition - Use platform to change device power state
1200 * @dev: PCI device to handle.
1201 * @state: State to put the device into.
1203 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1207 error = platform_pci_set_power_state(dev, state);
1209 pci_update_current_state(dev, state);
1210 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1211 dev->current_state = PCI_D0;
1215 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1217 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1219 pm_request_resume(&pci_dev->dev);
1224 * pci_resume_bus - Walk given bus and runtime resume devices on it
1225 * @bus: Top bus of the subtree to walk.
1227 void pci_resume_bus(struct pci_bus *bus)
1230 pci_walk_bus(bus, pci_resume_one, NULL);
1233 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 data to complete the read (except when
1243 * CRS SV is enabled and the read was for the Vendor ID; in that
1244 * case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1250 pci_read_config_dword(dev, PCI_COMMAND, &id);
1252 if (delay > timeout) {
1253 pci_warn(dev, "not ready %dms after %s; giving up\n",
1254 delay - 1, reset_type);
1259 pci_info(dev, "not ready %dms after %s; waiting\n",
1260 delay - 1, reset_type);
1264 pci_read_config_dword(dev, PCI_COMMAND, &id);
1268 pci_info(dev, "ready %dms after %s\n", delay - 1,
1275 * pci_power_up - Put the given device into D0
1276 * @dev: PCI device to power up
1278 int pci_power_up(struct pci_dev *dev)
1280 pci_platform_power_transition(dev, PCI_D0);
1283 * Mandatory power management transition delays are handled in
1284 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1285 * corresponding bridge.
1287 if (dev->runtime_d3cold) {
1289 * When powering on a bridge from D3cold, the whole hierarchy
1290 * may be powered on into D0uninitialized state, resume them to
1291 * give them a chance to suspend again
1293 pci_resume_bus(dev->subordinate);
1296 return pci_raw_set_power_state(dev, PCI_D0);
1300 * __pci_dev_set_current_state - Set current state of a PCI device
1301 * @dev: Device to handle
1302 * @data: pointer to state to be set
1304 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1306 pci_power_t state = *(pci_power_t *)data;
1308 dev->current_state = state;
1313 * pci_bus_set_current_state - Walk given bus and set current state of devices
1314 * @bus: Top bus of the subtree to walk.
1315 * @state: state to be set
1317 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1320 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1324 * pci_set_power_state - Set the power state of a PCI device
1325 * @dev: PCI device to handle.
1326 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1328 * Transition a device to a new power state, using the platform firmware and/or
1329 * the device's PCI PM registers.
1332 * -EINVAL if the requested state is invalid.
1333 * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 * wrong version, or device doesn't support the requested state.
1335 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1336 * 0 if device already is in the requested state.
1337 * 0 if the transition is to D3 but D3 is not supported.
1338 * 0 if device's power state has been successfully changed.
1340 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1344 /* Bound the state we're entering */
1345 if (state > PCI_D3cold)
1347 else if (state < PCI_D0)
1349 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1352 * If the device or the parent bridge do not support PCI
1353 * PM, ignore the request if we're doing anything other
1354 * than putting it into D0 (which would only happen on
1359 /* Check if we're already there */
1360 if (dev->current_state == state)
1363 if (state == PCI_D0)
1364 return pci_power_up(dev);
1367 * This device is quirked not to be put into D3, so don't put it in
1370 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1374 * To put device in D3cold, we put device into D3hot in native
1375 * way, then put device into D3cold with platform ops
1377 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1380 if (pci_platform_power_transition(dev, state))
1383 /* Powering off a bridge may power off the whole hierarchy */
1384 if (state == PCI_D3cold)
1385 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1389 EXPORT_SYMBOL(pci_set_power_state);
1391 #define PCI_EXP_SAVE_REGS 7
1393 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1394 u16 cap, bool extended)
1396 struct pci_cap_saved_state *tmp;
1398 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1399 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1405 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1407 return _pci_find_saved_cap(dev, cap, false);
1410 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1412 return _pci_find_saved_cap(dev, cap, true);
1415 static int pci_save_pcie_state(struct pci_dev *dev)
1418 struct pci_cap_saved_state *save_state;
1421 if (!pci_is_pcie(dev))
1424 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1426 pci_err(dev, "buffer not found in %s\n", __func__);
1430 cap = (u16 *)&save_state->cap.data[0];
1431 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1432 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1433 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1434 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1435 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1436 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1437 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1442 static void pci_restore_pcie_state(struct pci_dev *dev)
1445 struct pci_cap_saved_state *save_state;
1448 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1452 cap = (u16 *)&save_state->cap.data[0];
1453 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1454 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1455 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1456 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1457 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1458 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1459 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1462 static int pci_save_pcix_state(struct pci_dev *dev)
1465 struct pci_cap_saved_state *save_state;
1467 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1471 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1473 pci_err(dev, "buffer not found in %s\n", __func__);
1477 pci_read_config_word(dev, pos + PCI_X_CMD,
1478 (u16 *)save_state->cap.data);
1483 static void pci_restore_pcix_state(struct pci_dev *dev)
1486 struct pci_cap_saved_state *save_state;
1489 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1490 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1491 if (!save_state || !pos)
1493 cap = (u16 *)&save_state->cap.data[0];
1495 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1498 static void pci_save_ltr_state(struct pci_dev *dev)
1501 struct pci_cap_saved_state *save_state;
1504 if (!pci_is_pcie(dev))
1507 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1511 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1513 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1517 cap = (u16 *)&save_state->cap.data[0];
1518 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1519 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1522 static void pci_restore_ltr_state(struct pci_dev *dev)
1524 struct pci_cap_saved_state *save_state;
1528 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1529 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1530 if (!save_state || !ltr)
1533 cap = (u16 *)&save_state->cap.data[0];
1534 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1535 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1539 * pci_save_state - save the PCI configuration space of a device before
1541 * @dev: PCI device that we're dealing with
1543 int pci_save_state(struct pci_dev *dev)
1546 /* XXX: 100% dword access ok here? */
1547 for (i = 0; i < 16; i++) {
1548 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1549 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1550 i * 4, dev->saved_config_space[i]);
1552 dev->state_saved = true;
1554 i = pci_save_pcie_state(dev);
1558 i = pci_save_pcix_state(dev);
1562 pci_save_ltr_state(dev);
1563 pci_save_dpc_state(dev);
1564 pci_save_aer_state(dev);
1565 pci_save_ptm_state(dev);
1566 return pci_save_vc_state(dev);
1568 EXPORT_SYMBOL(pci_save_state);
1570 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1571 u32 saved_val, int retry, bool force)
1575 pci_read_config_dword(pdev, offset, &val);
1576 if (!force && val == saved_val)
1580 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1581 offset, val, saved_val);
1582 pci_write_config_dword(pdev, offset, saved_val);
1586 pci_read_config_dword(pdev, offset, &val);
1587 if (val == saved_val)
1594 static void pci_restore_config_space_range(struct pci_dev *pdev,
1595 int start, int end, int retry,
1600 for (index = end; index >= start; index--)
1601 pci_restore_config_dword(pdev, 4 * index,
1602 pdev->saved_config_space[index],
1606 static void pci_restore_config_space(struct pci_dev *pdev)
1608 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1609 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1610 /* Restore BARs before the command register. */
1611 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1612 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1613 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1614 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1617 * Force rewriting of prefetch registers to avoid S3 resume
1618 * issues on Intel PCI bridges that occur when these
1619 * registers are not explicitly written.
1621 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1622 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1624 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1628 static void pci_restore_rebar_state(struct pci_dev *pdev)
1630 unsigned int pos, nbars, i;
1633 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1637 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1638 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1639 PCI_REBAR_CTRL_NBAR_SHIFT;
1641 for (i = 0; i < nbars; i++, pos += 8) {
1642 struct resource *res;
1645 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1646 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1647 res = pdev->resource + bar_idx;
1648 size = pci_rebar_bytes_to_size(resource_size(res));
1649 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1650 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1651 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1656 * pci_restore_state - Restore the saved state of a PCI device
1657 * @dev: PCI device that we're dealing with
1659 void pci_restore_state(struct pci_dev *dev)
1661 if (!dev->state_saved)
1665 * Restore max latencies (in the LTR capability) before enabling
1666 * LTR itself (in the PCIe capability).
1668 pci_restore_ltr_state(dev);
1670 pci_restore_pcie_state(dev);
1671 pci_restore_pasid_state(dev);
1672 pci_restore_pri_state(dev);
1673 pci_restore_ats_state(dev);
1674 pci_restore_vc_state(dev);
1675 pci_restore_rebar_state(dev);
1676 pci_restore_dpc_state(dev);
1677 pci_restore_ptm_state(dev);
1679 pci_aer_clear_status(dev);
1680 pci_restore_aer_state(dev);
1682 pci_restore_config_space(dev);
1684 pci_restore_pcix_state(dev);
1685 pci_restore_msi_state(dev);
1687 /* Restore ACS and IOV configuration state */
1688 pci_enable_acs(dev);
1689 pci_restore_iov_state(dev);
1691 dev->state_saved = false;
1693 EXPORT_SYMBOL(pci_restore_state);
1695 struct pci_saved_state {
1696 u32 config_space[16];
1697 struct pci_cap_saved_data cap[];
1701 * pci_store_saved_state - Allocate and return an opaque struct containing
1702 * the device saved state.
1703 * @dev: PCI device that we're dealing with
1705 * Return NULL if no state or error.
1707 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1709 struct pci_saved_state *state;
1710 struct pci_cap_saved_state *tmp;
1711 struct pci_cap_saved_data *cap;
1714 if (!dev->state_saved)
1717 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1719 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1720 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1722 state = kzalloc(size, GFP_KERNEL);
1726 memcpy(state->config_space, dev->saved_config_space,
1727 sizeof(state->config_space));
1730 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1731 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1732 memcpy(cap, &tmp->cap, len);
1733 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1735 /* Empty cap_save terminates list */
1739 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1742 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1743 * @dev: PCI device that we're dealing with
1744 * @state: Saved state returned from pci_store_saved_state()
1746 int pci_load_saved_state(struct pci_dev *dev,
1747 struct pci_saved_state *state)
1749 struct pci_cap_saved_data *cap;
1751 dev->state_saved = false;
1756 memcpy(dev->saved_config_space, state->config_space,
1757 sizeof(state->config_space));
1761 struct pci_cap_saved_state *tmp;
1763 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1764 if (!tmp || tmp->cap.size != cap->size)
1767 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1768 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1769 sizeof(struct pci_cap_saved_data) + cap->size);
1772 dev->state_saved = true;
1775 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1778 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1779 * and free the memory allocated for it.
1780 * @dev: PCI device that we're dealing with
1781 * @state: Pointer to saved state returned from pci_store_saved_state()
1783 int pci_load_and_free_saved_state(struct pci_dev *dev,
1784 struct pci_saved_state **state)
1786 int ret = pci_load_saved_state(dev, *state);
1791 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1793 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1795 return pci_enable_resources(dev, bars);
1798 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1801 struct pci_dev *bridge;
1805 err = pci_set_power_state(dev, PCI_D0);
1806 if (err < 0 && err != -EIO)
1809 bridge = pci_upstream_bridge(dev);
1811 pcie_aspm_powersave_config_link(bridge);
1813 err = pcibios_enable_device(dev, bars);
1816 pci_fixup_device(pci_fixup_enable, dev);
1818 if (dev->msi_enabled || dev->msix_enabled)
1821 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1823 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1824 if (cmd & PCI_COMMAND_INTX_DISABLE)
1825 pci_write_config_word(dev, PCI_COMMAND,
1826 cmd & ~PCI_COMMAND_INTX_DISABLE);
1833 * pci_reenable_device - Resume abandoned device
1834 * @dev: PCI device to be resumed
1836 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1837 * to be called by normal code, write proper resume handler and use it instead.
1839 int pci_reenable_device(struct pci_dev *dev)
1841 if (pci_is_enabled(dev))
1842 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1845 EXPORT_SYMBOL(pci_reenable_device);
1847 static void pci_enable_bridge(struct pci_dev *dev)
1849 struct pci_dev *bridge;
1852 bridge = pci_upstream_bridge(dev);
1854 pci_enable_bridge(bridge);
1856 if (pci_is_enabled(dev)) {
1857 if (!dev->is_busmaster)
1858 pci_set_master(dev);
1862 retval = pci_enable_device(dev);
1864 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1866 pci_set_master(dev);
1869 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1871 struct pci_dev *bridge;
1876 * Power state could be unknown at this point, either due to a fresh
1877 * boot or a device removal call. So get the current power state
1878 * so that things like MSI message writing will behave as expected
1879 * (e.g. if the device really is in D0 at enable time).
1881 pci_update_current_state(dev, dev->current_state);
1883 if (atomic_inc_return(&dev->enable_cnt) > 1)
1884 return 0; /* already enabled */
1886 bridge = pci_upstream_bridge(dev);
1888 pci_enable_bridge(bridge);
1890 /* only skip sriov related */
1891 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1892 if (dev->resource[i].flags & flags)
1894 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1895 if (dev->resource[i].flags & flags)
1898 err = do_pci_enable_device(dev, bars);
1900 atomic_dec(&dev->enable_cnt);
1905 * pci_enable_device_io - Initialize a device for use with IO space
1906 * @dev: PCI device to be initialized
1908 * Initialize device before it's used by a driver. Ask low-level code
1909 * to enable I/O resources. Wake up the device if it was suspended.
1910 * Beware, this function can fail.
1912 int pci_enable_device_io(struct pci_dev *dev)
1914 return pci_enable_device_flags(dev, IORESOURCE_IO);
1916 EXPORT_SYMBOL(pci_enable_device_io);
1919 * pci_enable_device_mem - Initialize a device for use with Memory space
1920 * @dev: PCI device to be initialized
1922 * Initialize device before it's used by a driver. Ask low-level code
1923 * to enable Memory resources. Wake up the device if it was suspended.
1924 * Beware, this function can fail.
1926 int pci_enable_device_mem(struct pci_dev *dev)
1928 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1930 EXPORT_SYMBOL(pci_enable_device_mem);
1933 * pci_enable_device - Initialize device before it's used by a driver.
1934 * @dev: PCI device to be initialized
1936 * Initialize device before it's used by a driver. Ask low-level code
1937 * to enable I/O and memory. Wake up the device if it was suspended.
1938 * Beware, this function can fail.
1940 * Note we don't actually enable the device many times if we call
1941 * this function repeatedly (we just increment the count).
1943 int pci_enable_device(struct pci_dev *dev)
1945 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1947 EXPORT_SYMBOL(pci_enable_device);
1950 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1951 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1952 * there's no need to track it separately. pci_devres is initialized
1953 * when a device is enabled using managed PCI device enable interface.
1956 unsigned int enabled:1;
1957 unsigned int pinned:1;
1958 unsigned int orig_intx:1;
1959 unsigned int restore_intx:1;
1964 static void pcim_release(struct device *gendev, void *res)
1966 struct pci_dev *dev = to_pci_dev(gendev);
1967 struct pci_devres *this = res;
1970 if (dev->msi_enabled)
1971 pci_disable_msi(dev);
1972 if (dev->msix_enabled)
1973 pci_disable_msix(dev);
1975 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1976 if (this->region_mask & (1 << i))
1977 pci_release_region(dev, i);
1982 if (this->restore_intx)
1983 pci_intx(dev, this->orig_intx);
1985 if (this->enabled && !this->pinned)
1986 pci_disable_device(dev);
1989 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1991 struct pci_devres *dr, *new_dr;
1993 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1997 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2000 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2003 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2005 if (pci_is_managed(pdev))
2006 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2011 * pcim_enable_device - Managed pci_enable_device()
2012 * @pdev: PCI device to be initialized
2014 * Managed pci_enable_device().
2016 int pcim_enable_device(struct pci_dev *pdev)
2018 struct pci_devres *dr;
2021 dr = get_pci_dr(pdev);
2027 rc = pci_enable_device(pdev);
2029 pdev->is_managed = 1;
2034 EXPORT_SYMBOL(pcim_enable_device);
2037 * pcim_pin_device - Pin managed PCI device
2038 * @pdev: PCI device to pin
2040 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2041 * driver detach. @pdev must have been enabled with
2042 * pcim_enable_device().
2044 void pcim_pin_device(struct pci_dev *pdev)
2046 struct pci_devres *dr;
2048 dr = find_pci_dr(pdev);
2049 WARN_ON(!dr || !dr->enabled);
2053 EXPORT_SYMBOL(pcim_pin_device);
2056 * pcibios_add_device - provide arch specific hooks when adding device dev
2057 * @dev: the PCI device being added
2059 * Permits the platform to provide architecture specific functionality when
2060 * devices are added. This is the default implementation. Architecture
2061 * implementations can override this.
2063 int __weak pcibios_add_device(struct pci_dev *dev)
2069 * pcibios_release_device - provide arch specific hooks when releasing
2071 * @dev: the PCI device being released
2073 * Permits the platform to provide architecture specific functionality when
2074 * devices are released. This is the default implementation. Architecture
2075 * implementations can override this.
2077 void __weak pcibios_release_device(struct pci_dev *dev) {}
2080 * pcibios_disable_device - disable arch specific PCI resources for device dev
2081 * @dev: the PCI device to disable
2083 * Disables architecture specific PCI resources for the device. This
2084 * is the default implementation. Architecture implementations can
2087 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2090 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2091 * @irq: ISA IRQ to penalize
2092 * @active: IRQ active or not
2094 * Permits the platform to provide architecture-specific functionality when
2095 * penalizing ISA IRQs. This is the default implementation. Architecture
2096 * implementations can override this.
2098 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2100 static void do_pci_disable_device(struct pci_dev *dev)
2104 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2105 if (pci_command & PCI_COMMAND_MASTER) {
2106 pci_command &= ~PCI_COMMAND_MASTER;
2107 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2110 pcibios_disable_device(dev);
2114 * pci_disable_enabled_device - Disable device without updating enable_cnt
2115 * @dev: PCI device to disable
2117 * NOTE: This function is a backend of PCI power management routines and is
2118 * not supposed to be called drivers.
2120 void pci_disable_enabled_device(struct pci_dev *dev)
2122 if (pci_is_enabled(dev))
2123 do_pci_disable_device(dev);
2127 * pci_disable_device - Disable PCI device after use
2128 * @dev: PCI device to be disabled
2130 * Signal to the system that the PCI device is not in use by the system
2131 * anymore. This only involves disabling PCI bus-mastering, if active.
2133 * Note we don't actually disable the device until all callers of
2134 * pci_enable_device() have called pci_disable_device().
2136 void pci_disable_device(struct pci_dev *dev)
2138 struct pci_devres *dr;
2140 dr = find_pci_dr(dev);
2144 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2145 "disabling already-disabled device");
2147 if (atomic_dec_return(&dev->enable_cnt) != 0)
2150 do_pci_disable_device(dev);
2152 dev->is_busmaster = 0;
2154 EXPORT_SYMBOL(pci_disable_device);
2157 * pcibios_set_pcie_reset_state - set reset state for device dev
2158 * @dev: the PCIe device reset
2159 * @state: Reset state to enter into
2161 * Set the PCIe reset state for the device. This is the default
2162 * implementation. Architecture implementations can override this.
2164 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2165 enum pcie_reset_state state)
2171 * pci_set_pcie_reset_state - set reset state for device dev
2172 * @dev: the PCIe device reset
2173 * @state: Reset state to enter into
2175 * Sets the PCI reset state for the device.
2177 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2179 return pcibios_set_pcie_reset_state(dev, state);
2181 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2183 void pcie_clear_device_status(struct pci_dev *dev)
2187 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2188 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2192 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2193 * @dev: PCIe root port or event collector.
2195 void pcie_clear_root_pme_status(struct pci_dev *dev)
2197 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2201 * pci_check_pme_status - Check if given device has generated PME.
2202 * @dev: Device to check.
2204 * Check the PME status of the device and if set, clear it and clear PME enable
2205 * (if set). Return 'true' if PME status and PME enable were both set or
2206 * 'false' otherwise.
2208 bool pci_check_pme_status(struct pci_dev *dev)
2217 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2218 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2219 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2222 /* Clear PME status. */
2223 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2224 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2225 /* Disable PME to avoid interrupt flood. */
2226 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2230 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2236 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2237 * @dev: Device to handle.
2238 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2240 * Check if @dev has generated PME and queue a resume request for it in that
2243 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2245 if (pme_poll_reset && dev->pme_poll)
2246 dev->pme_poll = false;
2248 if (pci_check_pme_status(dev)) {
2249 pci_wakeup_event(dev);
2250 pm_request_resume(&dev->dev);
2256 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2257 * @bus: Top bus of the subtree to walk.
2259 void pci_pme_wakeup_bus(struct pci_bus *bus)
2262 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2267 * pci_pme_capable - check the capability of PCI device to generate PME#
2268 * @dev: PCI device to handle.
2269 * @state: PCI state from which device will issue PME#.
2271 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2276 return !!(dev->pme_support & (1 << state));
2278 EXPORT_SYMBOL(pci_pme_capable);
2280 static void pci_pme_list_scan(struct work_struct *work)
2282 struct pci_pme_device *pme_dev, *n;
2284 mutex_lock(&pci_pme_list_mutex);
2285 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2286 if (pme_dev->dev->pme_poll) {
2287 struct pci_dev *bridge;
2289 bridge = pme_dev->dev->bus->self;
2291 * If bridge is in low power state, the
2292 * configuration space of subordinate devices
2293 * may be not accessible
2295 if (bridge && bridge->current_state != PCI_D0)
2298 * If the device is in D3cold it should not be
2301 if (pme_dev->dev->current_state == PCI_D3cold)
2304 pci_pme_wakeup(pme_dev->dev, NULL);
2306 list_del(&pme_dev->list);
2310 if (!list_empty(&pci_pme_list))
2311 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2312 msecs_to_jiffies(PME_TIMEOUT));
2313 mutex_unlock(&pci_pme_list_mutex);
2316 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2320 if (!dev->pme_support)
2323 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2324 /* Clear PME_Status by writing 1 to it and enable PME# */
2325 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2327 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2329 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2333 * pci_pme_restore - Restore PME configuration after config space restore.
2334 * @dev: PCI device to update.
2336 void pci_pme_restore(struct pci_dev *dev)
2340 if (!dev->pme_support)
2343 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2344 if (dev->wakeup_prepared) {
2345 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2346 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2348 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2349 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2351 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2355 * pci_pme_active - enable or disable PCI device's PME# function
2356 * @dev: PCI device to handle.
2357 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2359 * The caller must verify that the device is capable of generating PME# before
2360 * calling this function with @enable equal to 'true'.
2362 void pci_pme_active(struct pci_dev *dev, bool enable)
2364 __pci_pme_active(dev, enable);
2367 * PCI (as opposed to PCIe) PME requires that the device have
2368 * its PME# line hooked up correctly. Not all hardware vendors
2369 * do this, so the PME never gets delivered and the device
2370 * remains asleep. The easiest way around this is to
2371 * periodically walk the list of suspended devices and check
2372 * whether any have their PME flag set. The assumption is that
2373 * we'll wake up often enough anyway that this won't be a huge
2374 * hit, and the power savings from the devices will still be a
2377 * Although PCIe uses in-band PME message instead of PME# line
2378 * to report PME, PME does not work for some PCIe devices in
2379 * reality. For example, there are devices that set their PME
2380 * status bits, but don't really bother to send a PME message;
2381 * there are PCI Express Root Ports that don't bother to
2382 * trigger interrupts when they receive PME messages from the
2383 * devices below. So PME poll is used for PCIe devices too.
2386 if (dev->pme_poll) {
2387 struct pci_pme_device *pme_dev;
2389 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2392 pci_warn(dev, "can't enable PME#\n");
2396 mutex_lock(&pci_pme_list_mutex);
2397 list_add(&pme_dev->list, &pci_pme_list);
2398 if (list_is_singular(&pci_pme_list))
2399 queue_delayed_work(system_freezable_wq,
2401 msecs_to_jiffies(PME_TIMEOUT));
2402 mutex_unlock(&pci_pme_list_mutex);
2404 mutex_lock(&pci_pme_list_mutex);
2405 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2406 if (pme_dev->dev == dev) {
2407 list_del(&pme_dev->list);
2412 mutex_unlock(&pci_pme_list_mutex);
2416 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2418 EXPORT_SYMBOL(pci_pme_active);
2421 * __pci_enable_wake - enable PCI device as wakeup event source
2422 * @dev: PCI device affected
2423 * @state: PCI state from which device will issue wakeup events
2424 * @enable: True to enable event generation; false to disable
2426 * This enables the device as a wakeup event source, or disables it.
2427 * When such events involves platform-specific hooks, those hooks are
2428 * called automatically by this routine.
2430 * Devices with legacy power management (no standard PCI PM capabilities)
2431 * always require such platform hooks.
2434 * 0 is returned on success
2435 * -EINVAL is returned if device is not supposed to wake up the system
2436 * Error code depending on the platform is returned if both the platform and
2437 * the native mechanism fail to enable the generation of wake-up events
2439 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2444 * Bridges that are not power-manageable directly only signal
2445 * wakeup on behalf of subordinate devices which is set up
2446 * elsewhere, so skip them. However, bridges that are
2447 * power-manageable may signal wakeup for themselves (for example,
2448 * on a hotplug event) and they need to be covered here.
2450 if (!pci_power_manageable(dev))
2453 /* Don't do the same thing twice in a row for one device. */
2454 if (!!enable == !!dev->wakeup_prepared)
2458 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2459 * Anderson we should be doing PME# wake enable followed by ACPI wake
2460 * enable. To disable wake-up we call the platform first, for symmetry.
2467 * Enable PME signaling if the device can signal PME from
2468 * D3cold regardless of whether or not it can signal PME from
2469 * the current target state, because that will allow it to
2470 * signal PME when the hierarchy above it goes into D3cold and
2471 * the device itself ends up in D3cold as a result of that.
2473 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2474 pci_pme_active(dev, true);
2477 error = platform_pci_set_wakeup(dev, true);
2481 dev->wakeup_prepared = true;
2483 platform_pci_set_wakeup(dev, false);
2484 pci_pme_active(dev, false);
2485 dev->wakeup_prepared = false;
2492 * pci_enable_wake - change wakeup settings for a PCI device
2493 * @pci_dev: Target device
2494 * @state: PCI state from which device will issue wakeup events
2495 * @enable: Whether or not to enable event generation
2497 * If @enable is set, check device_may_wakeup() for the device before calling
2498 * __pci_enable_wake() for it.
2500 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2502 if (enable && !device_may_wakeup(&pci_dev->dev))
2505 return __pci_enable_wake(pci_dev, state, enable);
2507 EXPORT_SYMBOL(pci_enable_wake);
2510 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2511 * @dev: PCI device to prepare
2512 * @enable: True to enable wake-up event generation; false to disable
2514 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2515 * and this function allows them to set that up cleanly - pci_enable_wake()
2516 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2517 * ordering constraints.
2519 * This function only returns error code if the device is not allowed to wake
2520 * up the system from sleep or it is not capable of generating PME# from both
2521 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2523 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2525 return pci_pme_capable(dev, PCI_D3cold) ?
2526 pci_enable_wake(dev, PCI_D3cold, enable) :
2527 pci_enable_wake(dev, PCI_D3hot, enable);
2529 EXPORT_SYMBOL(pci_wake_from_d3);
2532 * pci_target_state - find an appropriate low power state for a given PCI dev
2534 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2536 * Use underlying platform code to find a supported low power state for @dev.
2537 * If the platform can't manage @dev, return the deepest state from which it
2538 * can generate wake events, based on any available PME info.
2540 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2542 if (platform_pci_power_manageable(dev)) {
2544 * Call the platform to find the target state for the device.
2546 pci_power_t state = platform_pci_choose_state(dev);
2549 case PCI_POWER_ERROR:
2555 if (pci_no_d1d2(dev))
2563 * If the device is in D3cold even though it's not power-manageable by
2564 * the platform, it may have been powered down by non-standard means.
2565 * Best to let it slumber.
2567 if (dev->current_state == PCI_D3cold)
2569 else if (!dev->pm_cap)
2572 if (wakeup && dev->pme_support) {
2573 pci_power_t state = PCI_D3hot;
2576 * Find the deepest state from which the device can generate
2579 while (state && !(dev->pme_support & (1 << state)))
2584 else if (dev->pme_support & 1)
2592 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2593 * into a sleep state
2594 * @dev: Device to handle.
2596 * Choose the power state appropriate for the device depending on whether
2597 * it can wake up the system and/or is power manageable by the platform
2598 * (PCI_D3hot is the default) and put the device into that state.
2600 int pci_prepare_to_sleep(struct pci_dev *dev)
2602 bool wakeup = device_may_wakeup(&dev->dev);
2603 pci_power_t target_state = pci_target_state(dev, wakeup);
2606 if (target_state == PCI_POWER_ERROR)
2610 * There are systems (for example, Intel mobile chips since Coffee
2611 * Lake) where the power drawn while suspended can be significantly
2612 * reduced by disabling PTM on PCIe root ports as this allows the
2613 * port to enter a lower-power PM state and the SoC to reach a
2614 * lower-power idle state as a whole.
2616 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2617 pci_disable_ptm(dev);
2619 pci_enable_wake(dev, target_state, wakeup);
2621 error = pci_set_power_state(dev, target_state);
2624 pci_enable_wake(dev, target_state, false);
2625 pci_restore_ptm_state(dev);
2630 EXPORT_SYMBOL(pci_prepare_to_sleep);
2633 * pci_back_from_sleep - turn PCI device on during system-wide transition
2634 * into working state
2635 * @dev: Device to handle.
2637 * Disable device's system wake-up capability and put it into D0.
2639 int pci_back_from_sleep(struct pci_dev *dev)
2641 int ret = pci_set_power_state(dev, PCI_D0);
2646 pci_enable_wake(dev, PCI_D0, false);
2649 EXPORT_SYMBOL(pci_back_from_sleep);
2652 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2653 * @dev: PCI device being suspended.
2655 * Prepare @dev to generate wake-up events at run time and put it into a low
2658 int pci_finish_runtime_suspend(struct pci_dev *dev)
2660 pci_power_t target_state;
2663 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2664 if (target_state == PCI_POWER_ERROR)
2667 dev->runtime_d3cold = target_state == PCI_D3cold;
2670 * There are systems (for example, Intel mobile chips since Coffee
2671 * Lake) where the power drawn while suspended can be significantly
2672 * reduced by disabling PTM on PCIe root ports as this allows the
2673 * port to enter a lower-power PM state and the SoC to reach a
2674 * lower-power idle state as a whole.
2676 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2677 pci_disable_ptm(dev);
2679 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2681 error = pci_set_power_state(dev, target_state);
2684 pci_enable_wake(dev, target_state, false);
2685 pci_restore_ptm_state(dev);
2686 dev->runtime_d3cold = false;
2693 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2694 * @dev: Device to check.
2696 * Return true if the device itself is capable of generating wake-up events
2697 * (through the platform or using the native PCIe PME) or if the device supports
2698 * PME and one of its upstream bridges can generate wake-up events.
2700 bool pci_dev_run_wake(struct pci_dev *dev)
2702 struct pci_bus *bus = dev->bus;
2704 if (!dev->pme_support)
2707 /* PME-capable in principle, but not from the target power state */
2708 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2711 if (device_can_wakeup(&dev->dev))
2714 while (bus->parent) {
2715 struct pci_dev *bridge = bus->self;
2717 if (device_can_wakeup(&bridge->dev))
2723 /* We have reached the root bus. */
2725 return device_can_wakeup(bus->bridge);
2729 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2732 * pci_dev_need_resume - Check if it is necessary to resume the device.
2733 * @pci_dev: Device to check.
2735 * Return 'true' if the device is not runtime-suspended or it has to be
2736 * reconfigured due to wakeup settings difference between system and runtime
2737 * suspend, or the current power state of it is not suitable for the upcoming
2738 * (system-wide) transition.
2740 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2742 struct device *dev = &pci_dev->dev;
2743 pci_power_t target_state;
2745 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2748 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2751 * If the earlier platform check has not triggered, D3cold is just power
2752 * removal on top of D3hot, so no need to resume the device in that
2755 return target_state != pci_dev->current_state &&
2756 target_state != PCI_D3cold &&
2757 pci_dev->current_state != PCI_D3hot;
2761 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2762 * @pci_dev: Device to check.
2764 * If the device is suspended and it is not configured for system wakeup,
2765 * disable PME for it to prevent it from waking up the system unnecessarily.
2767 * Note that if the device's power state is D3cold and the platform check in
2768 * pci_dev_need_resume() has not triggered, the device's configuration need not
2771 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2773 struct device *dev = &pci_dev->dev;
2775 spin_lock_irq(&dev->power.lock);
2777 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2778 pci_dev->current_state < PCI_D3cold)
2779 __pci_pme_active(pci_dev, false);
2781 spin_unlock_irq(&dev->power.lock);
2785 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2786 * @pci_dev: Device to handle.
2788 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2789 * it might have been disabled during the prepare phase of system suspend if
2790 * the device was not configured for system wakeup.
2792 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2794 struct device *dev = &pci_dev->dev;
2796 if (!pci_dev_run_wake(pci_dev))
2799 spin_lock_irq(&dev->power.lock);
2801 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2802 __pci_pme_active(pci_dev, true);
2804 spin_unlock_irq(&dev->power.lock);
2808 * pci_choose_state - Choose the power state of a PCI device.
2809 * @dev: Target PCI device.
2810 * @state: Target state for the whole system.
2812 * Returns PCI power state suitable for @dev and @state.
2814 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2816 if (state.event == PM_EVENT_ON)
2819 return pci_target_state(dev, false);
2821 EXPORT_SYMBOL(pci_choose_state);
2823 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2825 struct device *dev = &pdev->dev;
2826 struct device *parent = dev->parent;
2829 pm_runtime_get_sync(parent);
2830 pm_runtime_get_noresume(dev);
2832 * pdev->current_state is set to PCI_D3cold during suspending,
2833 * so wait until suspending completes
2835 pm_runtime_barrier(dev);
2837 * Only need to resume devices in D3cold, because config
2838 * registers are still accessible for devices suspended but
2841 if (pdev->current_state == PCI_D3cold)
2842 pm_runtime_resume(dev);
2845 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2847 struct device *dev = &pdev->dev;
2848 struct device *parent = dev->parent;
2850 pm_runtime_put(dev);
2852 pm_runtime_put_sync(parent);
2855 static const struct dmi_system_id bridge_d3_blacklist[] = {
2859 * Gigabyte X299 root port is not marked as hotplug capable
2860 * which allows Linux to power manage it. However, this
2861 * confuses the BIOS SMI handler so don't power manage root
2862 * ports on that system.
2864 .ident = "X299 DESIGNARE EX-CF",
2866 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2867 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2875 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2876 * @bridge: Bridge to check
2878 * This function checks if it is possible to move the bridge to D3.
2879 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2881 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2883 if (!pci_is_pcie(bridge))
2886 switch (pci_pcie_type(bridge)) {
2887 case PCI_EXP_TYPE_ROOT_PORT:
2888 case PCI_EXP_TYPE_UPSTREAM:
2889 case PCI_EXP_TYPE_DOWNSTREAM:
2890 if (pci_bridge_d3_disable)
2894 * Hotplug ports handled by firmware in System Management Mode
2895 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2897 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2900 if (pci_bridge_d3_force)
2903 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2904 if (bridge->is_thunderbolt)
2907 /* Platform might know better if the bridge supports D3 */
2908 if (platform_pci_bridge_d3(bridge))
2912 * Hotplug ports handled natively by the OS were not validated
2913 * by vendors for runtime D3 at least until 2018 because there
2914 * was no OS support.
2916 if (bridge->is_hotplug_bridge)
2919 if (dmi_check_system(bridge_d3_blacklist))
2923 * It should be safe to put PCIe ports from 2015 or newer
2926 if (dmi_get_bios_year() >= 2015)
2934 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2936 bool *d3cold_ok = data;
2938 if (/* The device needs to be allowed to go D3cold ... */
2939 dev->no_d3cold || !dev->d3cold_allowed ||
2941 /* ... and if it is wakeup capable to do so from D3cold. */
2942 (device_may_wakeup(&dev->dev) &&
2943 !pci_pme_capable(dev, PCI_D3cold)) ||
2945 /* If it is a bridge it must be allowed to go to D3. */
2946 !pci_power_manageable(dev))
2954 * pci_bridge_d3_update - Update bridge D3 capabilities
2955 * @dev: PCI device which is changed
2957 * Update upstream bridge PM capabilities accordingly depending on if the
2958 * device PM configuration was changed or the device is being removed. The
2959 * change is also propagated upstream.
2961 void pci_bridge_d3_update(struct pci_dev *dev)
2963 bool remove = !device_is_registered(&dev->dev);
2964 struct pci_dev *bridge;
2965 bool d3cold_ok = true;
2967 bridge = pci_upstream_bridge(dev);
2968 if (!bridge || !pci_bridge_d3_possible(bridge))
2972 * If D3 is currently allowed for the bridge, removing one of its
2973 * children won't change that.
2975 if (remove && bridge->bridge_d3)
2979 * If D3 is currently allowed for the bridge and a child is added or
2980 * changed, disallowance of D3 can only be caused by that child, so
2981 * we only need to check that single device, not any of its siblings.
2983 * If D3 is currently not allowed for the bridge, checking the device
2984 * first may allow us to skip checking its siblings.
2987 pci_dev_check_d3cold(dev, &d3cold_ok);
2990 * If D3 is currently not allowed for the bridge, this may be caused
2991 * either by the device being changed/removed or any of its siblings,
2992 * so we need to go through all children to find out if one of them
2993 * continues to block D3.
2995 if (d3cold_ok && !bridge->bridge_d3)
2996 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2999 if (bridge->bridge_d3 != d3cold_ok) {
3000 bridge->bridge_d3 = d3cold_ok;
3001 /* Propagate change to upstream bridges */
3002 pci_bridge_d3_update(bridge);
3007 * pci_d3cold_enable - Enable D3cold for device
3008 * @dev: PCI device to handle
3010 * This function can be used in drivers to enable D3cold from the device
3011 * they handle. It also updates upstream PCI bridge PM capabilities
3014 void pci_d3cold_enable(struct pci_dev *dev)
3016 if (dev->no_d3cold) {
3017 dev->no_d3cold = false;
3018 pci_bridge_d3_update(dev);
3021 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3024 * pci_d3cold_disable - Disable D3cold for device
3025 * @dev: PCI device to handle
3027 * This function can be used in drivers to disable D3cold from the device
3028 * they handle. It also updates upstream PCI bridge PM capabilities
3031 void pci_d3cold_disable(struct pci_dev *dev)
3033 if (!dev->no_d3cold) {
3034 dev->no_d3cold = true;
3035 pci_bridge_d3_update(dev);
3038 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3041 * pci_pm_init - Initialize PM functions of given PCI device
3042 * @dev: PCI device to handle.
3044 void pci_pm_init(struct pci_dev *dev)
3050 pm_runtime_forbid(&dev->dev);
3051 pm_runtime_set_active(&dev->dev);
3052 pm_runtime_enable(&dev->dev);
3053 device_enable_async_suspend(&dev->dev);
3054 dev->wakeup_prepared = false;
3057 dev->pme_support = 0;
3059 /* find PCI PM capability in list */
3060 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3063 /* Check device's ability to generate PME# */
3064 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3066 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3067 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3068 pmc & PCI_PM_CAP_VER_MASK);
3073 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3074 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3075 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3076 dev->d3cold_allowed = true;
3078 dev->d1_support = false;
3079 dev->d2_support = false;
3080 if (!pci_no_d1d2(dev)) {
3081 if (pmc & PCI_PM_CAP_D1)
3082 dev->d1_support = true;
3083 if (pmc & PCI_PM_CAP_D2)
3084 dev->d2_support = true;
3086 if (dev->d1_support || dev->d2_support)
3087 pci_info(dev, "supports%s%s\n",
3088 dev->d1_support ? " D1" : "",
3089 dev->d2_support ? " D2" : "");
3092 pmc &= PCI_PM_CAP_PME_MASK;
3094 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3095 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3096 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3097 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3098 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3099 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3100 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3101 dev->pme_poll = true;
3103 * Make device's PM flags reflect the wake-up capability, but
3104 * let the user space enable it to wake up the system as needed.
3106 device_set_wakeup_capable(&dev->dev, true);
3107 /* Disable the PME# generation functionality */
3108 pci_pme_active(dev, false);
3111 pci_read_config_word(dev, PCI_STATUS, &status);
3112 if (status & PCI_STATUS_IMM_READY)
3116 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3118 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3122 case PCI_EA_P_VF_MEM:
3123 flags |= IORESOURCE_MEM;
3125 case PCI_EA_P_MEM_PREFETCH:
3126 case PCI_EA_P_VF_MEM_PREFETCH:
3127 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3130 flags |= IORESOURCE_IO;
3139 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3142 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3143 return &dev->resource[bei];
3144 #ifdef CONFIG_PCI_IOV
3145 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3146 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3147 return &dev->resource[PCI_IOV_RESOURCES +
3148 bei - PCI_EA_BEI_VF_BAR0];
3150 else if (bei == PCI_EA_BEI_ROM)
3151 return &dev->resource[PCI_ROM_RESOURCE];
3156 /* Read an Enhanced Allocation (EA) entry */
3157 static int pci_ea_read(struct pci_dev *dev, int offset)
3159 struct resource *res;
3160 int ent_size, ent_offset = offset;
3161 resource_size_t start, end;
3162 unsigned long flags;
3163 u32 dw0, bei, base, max_offset;
3165 bool support_64 = (sizeof(resource_size_t) >= 8);
3167 pci_read_config_dword(dev, ent_offset, &dw0);
3170 /* Entry size field indicates DWORDs after 1st */
3171 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3173 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3176 bei = (dw0 & PCI_EA_BEI) >> 4;
3177 prop = (dw0 & PCI_EA_PP) >> 8;
3180 * If the Property is in the reserved range, try the Secondary
3183 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3184 prop = (dw0 & PCI_EA_SP) >> 16;
3185 if (prop > PCI_EA_P_BRIDGE_IO)
3188 res = pci_ea_get_resource(dev, bei, prop);
3190 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3194 flags = pci_ea_flags(dev, prop);
3196 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3201 pci_read_config_dword(dev, ent_offset, &base);
3202 start = (base & PCI_EA_FIELD_MASK);
3205 /* Read MaxOffset */
3206 pci_read_config_dword(dev, ent_offset, &max_offset);
3209 /* Read Base MSBs (if 64-bit entry) */
3210 if (base & PCI_EA_IS_64) {
3213 pci_read_config_dword(dev, ent_offset, &base_upper);
3216 flags |= IORESOURCE_MEM_64;
3218 /* entry starts above 32-bit boundary, can't use */
3219 if (!support_64 && base_upper)
3223 start |= ((u64)base_upper << 32);
3226 end = start + (max_offset | 0x03);
3228 /* Read MaxOffset MSBs (if 64-bit entry) */
3229 if (max_offset & PCI_EA_IS_64) {
3230 u32 max_offset_upper;
3232 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3235 flags |= IORESOURCE_MEM_64;
3237 /* entry too big, can't use */
3238 if (!support_64 && max_offset_upper)
3242 end += ((u64)max_offset_upper << 32);
3246 pci_err(dev, "EA Entry crosses address boundary\n");
3250 if (ent_size != ent_offset - offset) {
3251 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3252 ent_size, ent_offset - offset);
3256 res->name = pci_name(dev);
3261 if (bei <= PCI_EA_BEI_BAR5)
3262 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3264 else if (bei == PCI_EA_BEI_ROM)
3265 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3267 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3268 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3269 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3271 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3275 return offset + ent_size;
3278 /* Enhanced Allocation Initialization */
3279 void pci_ea_init(struct pci_dev *dev)
3286 /* find PCI EA capability in list */
3287 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3291 /* determine the number of entries */
3292 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3294 num_ent &= PCI_EA_NUM_ENT_MASK;
3296 offset = ea + PCI_EA_FIRST_ENT;
3298 /* Skip DWORD 2 for type 1 functions */
3299 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3302 /* parse each EA entry */
3303 for (i = 0; i < num_ent; ++i)
3304 offset = pci_ea_read(dev, offset);
3307 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3308 struct pci_cap_saved_state *new_cap)
3310 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3314 * _pci_add_cap_save_buffer - allocate buffer for saving given
3315 * capability registers
3316 * @dev: the PCI device
3317 * @cap: the capability to allocate the buffer for
3318 * @extended: Standard or Extended capability ID
3319 * @size: requested size of the buffer
3321 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3322 bool extended, unsigned int size)
3325 struct pci_cap_saved_state *save_state;
3328 pos = pci_find_ext_capability(dev, cap);
3330 pos = pci_find_capability(dev, cap);
3335 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3339 save_state->cap.cap_nr = cap;
3340 save_state->cap.cap_extended = extended;
3341 save_state->cap.size = size;
3342 pci_add_saved_cap(dev, save_state);
3347 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3349 return _pci_add_cap_save_buffer(dev, cap, false, size);
3352 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3354 return _pci_add_cap_save_buffer(dev, cap, true, size);
3358 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3359 * @dev: the PCI device
3361 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3365 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3366 PCI_EXP_SAVE_REGS * sizeof(u16));
3368 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3370 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3372 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3374 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3377 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3379 pci_allocate_vc_save_buffers(dev);
3382 void pci_free_cap_save_buffers(struct pci_dev *dev)
3384 struct pci_cap_saved_state *tmp;
3385 struct hlist_node *n;
3387 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3392 * pci_configure_ari - enable or disable ARI forwarding
3393 * @dev: the PCI device
3395 * If @dev and its upstream bridge both support ARI, enable ARI in the
3396 * bridge. Otherwise, disable ARI in the bridge.
3398 void pci_configure_ari(struct pci_dev *dev)
3401 struct pci_dev *bridge;
3403 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3406 bridge = dev->bus->self;
3410 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3411 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3414 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3415 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3416 PCI_EXP_DEVCTL2_ARI);
3417 bridge->ari_enabled = 1;
3419 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3420 PCI_EXP_DEVCTL2_ARI);
3421 bridge->ari_enabled = 0;
3425 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3430 pos = pdev->acs_cap;
3435 * Except for egress control, capabilities are either required
3436 * or only required if controllable. Features missing from the
3437 * capability field can therefore be assumed as hard-wired enabled.
3439 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3440 acs_flags &= (cap | PCI_ACS_EC);
3442 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3443 return (ctrl & acs_flags) == acs_flags;
3447 * pci_acs_enabled - test ACS against required flags for a given device
3448 * @pdev: device to test
3449 * @acs_flags: required PCI ACS flags
3451 * Return true if the device supports the provided flags. Automatically
3452 * filters out flags that are not implemented on multifunction devices.
3454 * Note that this interface checks the effective ACS capabilities of the
3455 * device rather than the actual capabilities. For instance, most single
3456 * function endpoints are not required to support ACS because they have no
3457 * opportunity for peer-to-peer access. We therefore return 'true'
3458 * regardless of whether the device exposes an ACS capability. This makes
3459 * it much easier for callers of this function to ignore the actual type
3460 * or topology of the device when testing ACS support.
3462 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3466 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3471 * Conventional PCI and PCI-X devices never support ACS, either
3472 * effectively or actually. The shared bus topology implies that
3473 * any device on the bus can receive or snoop DMA.
3475 if (!pci_is_pcie(pdev))
3478 switch (pci_pcie_type(pdev)) {
3480 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3481 * but since their primary interface is PCI/X, we conservatively
3482 * handle them as we would a non-PCIe device.
3484 case PCI_EXP_TYPE_PCIE_BRIDGE:
3486 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3487 * applicable... must never implement an ACS Extended Capability...".
3488 * This seems arbitrary, but we take a conservative interpretation
3489 * of this statement.
3491 case PCI_EXP_TYPE_PCI_BRIDGE:
3492 case PCI_EXP_TYPE_RC_EC:
3495 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3496 * implement ACS in order to indicate their peer-to-peer capabilities,
3497 * regardless of whether they are single- or multi-function devices.
3499 case PCI_EXP_TYPE_DOWNSTREAM:
3500 case PCI_EXP_TYPE_ROOT_PORT:
3501 return pci_acs_flags_enabled(pdev, acs_flags);
3503 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3504 * implemented by the remaining PCIe types to indicate peer-to-peer
3505 * capabilities, but only when they are part of a multifunction
3506 * device. The footnote for section 6.12 indicates the specific
3507 * PCIe types included here.
3509 case PCI_EXP_TYPE_ENDPOINT:
3510 case PCI_EXP_TYPE_UPSTREAM:
3511 case PCI_EXP_TYPE_LEG_END:
3512 case PCI_EXP_TYPE_RC_END:
3513 if (!pdev->multifunction)
3516 return pci_acs_flags_enabled(pdev, acs_flags);
3520 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3521 * to single function devices with the exception of downstream ports.
3527 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3528 * @start: starting downstream device
3529 * @end: ending upstream device or NULL to search to the root bus
3530 * @acs_flags: required flags
3532 * Walk up a device tree from start to end testing PCI ACS support. If
3533 * any step along the way does not support the required flags, return false.
3535 bool pci_acs_path_enabled(struct pci_dev *start,
3536 struct pci_dev *end, u16 acs_flags)
3538 struct pci_dev *pdev, *parent = start;
3543 if (!pci_acs_enabled(pdev, acs_flags))
3546 if (pci_is_root_bus(pdev->bus))
3547 return (end == NULL);
3549 parent = pdev->bus->self;
3550 } while (pdev != end);
3556 * pci_acs_init - Initialize ACS if hardware supports it
3557 * @dev: the PCI device
3559 void pci_acs_init(struct pci_dev *dev)
3561 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3564 * Attempt to enable ACS regardless of capability because some Root
3565 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3566 * the standard ACS capability but still support ACS via those
3569 pci_enable_acs(dev);
3573 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3577 * Helper to find the position of the ctrl register for a BAR.
3578 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3579 * Returns -ENOENT if no ctrl register for the BAR could be found.
3581 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3583 unsigned int pos, nbars, i;
3586 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3590 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3591 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3592 PCI_REBAR_CTRL_NBAR_SHIFT;
3594 for (i = 0; i < nbars; i++, pos += 8) {
3597 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3598 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3607 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3609 * @bar: BAR to query
3611 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3612 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3614 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3619 pos = pci_rebar_find_pos(pdev, bar);
3623 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3624 cap &= PCI_REBAR_CAP_SIZES;
3626 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3627 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3628 bar == 0 && cap == 0x7000)
3633 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3636 * pci_rebar_get_current_size - get the current size of a BAR
3638 * @bar: BAR to set size to
3640 * Read the size of a BAR from the resizable BAR config.
3641 * Returns size if found or negative error code.
3643 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3648 pos = pci_rebar_find_pos(pdev, bar);
3652 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3653 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3657 * pci_rebar_set_size - set a new size for a BAR
3659 * @bar: BAR to set size to
3660 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3662 * Set the new size of a BAR as defined in the spec.
3663 * Returns zero if resizing was successful, error code otherwise.
3665 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3670 pos = pci_rebar_find_pos(pdev, bar);
3674 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3675 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3676 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3677 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3682 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3683 * @dev: the PCI device
3684 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3685 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3686 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3687 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3689 * Return 0 if all upstream bridges support AtomicOp routing, egress
3690 * blocking is disabled on all upstream ports, and the root port supports
3691 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3692 * AtomicOp completion), or negative otherwise.
3694 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3696 struct pci_bus *bus = dev->bus;
3697 struct pci_dev *bridge;
3700 if (!pci_is_pcie(dev))
3704 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3705 * AtomicOp requesters. For now, we only support endpoints as
3706 * requesters and root ports as completers. No endpoints as
3707 * completers, and no peer-to-peer.
3710 switch (pci_pcie_type(dev)) {
3711 case PCI_EXP_TYPE_ENDPOINT:
3712 case PCI_EXP_TYPE_LEG_END:
3713 case PCI_EXP_TYPE_RC_END:
3719 while (bus->parent) {
3722 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3724 switch (pci_pcie_type(bridge)) {
3725 /* Ensure switch ports support AtomicOp routing */
3726 case PCI_EXP_TYPE_UPSTREAM:
3727 case PCI_EXP_TYPE_DOWNSTREAM:
3728 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3732 /* Ensure root port supports all the sizes we care about */
3733 case PCI_EXP_TYPE_ROOT_PORT:
3734 if ((cap & cap_mask) != cap_mask)
3739 /* Ensure upstream ports don't block AtomicOps on egress */
3740 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3741 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3743 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3750 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3751 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3754 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3757 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3758 * @dev: the PCI device
3759 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3761 * Perform INTx swizzling for a device behind one level of bridge. This is
3762 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3763 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3764 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3765 * the PCI Express Base Specification, Revision 2.1)
3767 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3771 if (pci_ari_enabled(dev->bus))
3774 slot = PCI_SLOT(dev->devfn);
3776 return (((pin - 1) + slot) % 4) + 1;
3779 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3787 while (!pci_is_root_bus(dev->bus)) {
3788 pin = pci_swizzle_interrupt_pin(dev, pin);
3789 dev = dev->bus->self;
3796 * pci_common_swizzle - swizzle INTx all the way to root bridge
3797 * @dev: the PCI device
3798 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3800 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3801 * bridges all the way up to a PCI root bus.
3803 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3807 while (!pci_is_root_bus(dev->bus)) {
3808 pin = pci_swizzle_interrupt_pin(dev, pin);
3809 dev = dev->bus->self;
3812 return PCI_SLOT(dev->devfn);
3814 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3817 * pci_release_region - Release a PCI bar
3818 * @pdev: PCI device whose resources were previously reserved by
3819 * pci_request_region()
3820 * @bar: BAR to release
3822 * Releases the PCI I/O and memory resources previously reserved by a
3823 * successful call to pci_request_region(). Call this function only
3824 * after all use of the PCI regions has ceased.
3826 void pci_release_region(struct pci_dev *pdev, int bar)
3828 struct pci_devres *dr;
3830 if (pci_resource_len(pdev, bar) == 0)
3832 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3833 release_region(pci_resource_start(pdev, bar),
3834 pci_resource_len(pdev, bar));
3835 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3836 release_mem_region(pci_resource_start(pdev, bar),
3837 pci_resource_len(pdev, bar));
3839 dr = find_pci_dr(pdev);
3841 dr->region_mask &= ~(1 << bar);
3843 EXPORT_SYMBOL(pci_release_region);
3846 * __pci_request_region - Reserved PCI I/O and memory resource
3847 * @pdev: PCI device whose resources are to be reserved
3848 * @bar: BAR to be reserved
3849 * @res_name: Name to be associated with resource.
3850 * @exclusive: whether the region access is exclusive or not
3852 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3853 * being reserved by owner @res_name. Do not access any
3854 * address inside the PCI regions unless this call returns
3857 * If @exclusive is set, then the region is marked so that userspace
3858 * is explicitly not allowed to map the resource via /dev/mem or
3859 * sysfs MMIO access.
3861 * Returns 0 on success, or %EBUSY on error. A warning
3862 * message is also printed on failure.
3864 static int __pci_request_region(struct pci_dev *pdev, int bar,
3865 const char *res_name, int exclusive)
3867 struct pci_devres *dr;
3869 if (pci_resource_len(pdev, bar) == 0)
3872 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3873 if (!request_region(pci_resource_start(pdev, bar),
3874 pci_resource_len(pdev, bar), res_name))
3876 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3877 if (!__request_mem_region(pci_resource_start(pdev, bar),
3878 pci_resource_len(pdev, bar), res_name,
3883 dr = find_pci_dr(pdev);
3885 dr->region_mask |= 1 << bar;
3890 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3891 &pdev->resource[bar]);
3896 * pci_request_region - Reserve PCI I/O and memory resource
3897 * @pdev: PCI device whose resources are to be reserved
3898 * @bar: BAR to be reserved
3899 * @res_name: Name to be associated with resource
3901 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3902 * being reserved by owner @res_name. Do not access any
3903 * address inside the PCI regions unless this call returns
3906 * Returns 0 on success, or %EBUSY on error. A warning
3907 * message is also printed on failure.
3909 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3911 return __pci_request_region(pdev, bar, res_name, 0);
3913 EXPORT_SYMBOL(pci_request_region);
3916 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3917 * @pdev: PCI device whose resources were previously reserved
3918 * @bars: Bitmask of BARs to be released
3920 * Release selected PCI I/O and memory resources previously reserved.
3921 * Call this function only after all use of the PCI regions has ceased.
3923 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3927 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3928 if (bars & (1 << i))
3929 pci_release_region(pdev, i);
3931 EXPORT_SYMBOL(pci_release_selected_regions);
3933 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3934 const char *res_name, int excl)
3938 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3939 if (bars & (1 << i))
3940 if (__pci_request_region(pdev, i, res_name, excl))
3946 if (bars & (1 << i))
3947 pci_release_region(pdev, i);
3954 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3955 * @pdev: PCI device whose resources are to be reserved
3956 * @bars: Bitmask of BARs to be requested
3957 * @res_name: Name to be associated with resource
3959 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3960 const char *res_name)
3962 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3964 EXPORT_SYMBOL(pci_request_selected_regions);
3966 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3967 const char *res_name)
3969 return __pci_request_selected_regions(pdev, bars, res_name,
3970 IORESOURCE_EXCLUSIVE);
3972 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3975 * pci_release_regions - Release reserved PCI I/O and memory resources
3976 * @pdev: PCI device whose resources were previously reserved by
3977 * pci_request_regions()
3979 * Releases all PCI I/O and memory resources previously reserved by a
3980 * successful call to pci_request_regions(). Call this function only
3981 * after all use of the PCI regions has ceased.
3984 void pci_release_regions(struct pci_dev *pdev)
3986 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
3988 EXPORT_SYMBOL(pci_release_regions);
3991 * pci_request_regions - Reserve PCI I/O and memory resources
3992 * @pdev: PCI device whose resources are to be reserved
3993 * @res_name: Name to be associated with resource.
3995 * Mark all PCI regions associated with PCI device @pdev as
3996 * being reserved by owner @res_name. Do not access any
3997 * address inside the PCI regions unless this call returns
4000 * Returns 0 on success, or %EBUSY on error. A warning
4001 * message is also printed on failure.
4003 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4005 return pci_request_selected_regions(pdev,
4006 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4008 EXPORT_SYMBOL(pci_request_regions);
4011 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4012 * @pdev: PCI device whose resources are to be reserved
4013 * @res_name: Name to be associated with resource.
4015 * Mark all PCI regions associated with PCI device @pdev as being reserved
4016 * by owner @res_name. Do not access any address inside the PCI regions
4017 * unless this call returns successfully.
4019 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4020 * and the sysfs MMIO access will not be allowed.
4022 * Returns 0 on success, or %EBUSY on error. A warning message is also
4023 * printed on failure.
4025 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4027 return pci_request_selected_regions_exclusive(pdev,
4028 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4030 EXPORT_SYMBOL(pci_request_regions_exclusive);
4033 * Record the PCI IO range (expressed as CPU physical address + size).
4034 * Return a negative value if an error has occurred, zero otherwise
4036 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4037 resource_size_t size)
4041 struct logic_pio_hwaddr *range;
4043 if (!size || addr + size < addr)
4046 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4050 range->fwnode = fwnode;
4052 range->hw_start = addr;
4053 range->flags = LOGIC_PIO_CPU_MMIO;
4055 ret = logic_pio_register_range(range);
4059 /* Ignore duplicates due to deferred probing */
4067 phys_addr_t pci_pio_to_address(unsigned long pio)
4069 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4072 if (pio >= MMIO_UPPER_LIMIT)
4075 address = logic_pio_to_hwaddr(pio);
4080 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4082 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4085 return logic_pio_trans_cpuaddr(address);
4087 if (address > IO_SPACE_LIMIT)
4088 return (unsigned long)-1;
4090 return (unsigned long) address;
4095 * pci_remap_iospace - Remap the memory mapped I/O space
4096 * @res: Resource describing the I/O space
4097 * @phys_addr: physical address of range to be mapped
4099 * Remap the memory mapped I/O space described by the @res and the CPU
4100 * physical address @phys_addr into virtual address space. Only
4101 * architectures that have memory mapped IO functions defined (and the
4102 * PCI_IOBASE value defined) should call this function.
4104 #ifndef pci_remap_iospace
4105 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4107 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4108 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4110 if (!(res->flags & IORESOURCE_IO))
4113 if (res->end > IO_SPACE_LIMIT)
4116 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4117 pgprot_device(PAGE_KERNEL));
4120 * This architecture does not have memory mapped I/O space,
4121 * so this function should never be called
4123 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4127 EXPORT_SYMBOL(pci_remap_iospace);
4131 * pci_unmap_iospace - Unmap the memory mapped I/O space
4132 * @res: resource to be unmapped
4134 * Unmap the CPU virtual address @res from virtual address space. Only
4135 * architectures that have memory mapped IO functions defined (and the
4136 * PCI_IOBASE value defined) should call this function.
4138 void pci_unmap_iospace(struct resource *res)
4140 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4141 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4143 vunmap_range(vaddr, vaddr + resource_size(res));
4146 EXPORT_SYMBOL(pci_unmap_iospace);
4148 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4150 struct resource **res = ptr;
4152 pci_unmap_iospace(*res);
4156 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4157 * @dev: Generic device to remap IO address for
4158 * @res: Resource describing the I/O space
4159 * @phys_addr: physical address of range to be mapped
4161 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4164 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4165 phys_addr_t phys_addr)
4167 const struct resource **ptr;
4170 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4174 error = pci_remap_iospace(res, phys_addr);
4179 devres_add(dev, ptr);
4184 EXPORT_SYMBOL(devm_pci_remap_iospace);
4187 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4188 * @dev: Generic device to remap IO address for
4189 * @offset: Resource address to map
4190 * @size: Size of map
4192 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4195 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4196 resource_size_t offset,
4197 resource_size_t size)
4199 void __iomem **ptr, *addr;
4201 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4205 addr = pci_remap_cfgspace(offset, size);
4208 devres_add(dev, ptr);
4214 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4217 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4218 * @dev: generic device to handle the resource for
4219 * @res: configuration space resource to be handled
4221 * Checks that a resource is a valid memory region, requests the memory
4222 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4223 * proper PCI configuration space memory attributes are guaranteed.
4225 * All operations are managed and will be undone on driver detach.
4227 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4228 * on failure. Usage example::
4230 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4231 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4233 * return PTR_ERR(base);
4235 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4236 struct resource *res)
4238 resource_size_t size;
4240 void __iomem *dest_ptr;
4244 if (!res || resource_type(res) != IORESOURCE_MEM) {
4245 dev_err(dev, "invalid resource\n");
4246 return IOMEM_ERR_PTR(-EINVAL);
4249 size = resource_size(res);
4252 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4255 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4257 return IOMEM_ERR_PTR(-ENOMEM);
4259 if (!devm_request_mem_region(dev, res->start, size, name)) {
4260 dev_err(dev, "can't request region for resource %pR\n", res);
4261 return IOMEM_ERR_PTR(-EBUSY);
4264 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4266 dev_err(dev, "ioremap failed for resource %pR\n", res);
4267 devm_release_mem_region(dev, res->start, size);
4268 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4273 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4275 static void __pci_set_master(struct pci_dev *dev, bool enable)
4279 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4281 cmd = old_cmd | PCI_COMMAND_MASTER;
4283 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4284 if (cmd != old_cmd) {
4285 pci_dbg(dev, "%s bus mastering\n",
4286 enable ? "enabling" : "disabling");
4287 pci_write_config_word(dev, PCI_COMMAND, cmd);
4289 dev->is_busmaster = enable;
4293 * pcibios_setup - process "pci=" kernel boot arguments
4294 * @str: string used to pass in "pci=" kernel boot arguments
4296 * Process kernel boot arguments. This is the default implementation.
4297 * Architecture specific implementations can override this as necessary.
4299 char * __weak __init pcibios_setup(char *str)
4305 * pcibios_set_master - enable PCI bus-mastering for device dev
4306 * @dev: the PCI device to enable
4308 * Enables PCI bus-mastering for the device. This is the default
4309 * implementation. Architecture specific implementations can override
4310 * this if necessary.
4312 void __weak pcibios_set_master(struct pci_dev *dev)
4316 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4317 if (pci_is_pcie(dev))
4320 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4322 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4323 else if (lat > pcibios_max_latency)
4324 lat = pcibios_max_latency;
4328 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4332 * pci_set_master - enables bus-mastering for device dev
4333 * @dev: the PCI device to enable
4335 * Enables bus-mastering on the device and calls pcibios_set_master()
4336 * to do the needed arch specific settings.
4338 void pci_set_master(struct pci_dev *dev)
4340 __pci_set_master(dev, true);
4341 pcibios_set_master(dev);
4343 EXPORT_SYMBOL(pci_set_master);
4346 * pci_clear_master - disables bus-mastering for device dev
4347 * @dev: the PCI device to disable
4349 void pci_clear_master(struct pci_dev *dev)
4351 __pci_set_master(dev, false);
4353 EXPORT_SYMBOL(pci_clear_master);
4356 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4357 * @dev: the PCI device for which MWI is to be enabled
4359 * Helper function for pci_set_mwi.
4360 * Originally copied from drivers/net/acenic.c.
4361 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4363 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4365 int pci_set_cacheline_size(struct pci_dev *dev)
4369 if (!pci_cache_line_size)
4372 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4373 equal to or multiple of the right value. */
4374 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4375 if (cacheline_size >= pci_cache_line_size &&
4376 (cacheline_size % pci_cache_line_size) == 0)
4379 /* Write the correct value. */
4380 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4382 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4383 if (cacheline_size == pci_cache_line_size)
4386 pci_dbg(dev, "cache line size of %d is not supported\n",
4387 pci_cache_line_size << 2);
4391 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4394 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4395 * @dev: the PCI device for which MWI is enabled
4397 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4399 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4401 int pci_set_mwi(struct pci_dev *dev)
4403 #ifdef PCI_DISABLE_MWI
4409 rc = pci_set_cacheline_size(dev);
4413 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4414 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4415 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4416 cmd |= PCI_COMMAND_INVALIDATE;
4417 pci_write_config_word(dev, PCI_COMMAND, cmd);
4422 EXPORT_SYMBOL(pci_set_mwi);
4425 * pcim_set_mwi - a device-managed pci_set_mwi()
4426 * @dev: the PCI device for which MWI is enabled
4428 * Managed pci_set_mwi().
4430 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4432 int pcim_set_mwi(struct pci_dev *dev)
4434 struct pci_devres *dr;
4436 dr = find_pci_dr(dev);
4441 return pci_set_mwi(dev);
4443 EXPORT_SYMBOL(pcim_set_mwi);
4446 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4447 * @dev: the PCI device for which MWI is enabled
4449 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4450 * Callers are not required to check the return value.
4452 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4454 int pci_try_set_mwi(struct pci_dev *dev)
4456 #ifdef PCI_DISABLE_MWI
4459 return pci_set_mwi(dev);
4462 EXPORT_SYMBOL(pci_try_set_mwi);
4465 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4466 * @dev: the PCI device to disable
4468 * Disables PCI Memory-Write-Invalidate transaction on the device
4470 void pci_clear_mwi(struct pci_dev *dev)
4472 #ifndef PCI_DISABLE_MWI
4475 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4476 if (cmd & PCI_COMMAND_INVALIDATE) {
4477 cmd &= ~PCI_COMMAND_INVALIDATE;
4478 pci_write_config_word(dev, PCI_COMMAND, cmd);
4482 EXPORT_SYMBOL(pci_clear_mwi);
4485 * pci_disable_parity - disable parity checking for device
4486 * @dev: the PCI device to operate on
4488 * Disable parity checking for device @dev
4490 void pci_disable_parity(struct pci_dev *dev)
4494 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4495 if (cmd & PCI_COMMAND_PARITY) {
4496 cmd &= ~PCI_COMMAND_PARITY;
4497 pci_write_config_word(dev, PCI_COMMAND, cmd);
4502 * pci_intx - enables/disables PCI INTx for device dev
4503 * @pdev: the PCI device to operate on
4504 * @enable: boolean: whether to enable or disable PCI INTx
4506 * Enables/disables PCI INTx for device @pdev
4508 void pci_intx(struct pci_dev *pdev, int enable)
4510 u16 pci_command, new;
4512 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4515 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4517 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4519 if (new != pci_command) {
4520 struct pci_devres *dr;
4522 pci_write_config_word(pdev, PCI_COMMAND, new);
4524 dr = find_pci_dr(pdev);
4525 if (dr && !dr->restore_intx) {
4526 dr->restore_intx = 1;
4527 dr->orig_intx = !enable;
4531 EXPORT_SYMBOL_GPL(pci_intx);
4533 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4535 struct pci_bus *bus = dev->bus;
4536 bool mask_updated = true;
4537 u32 cmd_status_dword;
4538 u16 origcmd, newcmd;
4539 unsigned long flags;
4543 * We do a single dword read to retrieve both command and status.
4544 * Document assumptions that make this possible.
4546 BUILD_BUG_ON(PCI_COMMAND % 4);
4547 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4549 raw_spin_lock_irqsave(&pci_lock, flags);
4551 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4553 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4556 * Check interrupt status register to see whether our device
4557 * triggered the interrupt (when masking) or the next IRQ is
4558 * already pending (when unmasking).
4560 if (mask != irq_pending) {
4561 mask_updated = false;
4565 origcmd = cmd_status_dword;
4566 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4568 newcmd |= PCI_COMMAND_INTX_DISABLE;
4569 if (newcmd != origcmd)
4570 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4573 raw_spin_unlock_irqrestore(&pci_lock, flags);
4575 return mask_updated;
4579 * pci_check_and_mask_intx - mask INTx on pending interrupt
4580 * @dev: the PCI device to operate on
4582 * Check if the device dev has its INTx line asserted, mask it and return
4583 * true in that case. False is returned if no interrupt was pending.
4585 bool pci_check_and_mask_intx(struct pci_dev *dev)
4587 return pci_check_and_set_intx_mask(dev, true);
4589 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4592 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4593 * @dev: the PCI device to operate on
4595 * Check if the device dev has its INTx line asserted, unmask it if not and
4596 * return true. False is returned and the mask remains active if there was
4597 * still an interrupt pending.
4599 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4601 return pci_check_and_set_intx_mask(dev, false);
4603 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4606 * pci_wait_for_pending_transaction - wait for pending transaction
4607 * @dev: the PCI device to operate on
4609 * Return 0 if transaction is pending 1 otherwise.
4611 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4613 if (!pci_is_pcie(dev))
4616 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4617 PCI_EXP_DEVSTA_TRPND);
4619 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4622 * pcie_flr - initiate a PCIe function level reset
4623 * @dev: device to reset
4625 * Initiate a function level reset unconditionally on @dev without
4626 * checking any flags and DEVCAP
4628 int pcie_flr(struct pci_dev *dev)
4630 if (!pci_wait_for_pending_transaction(dev))
4631 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4633 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4639 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4640 * 100ms, but may silently discard requests while the FLR is in
4641 * progress. Wait 100ms before trying to access the device.
4645 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4647 EXPORT_SYMBOL_GPL(pcie_flr);
4650 * pcie_reset_flr - initiate a PCIe function level reset
4651 * @dev: device to reset
4652 * @probe: if true, return 0 if device can be reset this way
4654 * Initiate a function level reset on @dev.
4656 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4658 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4661 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4667 return pcie_flr(dev);
4669 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4671 static int pci_af_flr(struct pci_dev *dev, bool probe)
4676 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4680 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4683 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4684 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4691 * Wait for Transaction Pending bit to clear. A word-aligned test
4692 * is used, so we use the control offset rather than status and shift
4693 * the test bit to match.
4695 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4696 PCI_AF_STATUS_TP << 8))
4697 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4699 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4705 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4706 * updated 27 July 2006; a device must complete an FLR within
4707 * 100ms, but may silently discard requests while the FLR is in
4708 * progress. Wait 100ms before trying to access the device.
4712 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4716 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4717 * @dev: Device to reset.
4718 * @probe: if true, return 0 if the device can be reset this way.
4720 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4721 * unset, it will be reinitialized internally when going from PCI_D3hot to
4722 * PCI_D0. If that's the case and the device is not in a low-power state
4723 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4725 * NOTE: This causes the caller to sleep for twice the device power transition
4726 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4727 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4728 * Moreover, only devices in D0 can be reset by this function.
4730 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4734 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4737 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4738 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4744 if (dev->current_state != PCI_D0)
4747 csr &= ~PCI_PM_CTRL_STATE_MASK;
4749 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4750 pci_dev_d3_sleep(dev);
4752 csr &= ~PCI_PM_CTRL_STATE_MASK;
4754 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4755 pci_dev_d3_sleep(dev);
4757 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4761 * pcie_wait_for_link_delay - Wait until link is active or inactive
4762 * @pdev: Bridge device
4763 * @active: waiting for active or inactive?
4764 * @delay: Delay to wait after link has become active (in ms)
4766 * Use this to wait till link becomes active or inactive.
4768 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4776 * Some controllers might not implement link active reporting. In this
4777 * case, we wait for 1000 ms + any delay requested by the caller.
4779 if (!pdev->link_active_reporting) {
4780 msleep(timeout + delay);
4785 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4786 * after which we should expect an link active if the reset was
4787 * successful. If so, software must wait a minimum 100ms before sending
4788 * configuration requests to devices downstream this port.
4790 * If the link fails to activate, either the device was physically
4791 * removed or the link is permanently failed.
4796 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4797 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4808 return ret == active;
4812 * pcie_wait_for_link - Wait until link is active or inactive
4813 * @pdev: Bridge device
4814 * @active: waiting for active or inactive?
4816 * Use this to wait till link becomes active or inactive.
4818 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4820 return pcie_wait_for_link_delay(pdev, active, 100);
4824 * Find maximum D3cold delay required by all the devices on the bus. The
4825 * spec says 100 ms, but firmware can lower it and we allow drivers to
4826 * increase it as well.
4828 * Called with @pci_bus_sem locked for reading.
4830 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4832 const struct pci_dev *pdev;
4833 int min_delay = 100;
4836 list_for_each_entry(pdev, &bus->devices, bus_list) {
4837 if (pdev->d3cold_delay < min_delay)
4838 min_delay = pdev->d3cold_delay;
4839 if (pdev->d3cold_delay > max_delay)
4840 max_delay = pdev->d3cold_delay;
4843 return max(min_delay, max_delay);
4847 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4850 * Handle necessary delays before access to the devices on the secondary
4851 * side of the bridge are permitted after D3cold to D0 transition.
4853 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4854 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4857 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4859 struct pci_dev *child;
4862 if (pci_dev_is_disconnected(dev))
4865 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4868 down_read(&pci_bus_sem);
4871 * We only deal with devices that are present currently on the bus.
4872 * For any hot-added devices the access delay is handled in pciehp
4873 * board_added(). In case of ACPI hotplug the firmware is expected
4874 * to configure the devices before OS is notified.
4876 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4877 up_read(&pci_bus_sem);
4881 /* Take d3cold_delay requirements into account */
4882 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4884 up_read(&pci_bus_sem);
4888 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4890 up_read(&pci_bus_sem);
4893 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4894 * accessing the device after reset (that is 1000 ms + 100 ms). In
4895 * practice this should not be needed because we don't do power
4896 * management for them (see pci_bridge_d3_possible()).
4898 if (!pci_is_pcie(dev)) {
4899 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4900 msleep(1000 + delay);
4905 * For PCIe downstream and root ports that do not support speeds
4906 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4907 * speeds (gen3) we need to wait first for the data link layer to
4910 * However, 100 ms is the minimum and the PCIe spec says the
4911 * software must allow at least 1s before it can determine that the
4912 * device that did not respond is a broken device. There is
4913 * evidence that 100 ms is not always enough, for example certain
4914 * Titan Ridge xHCI controller does not always respond to
4915 * configuration requests if we only wait for 100 ms (see
4916 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4918 * Therefore we wait for 100 ms and check for the device presence.
4919 * If it is still not present give it an additional 100 ms.
4921 if (!pcie_downstream_port(dev))
4924 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4925 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4928 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4930 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4931 /* Did not train, no need to wait any further */
4932 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4937 if (!pci_device_is_present(child)) {
4938 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4943 void pci_reset_secondary_bus(struct pci_dev *dev)
4947 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4948 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4949 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4952 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4953 * this to 2ms to ensure that we meet the minimum requirement.
4957 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4958 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4961 * Trhfa for conventional PCI is 2^25 clock cycles.
4962 * Assuming a minimum 33MHz clock this results in a 1s
4963 * delay before we can consider subordinate devices to
4964 * be re-initialized. PCIe has some ways to shorten this,
4965 * but we don't make use of them yet.
4970 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4972 pci_reset_secondary_bus(dev);
4976 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4977 * @dev: Bridge device
4979 * Use the bridge control register to assert reset on the secondary bus.
4980 * Devices on the secondary bus are left in power-on state.
4982 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4984 pcibios_reset_secondary_bus(dev);
4986 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4988 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4990 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
4992 struct pci_dev *pdev;
4994 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4995 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4998 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5005 return pci_bridge_secondary_bus_reset(dev->bus->self);
5008 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5012 if (!hotplug || !try_module_get(hotplug->owner))
5015 if (hotplug->ops->reset_slot)
5016 rc = hotplug->ops->reset_slot(hotplug, probe);
5018 module_put(hotplug->owner);
5023 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5025 if (dev->multifunction || dev->subordinate || !dev->slot ||
5026 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5029 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5032 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5036 rc = pci_dev_reset_slot_function(dev, probe);
5039 return pci_parent_bus_reset(dev, probe);
5042 static void pci_dev_lock(struct pci_dev *dev)
5044 pci_cfg_access_lock(dev);
5045 /* block PM suspend, driver probe, etc. */
5046 device_lock(&dev->dev);
5049 /* Return 1 on successful lock, 0 on contention */
5050 int pci_dev_trylock(struct pci_dev *dev)
5052 if (pci_cfg_access_trylock(dev)) {
5053 if (device_trylock(&dev->dev))
5055 pci_cfg_access_unlock(dev);
5060 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5062 void pci_dev_unlock(struct pci_dev *dev)
5064 device_unlock(&dev->dev);
5065 pci_cfg_access_unlock(dev);
5067 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5069 static void pci_dev_save_and_disable(struct pci_dev *dev)
5071 const struct pci_error_handlers *err_handler =
5072 dev->driver ? dev->driver->err_handler : NULL;
5075 * dev->driver->err_handler->reset_prepare() is protected against
5076 * races with ->remove() by the device lock, which must be held by
5079 if (err_handler && err_handler->reset_prepare)
5080 err_handler->reset_prepare(dev);
5083 * Wake-up device prior to save. PM registers default to D0 after
5084 * reset and a simple register restore doesn't reliably return
5085 * to a non-D0 state anyway.
5087 pci_set_power_state(dev, PCI_D0);
5089 pci_save_state(dev);
5091 * Disable the device by clearing the Command register, except for
5092 * INTx-disable which is set. This not only disables MMIO and I/O port
5093 * BARs, but also prevents the device from being Bus Master, preventing
5094 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5095 * compliant devices, INTx-disable prevents legacy interrupts.
5097 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5100 static void pci_dev_restore(struct pci_dev *dev)
5102 const struct pci_error_handlers *err_handler =
5103 dev->driver ? dev->driver->err_handler : NULL;
5105 pci_restore_state(dev);
5108 * dev->driver->err_handler->reset_done() is protected against
5109 * races with ->remove() by the device lock, which must be held by
5112 if (err_handler && err_handler->reset_done)
5113 err_handler->reset_done(dev);
5116 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5117 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5119 { pci_dev_specific_reset, .name = "device_specific" },
5120 { pci_dev_acpi_reset, .name = "acpi" },
5121 { pcie_reset_flr, .name = "flr" },
5122 { pci_af_flr, .name = "af_flr" },
5123 { pci_pm_reset, .name = "pm" },
5124 { pci_reset_bus_function, .name = "bus" },
5127 static ssize_t reset_method_show(struct device *dev,
5128 struct device_attribute *attr, char *buf)
5130 struct pci_dev *pdev = to_pci_dev(dev);
5134 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5135 m = pdev->reset_methods[i];
5139 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5140 pci_reset_fn_methods[m].name);
5144 len += sysfs_emit_at(buf, len, "\n");
5149 static int reset_method_lookup(const char *name)
5153 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5154 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5158 return 0; /* not found */
5161 static ssize_t reset_method_store(struct device *dev,
5162 struct device_attribute *attr,
5163 const char *buf, size_t count)
5165 struct pci_dev *pdev = to_pci_dev(dev);
5166 char *options, *name;
5168 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5170 if (sysfs_streq(buf, "")) {
5171 pdev->reset_methods[0] = 0;
5172 pci_warn(pdev, "All device reset methods disabled by user");
5176 if (sysfs_streq(buf, "default")) {
5177 pci_init_reset_methods(pdev);
5181 options = kstrndup(buf, count, GFP_KERNEL);
5186 while ((name = strsep(&options, " ")) != NULL) {
5187 if (sysfs_streq(name, ""))
5192 m = reset_method_lookup(name);
5194 pci_err(pdev, "Invalid reset method '%s'", name);
5198 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5199 pci_err(pdev, "Unsupported reset method '%s'", name);
5203 if (n == PCI_NUM_RESET_METHODS - 1) {
5204 pci_err(pdev, "Too many reset methods\n");
5208 reset_methods[n++] = m;
5211 reset_methods[n] = 0;
5213 /* Warn if dev-specific supported but not highest priority */
5214 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5215 reset_methods[0] != 1)
5216 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5217 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5222 /* Leave previous methods unchanged */
5226 static DEVICE_ATTR_RW(reset_method);
5228 static struct attribute *pci_dev_reset_method_attrs[] = {
5229 &dev_attr_reset_method.attr,
5233 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5234 struct attribute *a, int n)
5236 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5238 if (!pci_reset_supported(pdev))
5244 const struct attribute_group pci_dev_reset_method_attr_group = {
5245 .attrs = pci_dev_reset_method_attrs,
5246 .is_visible = pci_dev_reset_method_attr_is_visible,
5250 * __pci_reset_function_locked - reset a PCI device function while holding
5251 * the @dev mutex lock.
5252 * @dev: PCI device to reset
5254 * Some devices allow an individual function to be reset without affecting
5255 * other functions in the same device. The PCI device must be responsive
5256 * to PCI config space in order to use this function.
5258 * The device function is presumed to be unused and the caller is holding
5259 * the device mutex lock when this function is called.
5261 * Resetting the device will make the contents of PCI configuration space
5262 * random, so any caller of this must be prepared to reinitialise the
5263 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5266 * Returns 0 if the device function was successfully reset or negative if the
5267 * device doesn't support resetting a single function.
5269 int __pci_reset_function_locked(struct pci_dev *dev)
5271 int i, m, rc = -ENOTTY;
5276 * A reset method returns -ENOTTY if it doesn't support this device and
5277 * we should try the next method.
5279 * If it returns 0 (success), we're finished. If it returns any other
5280 * error, we're also finished: this indicates that further reset
5281 * mechanisms might be broken on the device.
5283 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5284 m = dev->reset_methods[i];
5288 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5297 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5300 * pci_init_reset_methods - check whether device can be safely reset
5301 * and store supported reset mechanisms.
5302 * @dev: PCI device to check for reset mechanisms
5304 * Some devices allow an individual function to be reset without affecting
5305 * other functions in the same device. The PCI device must be in D0-D3hot
5308 * Stores reset mechanisms supported by device in reset_methods byte array
5309 * which is a member of struct pci_dev.
5311 void pci_init_reset_methods(struct pci_dev *dev)
5315 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5320 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5321 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5323 dev->reset_methods[i++] = m;
5324 else if (rc != -ENOTTY)
5328 dev->reset_methods[i] = 0;
5332 * pci_reset_function - quiesce and reset a PCI device function
5333 * @dev: PCI device to reset
5335 * Some devices allow an individual function to be reset without affecting
5336 * other functions in the same device. The PCI device must be responsive
5337 * to PCI config space in order to use this function.
5339 * This function does not just reset the PCI portion of a device, but
5340 * clears all the state associated with the device. This function differs
5341 * from __pci_reset_function_locked() in that it saves and restores device state
5342 * over the reset and takes the PCI device lock.
5344 * Returns 0 if the device function was successfully reset or negative if the
5345 * device doesn't support resetting a single function.
5347 int pci_reset_function(struct pci_dev *dev)
5351 if (!pci_reset_supported(dev))
5355 pci_dev_save_and_disable(dev);
5357 rc = __pci_reset_function_locked(dev);
5359 pci_dev_restore(dev);
5360 pci_dev_unlock(dev);
5364 EXPORT_SYMBOL_GPL(pci_reset_function);
5367 * pci_reset_function_locked - quiesce and reset a PCI device function
5368 * @dev: PCI device to reset
5370 * Some devices allow an individual function to be reset without affecting
5371 * other functions in the same device. The PCI device must be responsive
5372 * to PCI config space in order to use this function.
5374 * This function does not just reset the PCI portion of a device, but
5375 * clears all the state associated with the device. This function differs
5376 * from __pci_reset_function_locked() in that it saves and restores device state
5377 * over the reset. It also differs from pci_reset_function() in that it
5378 * requires the PCI device lock to be held.
5380 * Returns 0 if the device function was successfully reset or negative if the
5381 * device doesn't support resetting a single function.
5383 int pci_reset_function_locked(struct pci_dev *dev)
5387 if (!pci_reset_supported(dev))
5390 pci_dev_save_and_disable(dev);
5392 rc = __pci_reset_function_locked(dev);
5394 pci_dev_restore(dev);
5398 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5401 * pci_try_reset_function - quiesce and reset a PCI device function
5402 * @dev: PCI device to reset
5404 * Same as above, except return -EAGAIN if unable to lock device.
5406 int pci_try_reset_function(struct pci_dev *dev)
5410 if (!pci_reset_supported(dev))
5413 if (!pci_dev_trylock(dev))
5416 pci_dev_save_and_disable(dev);
5417 rc = __pci_reset_function_locked(dev);
5418 pci_dev_restore(dev);
5419 pci_dev_unlock(dev);
5423 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5425 /* Do any devices on or below this bus prevent a bus reset? */
5426 static bool pci_bus_resetable(struct pci_bus *bus)
5428 struct pci_dev *dev;
5431 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5434 list_for_each_entry(dev, &bus->devices, bus_list) {
5435 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5436 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5443 /* Lock devices from the top of the tree down */
5444 static void pci_bus_lock(struct pci_bus *bus)
5446 struct pci_dev *dev;
5448 list_for_each_entry(dev, &bus->devices, bus_list) {
5450 if (dev->subordinate)
5451 pci_bus_lock(dev->subordinate);
5455 /* Unlock devices from the bottom of the tree up */
5456 static void pci_bus_unlock(struct pci_bus *bus)
5458 struct pci_dev *dev;
5460 list_for_each_entry(dev, &bus->devices, bus_list) {
5461 if (dev->subordinate)
5462 pci_bus_unlock(dev->subordinate);
5463 pci_dev_unlock(dev);
5467 /* Return 1 on successful lock, 0 on contention */
5468 static int pci_bus_trylock(struct pci_bus *bus)
5470 struct pci_dev *dev;
5472 list_for_each_entry(dev, &bus->devices, bus_list) {
5473 if (!pci_dev_trylock(dev))
5475 if (dev->subordinate) {
5476 if (!pci_bus_trylock(dev->subordinate)) {
5477 pci_dev_unlock(dev);
5485 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5486 if (dev->subordinate)
5487 pci_bus_unlock(dev->subordinate);
5488 pci_dev_unlock(dev);
5493 /* Do any devices on or below this slot prevent a bus reset? */
5494 static bool pci_slot_resetable(struct pci_slot *slot)
5496 struct pci_dev *dev;
5498 if (slot->bus->self &&
5499 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5502 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5503 if (!dev->slot || dev->slot != slot)
5505 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5506 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5513 /* Lock devices from the top of the tree down */
5514 static void pci_slot_lock(struct pci_slot *slot)
5516 struct pci_dev *dev;
5518 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5519 if (!dev->slot || dev->slot != slot)
5522 if (dev->subordinate)
5523 pci_bus_lock(dev->subordinate);
5527 /* Unlock devices from the bottom of the tree up */
5528 static void pci_slot_unlock(struct pci_slot *slot)
5530 struct pci_dev *dev;
5532 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5533 if (!dev->slot || dev->slot != slot)
5535 if (dev->subordinate)
5536 pci_bus_unlock(dev->subordinate);
5537 pci_dev_unlock(dev);
5541 /* Return 1 on successful lock, 0 on contention */
5542 static int pci_slot_trylock(struct pci_slot *slot)
5544 struct pci_dev *dev;
5546 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5547 if (!dev->slot || dev->slot != slot)
5549 if (!pci_dev_trylock(dev))
5551 if (dev->subordinate) {
5552 if (!pci_bus_trylock(dev->subordinate)) {
5553 pci_dev_unlock(dev);
5561 list_for_each_entry_continue_reverse(dev,
5562 &slot->bus->devices, bus_list) {
5563 if (!dev->slot || dev->slot != slot)
5565 if (dev->subordinate)
5566 pci_bus_unlock(dev->subordinate);
5567 pci_dev_unlock(dev);
5573 * Save and disable devices from the top of the tree down while holding
5574 * the @dev mutex lock for the entire tree.
5576 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5578 struct pci_dev *dev;
5580 list_for_each_entry(dev, &bus->devices, bus_list) {
5581 pci_dev_save_and_disable(dev);
5582 if (dev->subordinate)
5583 pci_bus_save_and_disable_locked(dev->subordinate);
5588 * Restore devices from top of the tree down while holding @dev mutex lock
5589 * for the entire tree. Parent bridges need to be restored before we can
5590 * get to subordinate devices.
5592 static void pci_bus_restore_locked(struct pci_bus *bus)
5594 struct pci_dev *dev;
5596 list_for_each_entry(dev, &bus->devices, bus_list) {
5597 pci_dev_restore(dev);
5598 if (dev->subordinate)
5599 pci_bus_restore_locked(dev->subordinate);
5604 * Save and disable devices from the top of the tree down while holding
5605 * the @dev mutex lock for the entire tree.
5607 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5609 struct pci_dev *dev;
5611 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5612 if (!dev->slot || dev->slot != slot)
5614 pci_dev_save_and_disable(dev);
5615 if (dev->subordinate)
5616 pci_bus_save_and_disable_locked(dev->subordinate);
5621 * Restore devices from top of the tree down while holding @dev mutex lock
5622 * for the entire tree. Parent bridges need to be restored before we can
5623 * get to subordinate devices.
5625 static void pci_slot_restore_locked(struct pci_slot *slot)
5627 struct pci_dev *dev;
5629 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5630 if (!dev->slot || dev->slot != slot)
5632 pci_dev_restore(dev);
5633 if (dev->subordinate)
5634 pci_bus_restore_locked(dev->subordinate);
5638 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5642 if (!slot || !pci_slot_resetable(slot))
5646 pci_slot_lock(slot);
5650 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5653 pci_slot_unlock(slot);
5659 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5660 * @slot: PCI slot to probe
5662 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5664 int pci_probe_reset_slot(struct pci_slot *slot)
5666 return pci_slot_reset(slot, PCI_RESET_PROBE);
5668 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5671 * __pci_reset_slot - Try to reset a PCI slot
5672 * @slot: PCI slot to reset
5674 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5675 * independent of other slots. For instance, some slots may support slot power
5676 * control. In the case of a 1:1 bus to slot architecture, this function may
5677 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5678 * Generally a slot reset should be attempted before a bus reset. All of the
5679 * function of the slot and any subordinate buses behind the slot are reset
5680 * through this function. PCI config space of all devices in the slot and
5681 * behind the slot is saved before and restored after reset.
5683 * Same as above except return -EAGAIN if the slot cannot be locked
5685 static int __pci_reset_slot(struct pci_slot *slot)
5689 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5693 if (pci_slot_trylock(slot)) {
5694 pci_slot_save_and_disable_locked(slot);
5696 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5697 pci_slot_restore_locked(slot);
5698 pci_slot_unlock(slot);
5705 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5709 if (!bus->self || !pci_bus_resetable(bus))
5719 ret = pci_bridge_secondary_bus_reset(bus->self);
5721 pci_bus_unlock(bus);
5727 * pci_bus_error_reset - reset the bridge's subordinate bus
5728 * @bridge: The parent device that connects to the bus to reset
5730 * This function will first try to reset the slots on this bus if the method is
5731 * available. If slot reset fails or is not available, this will fall back to a
5732 * secondary bus reset.
5734 int pci_bus_error_reset(struct pci_dev *bridge)
5736 struct pci_bus *bus = bridge->subordinate;
5737 struct pci_slot *slot;
5742 mutex_lock(&pci_slot_mutex);
5743 if (list_empty(&bus->slots))
5746 list_for_each_entry(slot, &bus->slots, list)
5747 if (pci_probe_reset_slot(slot))
5750 list_for_each_entry(slot, &bus->slots, list)
5751 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5754 mutex_unlock(&pci_slot_mutex);
5757 mutex_unlock(&pci_slot_mutex);
5758 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5762 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5763 * @bus: PCI bus to probe
5765 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5767 int pci_probe_reset_bus(struct pci_bus *bus)
5769 return pci_bus_reset(bus, PCI_RESET_PROBE);
5771 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5774 * __pci_reset_bus - Try to reset a PCI bus
5775 * @bus: top level PCI bus to reset
5777 * Same as above except return -EAGAIN if the bus cannot be locked
5779 static int __pci_reset_bus(struct pci_bus *bus)
5783 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5787 if (pci_bus_trylock(bus)) {
5788 pci_bus_save_and_disable_locked(bus);
5790 rc = pci_bridge_secondary_bus_reset(bus->self);
5791 pci_bus_restore_locked(bus);
5792 pci_bus_unlock(bus);
5800 * pci_reset_bus - Try to reset a PCI bus
5801 * @pdev: top level PCI device to reset via slot/bus
5803 * Same as above except return -EAGAIN if the bus cannot be locked
5805 int pci_reset_bus(struct pci_dev *pdev)
5807 return (!pci_probe_reset_slot(pdev->slot)) ?
5808 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5810 EXPORT_SYMBOL_GPL(pci_reset_bus);
5813 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5814 * @dev: PCI device to query
5816 * Returns mmrbc: maximum designed memory read count in bytes or
5817 * appropriate error value.
5819 int pcix_get_max_mmrbc(struct pci_dev *dev)
5824 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5828 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5831 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5833 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5836 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5837 * @dev: PCI device to query
5839 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5842 int pcix_get_mmrbc(struct pci_dev *dev)
5847 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5851 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5854 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5856 EXPORT_SYMBOL(pcix_get_mmrbc);
5859 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5860 * @dev: PCI device to query
5861 * @mmrbc: maximum memory read count in bytes
5862 * valid values are 512, 1024, 2048, 4096
5864 * If possible sets maximum memory read byte count, some bridges have errata
5865 * that prevent this.
5867 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5873 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5876 v = ffs(mmrbc) - 10;
5878 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5882 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5885 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5888 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5891 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5893 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5896 cmd &= ~PCI_X_CMD_MAX_READ;
5898 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5903 EXPORT_SYMBOL(pcix_set_mmrbc);
5906 * pcie_get_readrq - get PCI Express read request size
5907 * @dev: PCI device to query
5909 * Returns maximum memory read request in bytes or appropriate error value.
5911 int pcie_get_readrq(struct pci_dev *dev)
5915 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5917 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5919 EXPORT_SYMBOL(pcie_get_readrq);
5922 * pcie_set_readrq - set PCI Express maximum memory read request
5923 * @dev: PCI device to query
5924 * @rq: maximum memory read count in bytes
5925 * valid values are 128, 256, 512, 1024, 2048, 4096
5927 * If possible sets maximum memory read request in bytes
5929 int pcie_set_readrq(struct pci_dev *dev, int rq)
5934 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5938 * If using the "performance" PCIe config, we clamp the read rq
5939 * size to the max packet size to keep the host bridge from
5940 * generating requests larger than we can cope with.
5942 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5943 int mps = pcie_get_mps(dev);
5949 v = (ffs(rq) - 8) << 12;
5951 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5952 PCI_EXP_DEVCTL_READRQ, v);
5954 return pcibios_err_to_errno(ret);
5956 EXPORT_SYMBOL(pcie_set_readrq);
5959 * pcie_get_mps - get PCI Express maximum payload size
5960 * @dev: PCI device to query
5962 * Returns maximum payload size in bytes
5964 int pcie_get_mps(struct pci_dev *dev)
5968 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5970 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5972 EXPORT_SYMBOL(pcie_get_mps);
5975 * pcie_set_mps - set PCI Express maximum payload size
5976 * @dev: PCI device to query
5977 * @mps: maximum payload size in bytes
5978 * valid values are 128, 256, 512, 1024, 2048, 4096
5980 * If possible sets maximum payload size
5982 int pcie_set_mps(struct pci_dev *dev, int mps)
5987 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5991 if (v > dev->pcie_mpss)
5995 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5996 PCI_EXP_DEVCTL_PAYLOAD, v);
5998 return pcibios_err_to_errno(ret);
6000 EXPORT_SYMBOL(pcie_set_mps);
6003 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6004 * device and its bandwidth limitation
6005 * @dev: PCI device to query
6006 * @limiting_dev: storage for device causing the bandwidth limitation
6007 * @speed: storage for speed of limiting device
6008 * @width: storage for width of limiting device
6010 * Walk up the PCI device chain and find the point where the minimum
6011 * bandwidth is available. Return the bandwidth available there and (if
6012 * limiting_dev, speed, and width pointers are supplied) information about
6013 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6016 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6017 enum pci_bus_speed *speed,
6018 enum pcie_link_width *width)
6021 enum pci_bus_speed next_speed;
6022 enum pcie_link_width next_width;
6026 *speed = PCI_SPEED_UNKNOWN;
6028 *width = PCIE_LNK_WIDTH_UNKNOWN;
6033 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6035 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6036 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6037 PCI_EXP_LNKSTA_NLW_SHIFT;
6039 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6041 /* Check if current device limits the total bandwidth */
6042 if (!bw || next_bw <= bw) {
6046 *limiting_dev = dev;
6048 *speed = next_speed;
6050 *width = next_width;
6053 dev = pci_upstream_bridge(dev);
6058 EXPORT_SYMBOL(pcie_bandwidth_available);
6061 * pcie_get_speed_cap - query for the PCI device's link speed capability
6062 * @dev: PCI device to query
6064 * Query the PCI device speed capability. Return the maximum link speed
6065 * supported by the device.
6067 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6069 u32 lnkcap2, lnkcap;
6072 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6073 * implementation note there recommends using the Supported Link
6074 * Speeds Vector in Link Capabilities 2 when supported.
6076 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6077 * should use the Supported Link Speeds field in Link Capabilities,
6078 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6080 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6082 /* PCIe r3.0-compliant */
6084 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6086 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6087 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6088 return PCIE_SPEED_5_0GT;
6089 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6090 return PCIE_SPEED_2_5GT;
6092 return PCI_SPEED_UNKNOWN;
6094 EXPORT_SYMBOL(pcie_get_speed_cap);
6097 * pcie_get_width_cap - query for the PCI device's link width capability
6098 * @dev: PCI device to query
6100 * Query the PCI device width capability. Return the maximum link width
6101 * supported by the device.
6103 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6107 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6109 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6111 return PCIE_LNK_WIDTH_UNKNOWN;
6113 EXPORT_SYMBOL(pcie_get_width_cap);
6116 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6118 * @speed: storage for link speed
6119 * @width: storage for link width
6121 * Calculate a PCI device's link bandwidth by querying for its link speed
6122 * and width, multiplying them, and applying encoding overhead. The result
6123 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6125 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6126 enum pcie_link_width *width)
6128 *speed = pcie_get_speed_cap(dev);
6129 *width = pcie_get_width_cap(dev);
6131 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6134 return *width * PCIE_SPEED2MBS_ENC(*speed);
6138 * __pcie_print_link_status - Report the PCI device's link speed and width
6139 * @dev: PCI device to query
6140 * @verbose: Print info even when enough bandwidth is available
6142 * If the available bandwidth at the device is less than the device is
6143 * capable of, report the device's maximum possible bandwidth and the
6144 * upstream link that limits its performance. If @verbose, always print
6145 * the available bandwidth, even if the device isn't constrained.
6147 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6149 enum pcie_link_width width, width_cap;
6150 enum pci_bus_speed speed, speed_cap;
6151 struct pci_dev *limiting_dev = NULL;
6152 u32 bw_avail, bw_cap;
6154 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6155 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6157 if (bw_avail >= bw_cap && verbose)
6158 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6159 bw_cap / 1000, bw_cap % 1000,
6160 pci_speed_string(speed_cap), width_cap);
6161 else if (bw_avail < bw_cap)
6162 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6163 bw_avail / 1000, bw_avail % 1000,
6164 pci_speed_string(speed), width,
6165 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6166 bw_cap / 1000, bw_cap % 1000,
6167 pci_speed_string(speed_cap), width_cap);
6171 * pcie_print_link_status - Report the PCI device's link speed and width
6172 * @dev: PCI device to query
6174 * Report the available bandwidth at the device.
6176 void pcie_print_link_status(struct pci_dev *dev)
6178 __pcie_print_link_status(dev, true);
6180 EXPORT_SYMBOL(pcie_print_link_status);
6183 * pci_select_bars - Make BAR mask from the type of resource
6184 * @dev: the PCI device for which BAR mask is made
6185 * @flags: resource type mask to be selected
6187 * This helper routine makes bar mask from the type of resource.
6189 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6192 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6193 if (pci_resource_flags(dev, i) & flags)
6197 EXPORT_SYMBOL(pci_select_bars);
6199 /* Some architectures require additional programming to enable VGA */
6200 static arch_set_vga_state_t arch_set_vga_state;
6202 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6204 arch_set_vga_state = func; /* NULL disables */
6207 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6208 unsigned int command_bits, u32 flags)
6210 if (arch_set_vga_state)
6211 return arch_set_vga_state(dev, decode, command_bits,
6217 * pci_set_vga_state - set VGA decode state on device and parents if requested
6218 * @dev: the PCI device
6219 * @decode: true = enable decoding, false = disable decoding
6220 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6221 * @flags: traverse ancestors and change bridges
6222 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6224 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6225 unsigned int command_bits, u32 flags)
6227 struct pci_bus *bus;
6228 struct pci_dev *bridge;
6232 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6234 /* ARCH specific VGA enables */
6235 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6239 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6240 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6242 cmd |= command_bits;
6244 cmd &= ~command_bits;
6245 pci_write_config_word(dev, PCI_COMMAND, cmd);
6248 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6255 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6258 cmd |= PCI_BRIDGE_CTL_VGA;
6260 cmd &= ~PCI_BRIDGE_CTL_VGA;
6261 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6270 bool pci_pr3_present(struct pci_dev *pdev)
6272 struct acpi_device *adev;
6277 adev = ACPI_COMPANION(&pdev->dev);
6281 return adev->power.flags.power_resources &&
6282 acpi_has_method(adev->handle, "_PR3");
6284 EXPORT_SYMBOL_GPL(pci_pr3_present);
6288 * pci_add_dma_alias - Add a DMA devfn alias for a device
6289 * @dev: the PCI device for which alias is added
6290 * @devfn_from: alias slot and function
6291 * @nr_devfns: number of subsequent devfns to alias
6293 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6294 * which is used to program permissible bus-devfn source addresses for DMA
6295 * requests in an IOMMU. These aliases factor into IOMMU group creation
6296 * and are useful for devices generating DMA requests beyond or different
6297 * from their logical bus-devfn. Examples include device quirks where the
6298 * device simply uses the wrong devfn, as well as non-transparent bridges
6299 * where the alias may be a proxy for devices in another domain.
6301 * IOMMU group creation is performed during device discovery or addition,
6302 * prior to any potential DMA mapping and therefore prior to driver probing
6303 * (especially for userspace assigned devices where IOMMU group definition
6304 * cannot be left as a userspace activity). DMA aliases should therefore
6305 * be configured via quirks, such as the PCI fixup header quirk.
6307 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6311 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6312 devfn_to = devfn_from + nr_devfns - 1;
6314 if (!dev->dma_alias_mask)
6315 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6316 if (!dev->dma_alias_mask) {
6317 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6321 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6324 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6325 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6326 else if (nr_devfns > 1)
6327 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6328 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6329 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6332 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6334 return (dev1->dma_alias_mask &&
6335 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6336 (dev2->dma_alias_mask &&
6337 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6338 pci_real_dma_dev(dev1) == dev2 ||
6339 pci_real_dma_dev(dev2) == dev1;
6342 bool pci_device_is_present(struct pci_dev *pdev)
6346 if (pci_dev_is_disconnected(pdev))
6348 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6350 EXPORT_SYMBOL_GPL(pci_device_is_present);
6352 void pci_ignore_hotplug(struct pci_dev *dev)
6354 struct pci_dev *bridge = dev->bus->self;
6356 dev->ignore_hotplug = 1;
6357 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6359 bridge->ignore_hotplug = 1;
6361 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6364 * pci_real_dma_dev - Get PCI DMA device for PCI device
6365 * @dev: the PCI device that may have a PCI DMA alias
6367 * Permits the platform to provide architecture-specific functionality to
6368 * devices needing to alias DMA to another PCI device on another PCI bus. If
6369 * the PCI device is on the same bus, it is recommended to use
6370 * pci_add_dma_alias(). This is the default implementation. Architecture
6371 * implementations can override this.
6373 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6378 resource_size_t __weak pcibios_default_alignment(void)
6384 * Arches that don't want to expose struct resource to userland as-is in
6385 * sysfs and /proc can implement their own pci_resource_to_user().
6387 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6388 const struct resource *rsrc,
6389 resource_size_t *start, resource_size_t *end)
6391 *start = rsrc->start;
6395 static char *resource_alignment_param;
6396 static DEFINE_SPINLOCK(resource_alignment_lock);
6399 * pci_specified_resource_alignment - get resource alignment specified by user.
6400 * @dev: the PCI device to get
6401 * @resize: whether or not to change resources' size when reassigning alignment
6403 * RETURNS: Resource alignment if it is specified.
6404 * Zero if it is not specified.
6406 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6409 int align_order, count;
6410 resource_size_t align = pcibios_default_alignment();
6414 spin_lock(&resource_alignment_lock);
6415 p = resource_alignment_param;
6418 if (pci_has_flag(PCI_PROBE_ONLY)) {
6420 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6426 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6429 if (align_order > 63) {
6430 pr_err("PCI: Invalid requested alignment (order %d)\n",
6432 align_order = PAGE_SHIFT;
6435 align_order = PAGE_SHIFT;
6438 ret = pci_dev_str_match(dev, p, &p);
6441 align = 1ULL << align_order;
6443 } else if (ret < 0) {
6444 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6449 if (*p != ';' && *p != ',') {
6450 /* End of param or invalid format */
6456 spin_unlock(&resource_alignment_lock);
6460 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6461 resource_size_t align, bool resize)
6463 struct resource *r = &dev->resource[bar];
6464 resource_size_t size;
6466 if (!(r->flags & IORESOURCE_MEM))
6469 if (r->flags & IORESOURCE_PCI_FIXED) {
6470 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6471 bar, r, (unsigned long long)align);
6475 size = resource_size(r);
6480 * Increase the alignment of the resource. There are two ways we
6483 * 1) Increase the size of the resource. BARs are aligned on their
6484 * size, so when we reallocate space for this resource, we'll
6485 * allocate it with the larger alignment. This also prevents
6486 * assignment of any other BARs inside the alignment region, so
6487 * if we're requesting page alignment, this means no other BARs
6488 * will share the page.
6490 * The disadvantage is that this makes the resource larger than
6491 * the hardware BAR, which may break drivers that compute things
6492 * based on the resource size, e.g., to find registers at a
6493 * fixed offset before the end of the BAR.
6495 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6496 * set r->start to the desired alignment. By itself this
6497 * doesn't prevent other BARs being put inside the alignment
6498 * region, but if we realign *every* resource of every device in
6499 * the system, none of them will share an alignment region.
6501 * When the user has requested alignment for only some devices via
6502 * the "pci=resource_alignment" argument, "resize" is true and we
6503 * use the first method. Otherwise we assume we're aligning all
6504 * devices and we use the second.
6507 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6508 bar, r, (unsigned long long)align);
6514 r->flags &= ~IORESOURCE_SIZEALIGN;
6515 r->flags |= IORESOURCE_STARTALIGN;
6517 r->end = r->start + size - 1;
6519 r->flags |= IORESOURCE_UNSET;
6523 * This function disables memory decoding and releases memory resources
6524 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6525 * It also rounds up size to specified alignment.
6526 * Later on, the kernel will assign page-aligned memory resource back
6529 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6533 resource_size_t align;
6535 bool resize = false;
6538 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6539 * 3.4.1.11. Their resources are allocated from the space
6540 * described by the VF BARx register in the PF's SR-IOV capability.
6541 * We can't influence their alignment here.
6546 /* check if specified PCI is target device to reassign */
6547 align = pci_specified_resource_alignment(dev, &resize);
6551 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6552 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6553 pci_warn(dev, "Can't reassign resources to host bridge\n");
6557 pci_read_config_word(dev, PCI_COMMAND, &command);
6558 command &= ~PCI_COMMAND_MEMORY;
6559 pci_write_config_word(dev, PCI_COMMAND, command);
6561 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6562 pci_request_resource_alignment(dev, i, align, resize);
6565 * Need to disable bridge's resource window,
6566 * to enable the kernel to reassign new resource
6569 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6570 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6571 r = &dev->resource[i];
6572 if (!(r->flags & IORESOURCE_MEM))
6574 r->flags |= IORESOURCE_UNSET;
6575 r->end = resource_size(r) - 1;
6578 pci_disable_bridge_window(dev);
6582 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6586 spin_lock(&resource_alignment_lock);
6587 if (resource_alignment_param)
6588 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6589 spin_unlock(&resource_alignment_lock);
6594 static ssize_t resource_alignment_store(struct bus_type *bus,
6595 const char *buf, size_t count)
6597 char *param, *old, *end;
6599 if (count >= (PAGE_SIZE - 1))
6602 param = kstrndup(buf, count, GFP_KERNEL);
6606 end = strchr(param, '\n');
6610 spin_lock(&resource_alignment_lock);
6611 old = resource_alignment_param;
6612 if (strlen(param)) {
6613 resource_alignment_param = param;
6616 resource_alignment_param = NULL;
6618 spin_unlock(&resource_alignment_lock);
6625 static BUS_ATTR_RW(resource_alignment);
6627 static int __init pci_resource_alignment_sysfs_init(void)
6629 return bus_create_file(&pci_bus_type,
6630 &bus_attr_resource_alignment);
6632 late_initcall(pci_resource_alignment_sysfs_init);
6634 static void pci_no_domains(void)
6636 #ifdef CONFIG_PCI_DOMAINS
6637 pci_domains_supported = 0;
6641 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6642 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6644 static int pci_get_new_domain_nr(void)
6646 return atomic_inc_return(&__domain_nr);
6649 static int of_pci_bus_find_domain_nr(struct device *parent)
6651 static int use_dt_domains = -1;
6655 domain = of_get_pci_domain_nr(parent->of_node);
6658 * Check DT domain and use_dt_domains values.
6660 * If DT domain property is valid (domain >= 0) and
6661 * use_dt_domains != 0, the DT assignment is valid since this means
6662 * we have not previously allocated a domain number by using
6663 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6664 * 1, to indicate that we have just assigned a domain number from
6667 * If DT domain property value is not valid (ie domain < 0), and we
6668 * have not previously assigned a domain number from DT
6669 * (use_dt_domains != 1) we should assign a domain number by
6672 * pci_get_new_domain_nr()
6674 * API and update the use_dt_domains value to keep track of method we
6675 * are using to assign domain numbers (use_dt_domains = 0).
6677 * All other combinations imply we have a platform that is trying
6678 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6679 * which is a recipe for domain mishandling and it is prevented by
6680 * invalidating the domain value (domain = -1) and printing a
6681 * corresponding error.
6683 if (domain >= 0 && use_dt_domains) {
6685 } else if (domain < 0 && use_dt_domains != 1) {
6687 domain = pci_get_new_domain_nr();
6690 pr_err("Node %pOF has ", parent->of_node);
6691 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6698 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6700 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6701 acpi_pci_bus_find_domain_nr(bus);
6706 * pci_ext_cfg_avail - can we access extended PCI config space?
6708 * Returns 1 if we can access PCI extended config space (offsets
6709 * greater than 0xff). This is the default implementation. Architecture
6710 * implementations can override this.
6712 int __weak pci_ext_cfg_avail(void)
6717 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6720 EXPORT_SYMBOL(pci_fixup_cardbus);
6722 static int __init pci_setup(char *str)
6725 char *k = strchr(str, ',');
6728 if (*str && (str = pcibios_setup(str)) && *str) {
6729 if (!strcmp(str, "nomsi")) {
6731 } else if (!strncmp(str, "noats", 5)) {
6732 pr_info("PCIe: ATS is disabled\n");
6733 pcie_ats_disabled = true;
6734 } else if (!strcmp(str, "noaer")) {
6736 } else if (!strcmp(str, "earlydump")) {
6737 pci_early_dump = true;
6738 } else if (!strncmp(str, "realloc=", 8)) {
6739 pci_realloc_get_opt(str + 8);
6740 } else if (!strncmp(str, "realloc", 7)) {
6741 pci_realloc_get_opt("on");
6742 } else if (!strcmp(str, "nodomains")) {
6744 } else if (!strncmp(str, "noari", 5)) {
6745 pcie_ari_disabled = true;
6746 } else if (!strncmp(str, "cbiosize=", 9)) {
6747 pci_cardbus_io_size = memparse(str + 9, &str);
6748 } else if (!strncmp(str, "cbmemsize=", 10)) {
6749 pci_cardbus_mem_size = memparse(str + 10, &str);
6750 } else if (!strncmp(str, "resource_alignment=", 19)) {
6751 resource_alignment_param = str + 19;
6752 } else if (!strncmp(str, "ecrc=", 5)) {
6753 pcie_ecrc_get_policy(str + 5);
6754 } else if (!strncmp(str, "hpiosize=", 9)) {
6755 pci_hotplug_io_size = memparse(str + 9, &str);
6756 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6757 pci_hotplug_mmio_size = memparse(str + 11, &str);
6758 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6759 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6760 } else if (!strncmp(str, "hpmemsize=", 10)) {
6761 pci_hotplug_mmio_size = memparse(str + 10, &str);
6762 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6763 } else if (!strncmp(str, "hpbussize=", 10)) {
6764 pci_hotplug_bus_size =
6765 simple_strtoul(str + 10, &str, 0);
6766 if (pci_hotplug_bus_size > 0xff)
6767 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6768 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6769 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6770 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6771 pcie_bus_config = PCIE_BUS_SAFE;
6772 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6773 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6774 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6775 pcie_bus_config = PCIE_BUS_PEER2PEER;
6776 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6777 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6778 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6779 disable_acs_redir_param = str + 18;
6781 pr_err("PCI: Unknown option `%s'\n", str);
6788 early_param("pci", pci_setup);
6791 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6792 * in pci_setup(), above, to point to data in the __initdata section which
6793 * will be freed after the init sequence is complete. We can't allocate memory
6794 * in pci_setup() because some architectures do not have any memory allocation
6795 * service available during an early_param() call. So we allocate memory and
6796 * copy the variable here before the init section is freed.
6799 static int __init pci_realloc_setup_params(void)
6801 resource_alignment_param = kstrdup(resource_alignment_param,
6803 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6807 pure_initcall(pci_realloc_setup_params);