2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm-generic/pci-bridge.h>
26 #include <asm/setup.h>
29 const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32 EXPORT_SYMBOL_GPL(pci_power_names);
34 int isa_dma_bridge_buggy;
35 EXPORT_SYMBOL(isa_dma_bridge_buggy);
38 EXPORT_SYMBOL(pci_pci_problems);
40 unsigned int pci_pm_d3_delay;
42 static void pci_pme_list_scan(struct work_struct *work);
44 static LIST_HEAD(pci_pme_list);
45 static DEFINE_MUTEX(pci_pme_list_mutex);
46 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
48 struct pci_pme_device {
49 struct list_head list;
53 #define PME_TIMEOUT 1000 /* How long between PME checks */
55 static void pci_dev_d3_sleep(struct pci_dev *dev)
57 unsigned int delay = dev->d3_delay;
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
65 #ifdef CONFIG_PCI_DOMAINS
66 int pci_domains_supported = 1;
69 #define DEFAULT_CARDBUS_IO_SIZE (256)
70 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
72 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
75 #define DEFAULT_HOTPLUG_IO_SIZE (256)
76 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
78 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
89 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
90 u8 pci_cache_line_size;
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
96 unsigned int pcibios_max_latency = 255;
98 /* If set, the PCIe ARI capability will not be used. */
99 static bool pcie_ari_disabled;
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
108 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
110 struct list_head *tmp;
111 unsigned char max, n;
113 max = bus->busn_res.end;
114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
121 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
123 #ifdef CONFIG_HAS_IOMEM
124 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
127 * Make sure the BAR is actually a memory resource, not an IO resource
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
136 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
139 #define PCI_FIND_CAP_TTL 48
141 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
142 u8 pos, int cap, int *ttl)
147 pci_bus_read_config_byte(bus, devfn, pos, &pos);
151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
157 pos += PCI_CAP_LIST_NEXT;
162 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
165 int ttl = PCI_FIND_CAP_TTL;
167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
170 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
172 return __pci_find_next_cap(dev->bus, dev->devfn,
173 pos + PCI_CAP_LIST_NEXT, cap);
175 EXPORT_SYMBOL_GPL(pci_find_next_capability);
177 static int __pci_bus_find_cap_start(struct pci_bus *bus,
178 unsigned int devfn, u8 hdr_type)
182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
183 if (!(status & PCI_STATUS_CAP_LIST))
187 case PCI_HEADER_TYPE_NORMAL:
188 case PCI_HEADER_TYPE_BRIDGE:
189 return PCI_CAPABILITY_LIST;
190 case PCI_HEADER_TYPE_CARDBUS:
191 return PCI_CB_CAPABILITY_LIST;
200 * pci_find_capability - query for devices' capabilities
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Tell if a device supports a given PCI capability.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
207 * support it. Possible values for @cap:
209 * %PCI_CAP_ID_PM Power Management
210 * %PCI_CAP_ID_AGP Accelerated Graphics Port
211 * %PCI_CAP_ID_VPD Vital Product Data
212 * %PCI_CAP_ID_SLOTID Slot Identification
213 * %PCI_CAP_ID_MSI Message Signalled Interrupts
214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
215 * %PCI_CAP_ID_PCIX PCI-X
216 * %PCI_CAP_ID_EXP PCI Express
218 int pci_find_capability(struct pci_dev *dev, int cap)
222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
230 * pci_bus_find_capability - query for devices' capabilities
231 * @bus: the PCI bus to query
232 * @devfn: PCI device to query
233 * @cap: capability code
235 * Like pci_find_capability() but works for pci devices that do not have a
236 * pci_dev structure set up yet.
238 * Returns the address of the requested capability structure within the
239 * device's PCI configuration space or 0 in case the device does not
242 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
251 pos = __pci_find_next_cap(bus, devfn, pos, cap);
257 * pci_find_next_ext_capability - Find an extended capability
258 * @dev: PCI device to query
259 * @start: address at which to start looking (0 to start at beginning of list)
260 * @cap: capability code
262 * Returns the address of the next matching extended capability structure
263 * within the device's PCI configuration space or 0 if the device does
264 * not support it. Some capabilities can occur several times, e.g., the
265 * vendor-specific capability, and this provides a way to find them all.
267 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
271 int pos = PCI_CFG_SPACE_SIZE;
273 /* minimum 8 bytes per capability */
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
286 * If we have no capabilities, this is indicated by cap ID,
287 * cap version and next pointer all being 0.
293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
296 pos = PCI_EXT_CAP_NEXT(header);
297 if (pos < PCI_CFG_SPACE_SIZE)
300 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
306 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
322 int pci_find_ext_capability(struct pci_dev *dev, int cap)
324 return pci_find_next_ext_capability(dev, 0, cap);
326 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
328 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
330 int rc, ttl = PCI_FIND_CAP_TTL;
333 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
334 mask = HT_3BIT_CAP_MASK;
336 mask = HT_5BIT_CAP_MASK;
338 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
339 PCI_CAP_ID_HT, &ttl);
341 rc = pci_read_config_byte(dev, pos + 3, &cap);
342 if (rc != PCIBIOS_SUCCESSFUL)
345 if ((cap & mask) == ht_cap)
348 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
349 pos + PCI_CAP_LIST_NEXT,
350 PCI_CAP_ID_HT, &ttl);
356 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
357 * @dev: PCI device to query
358 * @pos: Position from which to continue searching
359 * @ht_cap: Hypertransport capability code
361 * To be used in conjunction with pci_find_ht_capability() to search for
362 * all capabilities matching @ht_cap. @pos should always be a value returned
363 * from pci_find_ht_capability().
365 * NB. To be 100% safe against broken PCI devices, the caller should take
366 * steps to avoid an infinite loop.
368 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
370 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
372 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
375 * pci_find_ht_capability - query a device's Hypertransport capabilities
376 * @dev: PCI device to query
377 * @ht_cap: Hypertransport capability code
379 * Tell if a device supports a given Hypertransport capability.
380 * Returns an address within the device's PCI configuration space
381 * or 0 in case the device does not support the request capability.
382 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
383 * which has a Hypertransport capability matching @ht_cap.
385 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
389 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
391 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
395 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
398 * pci_find_parent_resource - return resource region of parent bus of given region
399 * @dev: PCI device structure contains resources to be searched
400 * @res: child resource record for which parent is sought
402 * For given resource region of given device, return the resource
403 * region of parent bus the given region is contained in or where
404 * it should be allocated from.
407 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
409 const struct pci_bus *bus = dev->bus;
411 struct resource *best = NULL, *r;
413 pci_bus_for_each_resource(bus, r, i) {
416 if (res->start && !(res->start >= r->start && res->end <= r->end))
417 continue; /* Not contained */
418 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
419 continue; /* Wrong type */
420 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
421 return r; /* Exact match */
422 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
423 if (r->flags & IORESOURCE_PREFETCH)
425 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
433 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
434 * @dev: PCI device to have its BARs restored
436 * Restore the BAR values for a given device, so as to make it
437 * accessible by its driver.
440 pci_restore_bars(struct pci_dev *dev)
444 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
445 pci_update_resource(dev, i);
448 static struct pci_platform_pm_ops *pci_platform_pm;
450 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
452 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
453 || !ops->sleep_wake || !ops->can_wakeup)
455 pci_platform_pm = ops;
459 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
461 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
464 static inline int platform_pci_set_power_state(struct pci_dev *dev,
467 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
470 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
472 return pci_platform_pm ?
473 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
476 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
478 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
481 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
483 return pci_platform_pm ?
484 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
487 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
489 return pci_platform_pm ?
490 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
494 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
496 * @dev: PCI device to handle.
497 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
500 * -EINVAL if the requested state is invalid.
501 * -EIO if device does not support PCI PM or its PM capabilities register has a
502 * wrong version, or device doesn't support the requested state.
503 * 0 if device already is in the requested state.
504 * 0 if device's power state has been successfully changed.
506 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
509 bool need_restore = false;
511 /* Check if we're already there */
512 if (dev->current_state == state)
518 if (state < PCI_D0 || state > PCI_D3hot)
521 /* Validate current state:
522 * Can enter D0 from any state, but if we can only go deeper
523 * to sleep if we're already in a low power state
525 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
526 && dev->current_state > state) {
527 dev_err(&dev->dev, "invalid power transition "
528 "(from state %d to %d)\n", dev->current_state, state);
532 /* check if this device supports the desired state */
533 if ((state == PCI_D1 && !dev->d1_support)
534 || (state == PCI_D2 && !dev->d2_support))
537 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
539 /* If we're (effectively) in D3, force entire word to 0.
540 * This doesn't affect PME_Status, disables PME_En, and
541 * sets PowerState to 0.
543 switch (dev->current_state) {
547 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
552 case PCI_UNKNOWN: /* Boot-up */
553 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
554 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
556 /* Fall-through: force to D0 */
562 /* enter specified state */
563 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
565 /* Mandatory power management transition delays */
566 /* see PCI PM 1.1 5.6.1 table 18 */
567 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
568 pci_dev_d3_sleep(dev);
569 else if (state == PCI_D2 || dev->current_state == PCI_D2)
570 udelay(PCI_PM_D2_DELAY);
572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
573 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
574 if (dev->current_state != state && printk_ratelimit())
575 dev_info(&dev->dev, "Refused to change power state, "
576 "currently in D%d\n", dev->current_state);
579 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
580 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
581 * from D3hot to D0 _may_ perform an internal reset, thereby
582 * going to "D0 Uninitialized" rather than "D0 Initialized".
583 * For example, at least some versions of the 3c905B and the
584 * 3c556B exhibit this behaviour.
586 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
587 * devices in a D3hot state at boot. Consequently, we need to
588 * restore at least the BARs so that the device will be
589 * accessible to its driver.
592 pci_restore_bars(dev);
595 pcie_aspm_pm_state_change(dev->bus->self);
601 * pci_update_current_state - Read PCI power state of given device from its
602 * PCI PM registers and cache it
603 * @dev: PCI device to handle.
604 * @state: State to cache in case the device doesn't have the PM capability
606 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
612 * Configuration space is not accessible for device in
613 * D3cold, so just keep or set D3cold for safety
615 if (dev->current_state == PCI_D3cold)
617 if (state == PCI_D3cold) {
618 dev->current_state = PCI_D3cold;
621 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
622 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
624 dev->current_state = state;
629 * pci_power_up - Put the given device into D0 forcibly
630 * @dev: PCI device to power up
632 void pci_power_up(struct pci_dev *dev)
634 if (platform_pci_power_manageable(dev))
635 platform_pci_set_power_state(dev, PCI_D0);
637 pci_raw_set_power_state(dev, PCI_D0);
638 pci_update_current_state(dev, PCI_D0);
642 * pci_platform_power_transition - Use platform to change device power state
643 * @dev: PCI device to handle.
644 * @state: State to put the device into.
646 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
650 if (platform_pci_power_manageable(dev)) {
651 error = platform_pci_set_power_state(dev, state);
653 pci_update_current_state(dev, state);
654 /* Fall back to PCI_D0 if native PM is not supported */
656 dev->current_state = PCI_D0;
659 /* Fall back to PCI_D0 if native PM is not supported */
661 dev->current_state = PCI_D0;
668 * __pci_start_power_transition - Start power transition of a PCI device
669 * @dev: PCI device to handle.
670 * @state: State to put the device into.
672 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
674 if (state == PCI_D0) {
675 pci_platform_power_transition(dev, PCI_D0);
677 * Mandatory power management transition delays, see
678 * PCI Express Base Specification Revision 2.0 Section
679 * 6.6.1: Conventional Reset. Do not delay for
680 * devices powered on/off by corresponding bridge,
681 * because have already delayed for the bridge.
683 if (dev->runtime_d3cold) {
684 msleep(dev->d3cold_delay);
686 * When powering on a bridge from D3cold, the
687 * whole hierarchy may be powered on into
688 * D0uninitialized state, resume them to give
689 * them a chance to suspend again
691 pci_wakeup_bus(dev->subordinate);
697 * __pci_dev_set_current_state - Set current state of a PCI device
698 * @dev: Device to handle
699 * @data: pointer to state to be set
701 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
703 pci_power_t state = *(pci_power_t *)data;
705 dev->current_state = state;
710 * __pci_bus_set_current_state - Walk given bus and set current state of devices
711 * @bus: Top bus of the subtree to walk.
712 * @state: state to be set
714 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
717 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
721 * __pci_complete_power_transition - Complete power transition of a PCI device
722 * @dev: PCI device to handle.
723 * @state: State to put the device into.
725 * This function should not be called directly by device drivers.
727 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
733 ret = pci_platform_power_transition(dev, state);
734 /* Power off the bridge may power off the whole hierarchy */
735 if (!ret && state == PCI_D3cold)
736 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
739 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
742 * pci_set_power_state - Set the power state of a PCI device
743 * @dev: PCI device to handle.
744 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
746 * Transition a device to a new power state, using the platform firmware and/or
747 * the device's PCI PM registers.
750 * -EINVAL if the requested state is invalid.
751 * -EIO if device does not support PCI PM or its PM capabilities register has a
752 * wrong version, or device doesn't support the requested state.
753 * 0 if device already is in the requested state.
754 * 0 if device's power state has been successfully changed.
756 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
760 /* bound the state we're entering */
761 if (state > PCI_D3cold)
763 else if (state < PCI_D0)
765 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
767 * If the device or the parent bridge do not support PCI PM,
768 * ignore the request if we're doing anything other than putting
769 * it into D0 (which would only happen on boot).
773 /* Check if we're already there */
774 if (dev->current_state == state)
777 __pci_start_power_transition(dev, state);
779 /* This device is quirked not to be put into D3, so
780 don't put it in D3 */
781 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
785 * To put device in D3cold, we put device into D3hot in native
786 * way, then put device into D3cold with platform ops
788 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
791 if (!__pci_complete_power_transition(dev, state))
794 * When aspm_policy is "powersave" this call ensures
795 * that ASPM is configured.
797 if (!error && dev->bus->self)
798 pcie_aspm_powersave_config_link(dev->bus->self);
804 * pci_choose_state - Choose the power state of a PCI device
805 * @dev: PCI device to be suspended
806 * @state: target sleep state for the whole system. This is the value
807 * that is passed to suspend() function.
809 * Returns PCI power state suitable for given device and given system
813 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
817 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
820 ret = platform_pci_choose_state(dev);
821 if (ret != PCI_POWER_ERROR)
824 switch (state.event) {
827 case PM_EVENT_FREEZE:
828 case PM_EVENT_PRETHAW:
829 /* REVISIT both freeze and pre-thaw "should" use D0 */
830 case PM_EVENT_SUSPEND:
831 case PM_EVENT_HIBERNATE:
834 dev_info(&dev->dev, "unrecognized suspend event %d\n",
841 EXPORT_SYMBOL(pci_choose_state);
843 #define PCI_EXP_SAVE_REGS 7
846 static struct pci_cap_saved_state *pci_find_saved_cap(
847 struct pci_dev *pci_dev, char cap)
849 struct pci_cap_saved_state *tmp;
850 struct hlist_node *pos;
852 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
853 if (tmp->cap.cap_nr == cap)
859 static int pci_save_pcie_state(struct pci_dev *dev)
862 struct pci_cap_saved_state *save_state;
865 if (!pci_is_pcie(dev))
868 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
870 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
874 cap = (u16 *)&save_state->cap.data[0];
875 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
876 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
877 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
878 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
879 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
880 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
881 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
886 static void pci_restore_pcie_state(struct pci_dev *dev)
889 struct pci_cap_saved_state *save_state;
892 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
896 cap = (u16 *)&save_state->cap.data[0];
897 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
898 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
899 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
900 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
901 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
902 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
903 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
907 static int pci_save_pcix_state(struct pci_dev *dev)
910 struct pci_cap_saved_state *save_state;
912 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
916 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
918 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
922 pci_read_config_word(dev, pos + PCI_X_CMD,
923 (u16 *)save_state->cap.data);
928 static void pci_restore_pcix_state(struct pci_dev *dev)
931 struct pci_cap_saved_state *save_state;
934 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
935 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
936 if (!save_state || pos <= 0)
938 cap = (u16 *)&save_state->cap.data[0];
940 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
945 * pci_save_state - save the PCI configuration space of a device before suspending
946 * @dev: - PCI device that we're dealing with
949 pci_save_state(struct pci_dev *dev)
952 /* XXX: 100% dword access ok here? */
953 for (i = 0; i < 16; i++)
954 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
955 dev->state_saved = true;
956 if ((i = pci_save_pcie_state(dev)) != 0)
958 if ((i = pci_save_pcix_state(dev)) != 0)
963 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
964 u32 saved_val, int retry)
968 pci_read_config_dword(pdev, offset, &val);
969 if (val == saved_val)
973 dev_dbg(&pdev->dev, "restoring config space at offset "
974 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
975 pci_write_config_dword(pdev, offset, saved_val);
979 pci_read_config_dword(pdev, offset, &val);
980 if (val == saved_val)
987 static void pci_restore_config_space_range(struct pci_dev *pdev,
988 int start, int end, int retry)
992 for (index = end; index >= start; index--)
993 pci_restore_config_dword(pdev, 4 * index,
994 pdev->saved_config_space[index],
998 static void pci_restore_config_space(struct pci_dev *pdev)
1000 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1001 pci_restore_config_space_range(pdev, 10, 15, 0);
1002 /* Restore BARs before the command register. */
1003 pci_restore_config_space_range(pdev, 4, 9, 10);
1004 pci_restore_config_space_range(pdev, 0, 3, 0);
1006 pci_restore_config_space_range(pdev, 0, 15, 0);
1011 * pci_restore_state - Restore the saved state of a PCI device
1012 * @dev: - PCI device that we're dealing with
1014 void pci_restore_state(struct pci_dev *dev)
1016 if (!dev->state_saved)
1019 /* PCI Express register must be restored first */
1020 pci_restore_pcie_state(dev);
1021 pci_restore_ats_state(dev);
1023 pci_restore_config_space(dev);
1025 pci_restore_pcix_state(dev);
1026 pci_restore_msi_state(dev);
1027 pci_restore_iov_state(dev);
1029 dev->state_saved = false;
1032 struct pci_saved_state {
1033 u32 config_space[16];
1034 struct pci_cap_saved_data cap[0];
1038 * pci_store_saved_state - Allocate and return an opaque struct containing
1039 * the device saved state.
1040 * @dev: PCI device that we're dealing with
1042 * Rerturn NULL if no state or error.
1044 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1046 struct pci_saved_state *state;
1047 struct pci_cap_saved_state *tmp;
1048 struct pci_cap_saved_data *cap;
1049 struct hlist_node *pos;
1052 if (!dev->state_saved)
1055 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1057 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1058 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1060 state = kzalloc(size, GFP_KERNEL);
1064 memcpy(state->config_space, dev->saved_config_space,
1065 sizeof(state->config_space));
1068 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1069 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1070 memcpy(cap, &tmp->cap, len);
1071 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1073 /* Empty cap_save terminates list */
1077 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1080 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1081 * @dev: PCI device that we're dealing with
1082 * @state: Saved state returned from pci_store_saved_state()
1084 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1086 struct pci_cap_saved_data *cap;
1088 dev->state_saved = false;
1093 memcpy(dev->saved_config_space, state->config_space,
1094 sizeof(state->config_space));
1098 struct pci_cap_saved_state *tmp;
1100 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1101 if (!tmp || tmp->cap.size != cap->size)
1104 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1105 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1106 sizeof(struct pci_cap_saved_data) + cap->size);
1109 dev->state_saved = true;
1112 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1115 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1116 * and free the memory allocated for it.
1117 * @dev: PCI device that we're dealing with
1118 * @state: Pointer to saved state returned from pci_store_saved_state()
1120 int pci_load_and_free_saved_state(struct pci_dev *dev,
1121 struct pci_saved_state **state)
1123 int ret = pci_load_saved_state(dev, *state);
1128 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1130 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1134 err = pci_set_power_state(dev, PCI_D0);
1135 if (err < 0 && err != -EIO)
1137 err = pcibios_enable_device(dev, bars);
1140 pci_fixup_device(pci_fixup_enable, dev);
1146 * pci_reenable_device - Resume abandoned device
1147 * @dev: PCI device to be resumed
1149 * Note this function is a backend of pci_default_resume and is not supposed
1150 * to be called by normal code, write proper resume handler and use it instead.
1152 int pci_reenable_device(struct pci_dev *dev)
1154 if (pci_is_enabled(dev))
1155 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1159 static int __pci_enable_device_flags(struct pci_dev *dev,
1160 resource_size_t flags)
1166 * Power state could be unknown at this point, either due to a fresh
1167 * boot or a device removal call. So get the current power state
1168 * so that things like MSI message writing will behave as expected
1169 * (e.g. if the device really is in D0 at enable time).
1173 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1174 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1177 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1178 return 0; /* already enabled */
1180 /* only skip sriov related */
1181 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1182 if (dev->resource[i].flags & flags)
1184 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1185 if (dev->resource[i].flags & flags)
1188 err = do_pci_enable_device(dev, bars);
1190 atomic_dec(&dev->enable_cnt);
1195 * pci_enable_device_io - Initialize a device for use with IO space
1196 * @dev: PCI device to be initialized
1198 * Initialize device before it's used by a driver. Ask low-level code
1199 * to enable I/O resources. Wake up the device if it was suspended.
1200 * Beware, this function can fail.
1202 int pci_enable_device_io(struct pci_dev *dev)
1204 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1208 * pci_enable_device_mem - Initialize a device for use with Memory space
1209 * @dev: PCI device to be initialized
1211 * Initialize device before it's used by a driver. Ask low-level code
1212 * to enable Memory resources. Wake up the device if it was suspended.
1213 * Beware, this function can fail.
1215 int pci_enable_device_mem(struct pci_dev *dev)
1217 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1221 * pci_enable_device - Initialize device before it's used by a driver.
1222 * @dev: PCI device to be initialized
1224 * Initialize device before it's used by a driver. Ask low-level code
1225 * to enable I/O and memory. Wake up the device if it was suspended.
1226 * Beware, this function can fail.
1228 * Note we don't actually enable the device many times if we call
1229 * this function repeatedly (we just increment the count).
1231 int pci_enable_device(struct pci_dev *dev)
1233 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1237 * Managed PCI resources. This manages device on/off, intx/msi/msix
1238 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1239 * there's no need to track it separately. pci_devres is initialized
1240 * when a device is enabled using managed PCI device enable interface.
1243 unsigned int enabled:1;
1244 unsigned int pinned:1;
1245 unsigned int orig_intx:1;
1246 unsigned int restore_intx:1;
1250 static void pcim_release(struct device *gendev, void *res)
1252 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1253 struct pci_devres *this = res;
1256 if (dev->msi_enabled)
1257 pci_disable_msi(dev);
1258 if (dev->msix_enabled)
1259 pci_disable_msix(dev);
1261 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1262 if (this->region_mask & (1 << i))
1263 pci_release_region(dev, i);
1265 if (this->restore_intx)
1266 pci_intx(dev, this->orig_intx);
1268 if (this->enabled && !this->pinned)
1269 pci_disable_device(dev);
1272 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1274 struct pci_devres *dr, *new_dr;
1276 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1280 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1283 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1286 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1288 if (pci_is_managed(pdev))
1289 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1294 * pcim_enable_device - Managed pci_enable_device()
1295 * @pdev: PCI device to be initialized
1297 * Managed pci_enable_device().
1299 int pcim_enable_device(struct pci_dev *pdev)
1301 struct pci_devres *dr;
1304 dr = get_pci_dr(pdev);
1310 rc = pci_enable_device(pdev);
1312 pdev->is_managed = 1;
1319 * pcim_pin_device - Pin managed PCI device
1320 * @pdev: PCI device to pin
1322 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1323 * driver detach. @pdev must have been enabled with
1324 * pcim_enable_device().
1326 void pcim_pin_device(struct pci_dev *pdev)
1328 struct pci_devres *dr;
1330 dr = find_pci_dr(pdev);
1331 WARN_ON(!dr || !dr->enabled);
1337 * pcibios_add_device - provide arch specific hooks when adding device dev
1338 * @dev: the PCI device being added
1340 * Permits the platform to provide architecture specific functionality when
1341 * devices are added. This is the default implementation. Architecture
1342 * implementations can override this.
1344 int __weak pcibios_add_device (struct pci_dev *dev)
1350 * pcibios_disable_device - disable arch specific PCI resources for device dev
1351 * @dev: the PCI device to disable
1353 * Disables architecture specific PCI resources for the device. This
1354 * is the default implementation. Architecture implementations can
1357 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1359 static void do_pci_disable_device(struct pci_dev *dev)
1363 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1364 if (pci_command & PCI_COMMAND_MASTER) {
1365 pci_command &= ~PCI_COMMAND_MASTER;
1366 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1369 pcibios_disable_device(dev);
1373 * pci_disable_enabled_device - Disable device without updating enable_cnt
1374 * @dev: PCI device to disable
1376 * NOTE: This function is a backend of PCI power management routines and is
1377 * not supposed to be called drivers.
1379 void pci_disable_enabled_device(struct pci_dev *dev)
1381 if (pci_is_enabled(dev))
1382 do_pci_disable_device(dev);
1386 * pci_disable_device - Disable PCI device after use
1387 * @dev: PCI device to be disabled
1389 * Signal to the system that the PCI device is not in use by the system
1390 * anymore. This only involves disabling PCI bus-mastering, if active.
1392 * Note we don't actually disable the device until all callers of
1393 * pci_enable_device() have called pci_disable_device().
1396 pci_disable_device(struct pci_dev *dev)
1398 struct pci_devres *dr;
1400 dr = find_pci_dr(dev);
1404 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1407 do_pci_disable_device(dev);
1409 dev->is_busmaster = 0;
1413 * pcibios_set_pcie_reset_state - set reset state for device dev
1414 * @dev: the PCIe device reset
1415 * @state: Reset state to enter into
1418 * Sets the PCIe reset state for the device. This is the default
1419 * implementation. Architecture implementations can override this.
1421 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1422 enum pcie_reset_state state)
1428 * pci_set_pcie_reset_state - set reset state for device dev
1429 * @dev: the PCIe device reset
1430 * @state: Reset state to enter into
1433 * Sets the PCI reset state for the device.
1435 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1437 return pcibios_set_pcie_reset_state(dev, state);
1441 * pci_check_pme_status - Check if given device has generated PME.
1442 * @dev: Device to check.
1444 * Check the PME status of the device and if set, clear it and clear PME enable
1445 * (if set). Return 'true' if PME status and PME enable were both set or
1446 * 'false' otherwise.
1448 bool pci_check_pme_status(struct pci_dev *dev)
1457 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1458 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1459 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1462 /* Clear PME status. */
1463 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1464 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1465 /* Disable PME to avoid interrupt flood. */
1466 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1470 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1476 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1477 * @dev: Device to handle.
1478 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1480 * Check if @dev has generated PME and queue a resume request for it in that
1483 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1485 if (pme_poll_reset && dev->pme_poll)
1486 dev->pme_poll = false;
1488 if (pci_check_pme_status(dev)) {
1489 pci_wakeup_event(dev);
1490 pm_request_resume(&dev->dev);
1496 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1497 * @bus: Top bus of the subtree to walk.
1499 void pci_pme_wakeup_bus(struct pci_bus *bus)
1502 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1506 * pci_wakeup - Wake up a PCI device
1507 * @pci_dev: Device to handle.
1508 * @ign: ignored parameter
1510 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1512 pci_wakeup_event(pci_dev);
1513 pm_request_resume(&pci_dev->dev);
1518 * pci_wakeup_bus - Walk given bus and wake up devices on it
1519 * @bus: Top bus of the subtree to walk.
1521 void pci_wakeup_bus(struct pci_bus *bus)
1524 pci_walk_bus(bus, pci_wakeup, NULL);
1528 * pci_pme_capable - check the capability of PCI device to generate PME#
1529 * @dev: PCI device to handle.
1530 * @state: PCI state from which device will issue PME#.
1532 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1537 return !!(dev->pme_support & (1 << state));
1540 static void pci_pme_list_scan(struct work_struct *work)
1542 struct pci_pme_device *pme_dev, *n;
1544 mutex_lock(&pci_pme_list_mutex);
1545 if (!list_empty(&pci_pme_list)) {
1546 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1547 if (pme_dev->dev->pme_poll) {
1548 struct pci_dev *bridge;
1550 bridge = pme_dev->dev->bus->self;
1552 * If bridge is in low power state, the
1553 * configuration space of subordinate devices
1554 * may be not accessible
1556 if (bridge && bridge->current_state != PCI_D0)
1558 pci_pme_wakeup(pme_dev->dev, NULL);
1560 list_del(&pme_dev->list);
1564 if (!list_empty(&pci_pme_list))
1565 schedule_delayed_work(&pci_pme_work,
1566 msecs_to_jiffies(PME_TIMEOUT));
1568 mutex_unlock(&pci_pme_list_mutex);
1572 * pci_pme_active - enable or disable PCI device's PME# function
1573 * @dev: PCI device to handle.
1574 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1576 * The caller must verify that the device is capable of generating PME# before
1577 * calling this function with @enable equal to 'true'.
1579 void pci_pme_active(struct pci_dev *dev, bool enable)
1586 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1587 /* Clear PME_Status by writing 1 to it and enable PME# */
1588 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1590 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1592 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1594 /* PCI (as opposed to PCIe) PME requires that the device have
1595 its PME# line hooked up correctly. Not all hardware vendors
1596 do this, so the PME never gets delivered and the device
1597 remains asleep. The easiest way around this is to
1598 periodically walk the list of suspended devices and check
1599 whether any have their PME flag set. The assumption is that
1600 we'll wake up often enough anyway that this won't be a huge
1601 hit, and the power savings from the devices will still be a
1604 if (dev->pme_poll) {
1605 struct pci_pme_device *pme_dev;
1607 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1612 mutex_lock(&pci_pme_list_mutex);
1613 list_add(&pme_dev->list, &pci_pme_list);
1614 if (list_is_singular(&pci_pme_list))
1615 schedule_delayed_work(&pci_pme_work,
1616 msecs_to_jiffies(PME_TIMEOUT));
1617 mutex_unlock(&pci_pme_list_mutex);
1619 mutex_lock(&pci_pme_list_mutex);
1620 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1621 if (pme_dev->dev == dev) {
1622 list_del(&pme_dev->list);
1627 mutex_unlock(&pci_pme_list_mutex);
1632 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1636 * __pci_enable_wake - enable PCI device as wakeup event source
1637 * @dev: PCI device affected
1638 * @state: PCI state from which device will issue wakeup events
1639 * @runtime: True if the events are to be generated at run time
1640 * @enable: True to enable event generation; false to disable
1642 * This enables the device as a wakeup event source, or disables it.
1643 * When such events involves platform-specific hooks, those hooks are
1644 * called automatically by this routine.
1646 * Devices with legacy power management (no standard PCI PM capabilities)
1647 * always require such platform hooks.
1650 * 0 is returned on success
1651 * -EINVAL is returned if device is not supposed to wake up the system
1652 * Error code depending on the platform is returned if both the platform and
1653 * the native mechanism fail to enable the generation of wake-up events
1655 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1656 bool runtime, bool enable)
1660 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1663 /* Don't do the same thing twice in a row for one device. */
1664 if (!!enable == !!dev->wakeup_prepared)
1668 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1669 * Anderson we should be doing PME# wake enable followed by ACPI wake
1670 * enable. To disable wake-up we call the platform first, for symmetry.
1676 if (pci_pme_capable(dev, state))
1677 pci_pme_active(dev, true);
1680 error = runtime ? platform_pci_run_wake(dev, true) :
1681 platform_pci_sleep_wake(dev, true);
1685 dev->wakeup_prepared = true;
1688 platform_pci_run_wake(dev, false);
1690 platform_pci_sleep_wake(dev, false);
1691 pci_pme_active(dev, false);
1692 dev->wakeup_prepared = false;
1697 EXPORT_SYMBOL(__pci_enable_wake);
1700 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1701 * @dev: PCI device to prepare
1702 * @enable: True to enable wake-up event generation; false to disable
1704 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1705 * and this function allows them to set that up cleanly - pci_enable_wake()
1706 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1707 * ordering constraints.
1709 * This function only returns error code if the device is not capable of
1710 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1711 * enable wake-up power for it.
1713 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1715 return pci_pme_capable(dev, PCI_D3cold) ?
1716 pci_enable_wake(dev, PCI_D3cold, enable) :
1717 pci_enable_wake(dev, PCI_D3hot, enable);
1721 * pci_target_state - find an appropriate low power state for a given PCI dev
1724 * Use underlying platform code to find a supported low power state for @dev.
1725 * If the platform can't manage @dev, return the deepest state from which it
1726 * can generate wake events, based on any available PME info.
1728 pci_power_t pci_target_state(struct pci_dev *dev)
1730 pci_power_t target_state = PCI_D3hot;
1732 if (platform_pci_power_manageable(dev)) {
1734 * Call the platform to choose the target state of the device
1735 * and enable wake-up from this state if supported.
1737 pci_power_t state = platform_pci_choose_state(dev);
1740 case PCI_POWER_ERROR:
1745 if (pci_no_d1d2(dev))
1748 target_state = state;
1750 } else if (!dev->pm_cap) {
1751 target_state = PCI_D0;
1752 } else if (device_may_wakeup(&dev->dev)) {
1754 * Find the deepest state from which the device can generate
1755 * wake-up events, make it the target state and enable device
1758 if (dev->pme_support) {
1760 && !(dev->pme_support & (1 << target_state)))
1765 return target_state;
1769 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1770 * @dev: Device to handle.
1772 * Choose the power state appropriate for the device depending on whether
1773 * it can wake up the system and/or is power manageable by the platform
1774 * (PCI_D3hot is the default) and put the device into that state.
1776 int pci_prepare_to_sleep(struct pci_dev *dev)
1778 pci_power_t target_state = pci_target_state(dev);
1781 if (target_state == PCI_POWER_ERROR)
1784 /* D3cold during system suspend/hibernate is not supported */
1785 if (target_state > PCI_D3hot)
1786 target_state = PCI_D3hot;
1788 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1790 error = pci_set_power_state(dev, target_state);
1793 pci_enable_wake(dev, target_state, false);
1799 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1800 * @dev: Device to handle.
1802 * Disable device's system wake-up capability and put it into D0.
1804 int pci_back_from_sleep(struct pci_dev *dev)
1806 pci_enable_wake(dev, PCI_D0, false);
1807 return pci_set_power_state(dev, PCI_D0);
1811 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1812 * @dev: PCI device being suspended.
1814 * Prepare @dev to generate wake-up events at run time and put it into a low
1817 int pci_finish_runtime_suspend(struct pci_dev *dev)
1819 pci_power_t target_state = pci_target_state(dev);
1822 if (target_state == PCI_POWER_ERROR)
1825 dev->runtime_d3cold = target_state == PCI_D3cold;
1827 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1829 error = pci_set_power_state(dev, target_state);
1832 __pci_enable_wake(dev, target_state, true, false);
1833 dev->runtime_d3cold = false;
1840 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1841 * @dev: Device to check.
1843 * Return true if the device itself is cabable of generating wake-up events
1844 * (through the platform or using the native PCIe PME) or if the device supports
1845 * PME and one of its upstream bridges can generate wake-up events.
1847 bool pci_dev_run_wake(struct pci_dev *dev)
1849 struct pci_bus *bus = dev->bus;
1851 if (device_run_wake(&dev->dev))
1854 if (!dev->pme_support)
1857 while (bus->parent) {
1858 struct pci_dev *bridge = bus->self;
1860 if (device_run_wake(&bridge->dev))
1866 /* We have reached the root bus. */
1868 return device_run_wake(bus->bridge);
1872 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1875 * pci_pm_init - Initialize PM functions of given PCI device
1876 * @dev: PCI device to handle.
1878 void pci_pm_init(struct pci_dev *dev)
1883 pm_runtime_forbid(&dev->dev);
1884 device_enable_async_suspend(&dev->dev);
1885 dev->wakeup_prepared = false;
1889 /* find PCI PM capability in list */
1890 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1893 /* Check device's ability to generate PME# */
1894 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1896 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1897 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1898 pmc & PCI_PM_CAP_VER_MASK);
1903 dev->d3_delay = PCI_PM_D3_WAIT;
1904 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1905 dev->d3cold_allowed = true;
1907 dev->d1_support = false;
1908 dev->d2_support = false;
1909 if (!pci_no_d1d2(dev)) {
1910 if (pmc & PCI_PM_CAP_D1)
1911 dev->d1_support = true;
1912 if (pmc & PCI_PM_CAP_D2)
1913 dev->d2_support = true;
1915 if (dev->d1_support || dev->d2_support)
1916 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1917 dev->d1_support ? " D1" : "",
1918 dev->d2_support ? " D2" : "");
1921 pmc &= PCI_PM_CAP_PME_MASK;
1923 dev_printk(KERN_DEBUG, &dev->dev,
1924 "PME# supported from%s%s%s%s%s\n",
1925 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1926 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1927 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1928 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1929 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1930 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1931 dev->pme_poll = true;
1933 * Make device's PM flags reflect the wake-up capability, but
1934 * let the user space enable it to wake up the system as needed.
1936 device_set_wakeup_capable(&dev->dev, true);
1937 /* Disable the PME# generation functionality */
1938 pci_pme_active(dev, false);
1940 dev->pme_support = 0;
1945 * platform_pci_wakeup_init - init platform wakeup if present
1948 * Some devices don't have PCI PM caps but can still generate wakeup
1949 * events through platform methods (like ACPI events). If @dev supports
1950 * platform wakeup events, set the device flag to indicate as much. This
1951 * may be redundant if the device also supports PCI PM caps, but double
1952 * initialization should be safe in that case.
1954 void platform_pci_wakeup_init(struct pci_dev *dev)
1956 if (!platform_pci_can_wakeup(dev))
1959 device_set_wakeup_capable(&dev->dev, true);
1960 platform_pci_sleep_wake(dev, false);
1963 static void pci_add_saved_cap(struct pci_dev *pci_dev,
1964 struct pci_cap_saved_state *new_cap)
1966 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
1970 * pci_add_save_buffer - allocate buffer for saving given capability registers
1971 * @dev: the PCI device
1972 * @cap: the capability to allocate the buffer for
1973 * @size: requested size of the buffer
1975 static int pci_add_cap_save_buffer(
1976 struct pci_dev *dev, char cap, unsigned int size)
1979 struct pci_cap_saved_state *save_state;
1981 pos = pci_find_capability(dev, cap);
1985 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1989 save_state->cap.cap_nr = cap;
1990 save_state->cap.size = size;
1991 pci_add_saved_cap(dev, save_state);
1997 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1998 * @dev: the PCI device
2000 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2004 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2005 PCI_EXP_SAVE_REGS * sizeof(u16));
2008 "unable to preallocate PCI Express save buffer\n");
2010 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2013 "unable to preallocate PCI-X save buffer\n");
2016 void pci_free_cap_save_buffers(struct pci_dev *dev)
2018 struct pci_cap_saved_state *tmp;
2019 struct hlist_node *pos, *n;
2021 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
2026 * pci_enable_ari - enable ARI forwarding if hardware support it
2027 * @dev: the PCI device
2029 void pci_enable_ari(struct pci_dev *dev)
2032 struct pci_dev *bridge;
2034 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2037 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
2040 bridge = dev->bus->self;
2044 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2045 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2048 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
2049 bridge->ari_enabled = 1;
2053 * pci_enable_ido - enable ID-based Ordering on a device
2054 * @dev: the PCI device
2055 * @type: which types of IDO to enable
2057 * Enable ID-based ordering on @dev. @type can contain the bits
2058 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2059 * which types of transactions are allowed to be re-ordered.
2061 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2065 if (type & PCI_EXP_IDO_REQUEST)
2066 ctrl |= PCI_EXP_IDO_REQ_EN;
2067 if (type & PCI_EXP_IDO_COMPLETION)
2068 ctrl |= PCI_EXP_IDO_CMP_EN;
2070 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2072 EXPORT_SYMBOL(pci_enable_ido);
2075 * pci_disable_ido - disable ID-based ordering on a device
2076 * @dev: the PCI device
2077 * @type: which types of IDO to disable
2079 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2083 if (type & PCI_EXP_IDO_REQUEST)
2084 ctrl |= PCI_EXP_IDO_REQ_EN;
2085 if (type & PCI_EXP_IDO_COMPLETION)
2086 ctrl |= PCI_EXP_IDO_CMP_EN;
2088 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2090 EXPORT_SYMBOL(pci_disable_ido);
2093 * pci_enable_obff - enable optimized buffer flush/fill
2095 * @type: type of signaling to use
2097 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2098 * signaling if possible, falling back to message signaling only if
2099 * WAKE# isn't supported. @type should indicate whether the PCIe link
2100 * be brought out of L0s or L1 to send the message. It should be either
2101 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2103 * If your device can benefit from receiving all messages, even at the
2104 * power cost of bringing the link back up from a low power state, use
2105 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2109 * Zero on success, appropriate error number on failure.
2111 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2117 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2118 if (!(cap & PCI_EXP_OBFF_MASK))
2119 return -ENOTSUPP; /* no OBFF support at all */
2121 /* Make sure the topology supports OBFF as well */
2122 if (dev->bus->self) {
2123 ret = pci_enable_obff(dev->bus->self, type);
2128 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2129 if (cap & PCI_EXP_OBFF_WAKE)
2130 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2133 case PCI_EXP_OBFF_SIGNAL_L0:
2134 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2135 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2137 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2138 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2139 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2142 WARN(1, "bad OBFF signal type\n");
2146 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2150 EXPORT_SYMBOL(pci_enable_obff);
2153 * pci_disable_obff - disable optimized buffer flush/fill
2156 * Disable OBFF on @dev.
2158 void pci_disable_obff(struct pci_dev *dev)
2160 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
2162 EXPORT_SYMBOL(pci_disable_obff);
2165 * pci_ltr_supported - check whether a device supports LTR
2169 * True if @dev supports latency tolerance reporting, false otherwise.
2171 static bool pci_ltr_supported(struct pci_dev *dev)
2175 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2177 return cap & PCI_EXP_DEVCAP2_LTR;
2181 * pci_enable_ltr - enable latency tolerance reporting
2184 * Enable LTR on @dev if possible, which means enabling it first on
2188 * Zero on success, errno on failure.
2190 int pci_enable_ltr(struct pci_dev *dev)
2194 /* Only primary function can enable/disable LTR */
2195 if (PCI_FUNC(dev->devfn) != 0)
2198 if (!pci_ltr_supported(dev))
2201 /* Enable upstream ports first */
2202 if (dev->bus->self) {
2203 ret = pci_enable_ltr(dev->bus->self);
2208 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2210 EXPORT_SYMBOL(pci_enable_ltr);
2213 * pci_disable_ltr - disable latency tolerance reporting
2216 void pci_disable_ltr(struct pci_dev *dev)
2218 /* Only primary function can enable/disable LTR */
2219 if (PCI_FUNC(dev->devfn) != 0)
2222 if (!pci_ltr_supported(dev))
2225 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2227 EXPORT_SYMBOL(pci_disable_ltr);
2229 static int __pci_ltr_scale(int *val)
2233 while (*val > 1023) {
2234 *val = (*val + 31) / 32;
2241 * pci_set_ltr - set LTR latency values
2243 * @snoop_lat_ns: snoop latency in nanoseconds
2244 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2246 * Figure out the scale and set the LTR values accordingly.
2248 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2250 int pos, ret, snoop_scale, nosnoop_scale;
2253 if (!pci_ltr_supported(dev))
2256 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2257 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2259 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2260 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2263 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2264 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2267 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2271 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2272 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2276 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2277 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2283 EXPORT_SYMBOL(pci_set_ltr);
2285 static int pci_acs_enable;
2288 * pci_request_acs - ask for ACS to be enabled if supported
2290 void pci_request_acs(void)
2296 * pci_enable_acs - enable ACS if hardware support it
2297 * @dev: the PCI device
2299 void pci_enable_acs(struct pci_dev *dev)
2305 if (!pci_acs_enable)
2308 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2312 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2313 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2315 /* Source Validation */
2316 ctrl |= (cap & PCI_ACS_SV);
2318 /* P2P Request Redirect */
2319 ctrl |= (cap & PCI_ACS_RR);
2321 /* P2P Completion Redirect */
2322 ctrl |= (cap & PCI_ACS_CR);
2324 /* Upstream Forwarding */
2325 ctrl |= (cap & PCI_ACS_UF);
2327 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2331 * pci_acs_enabled - test ACS against required flags for a given device
2332 * @pdev: device to test
2333 * @acs_flags: required PCI ACS flags
2335 * Return true if the device supports the provided flags. Automatically
2336 * filters out flags that are not implemented on multifunction devices.
2338 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2343 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2347 if (!pci_is_pcie(pdev))
2350 /* Filter out flags not applicable to multifunction */
2351 if (pdev->multifunction)
2352 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2353 PCI_ACS_EC | PCI_ACS_DT);
2355 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2356 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
2357 pdev->multifunction) {
2358 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2362 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2363 if ((ctrl & acs_flags) != acs_flags)
2371 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2372 * @start: starting downstream device
2373 * @end: ending upstream device or NULL to search to the root bus
2374 * @acs_flags: required flags
2376 * Walk up a device tree from start to end testing PCI ACS support. If
2377 * any step along the way does not support the required flags, return false.
2379 bool pci_acs_path_enabled(struct pci_dev *start,
2380 struct pci_dev *end, u16 acs_flags)
2382 struct pci_dev *pdev, *parent = start;
2387 if (!pci_acs_enabled(pdev, acs_flags))
2390 if (pci_is_root_bus(pdev->bus))
2391 return (end == NULL);
2393 parent = pdev->bus->self;
2394 } while (pdev != end);
2400 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2401 * @dev: the PCI device
2402 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2404 * Perform INTx swizzling for a device behind one level of bridge. This is
2405 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2406 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2407 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2408 * the PCI Express Base Specification, Revision 2.1)
2410 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2414 if (pci_ari_enabled(dev->bus))
2417 slot = PCI_SLOT(dev->devfn);
2419 return (((pin - 1) + slot) % 4) + 1;
2423 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2431 while (!pci_is_root_bus(dev->bus)) {
2432 pin = pci_swizzle_interrupt_pin(dev, pin);
2433 dev = dev->bus->self;
2440 * pci_common_swizzle - swizzle INTx all the way to root bridge
2441 * @dev: the PCI device
2442 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2444 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2445 * bridges all the way up to a PCI root bus.
2447 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2451 while (!pci_is_root_bus(dev->bus)) {
2452 pin = pci_swizzle_interrupt_pin(dev, pin);
2453 dev = dev->bus->self;
2456 return PCI_SLOT(dev->devfn);
2460 * pci_release_region - Release a PCI bar
2461 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2462 * @bar: BAR to release
2464 * Releases the PCI I/O and memory resources previously reserved by a
2465 * successful call to pci_request_region. Call this function only
2466 * after all use of the PCI regions has ceased.
2468 void pci_release_region(struct pci_dev *pdev, int bar)
2470 struct pci_devres *dr;
2472 if (pci_resource_len(pdev, bar) == 0)
2474 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2475 release_region(pci_resource_start(pdev, bar),
2476 pci_resource_len(pdev, bar));
2477 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2478 release_mem_region(pci_resource_start(pdev, bar),
2479 pci_resource_len(pdev, bar));
2481 dr = find_pci_dr(pdev);
2483 dr->region_mask &= ~(1 << bar);
2487 * __pci_request_region - Reserved PCI I/O and memory resource
2488 * @pdev: PCI device whose resources are to be reserved
2489 * @bar: BAR to be reserved
2490 * @res_name: Name to be associated with resource.
2491 * @exclusive: whether the region access is exclusive or not
2493 * Mark the PCI region associated with PCI device @pdev BR @bar as
2494 * being reserved by owner @res_name. Do not access any
2495 * address inside the PCI regions unless this call returns
2498 * If @exclusive is set, then the region is marked so that userspace
2499 * is explicitly not allowed to map the resource via /dev/mem or
2500 * sysfs MMIO access.
2502 * Returns 0 on success, or %EBUSY on error. A warning
2503 * message is also printed on failure.
2505 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2508 struct pci_devres *dr;
2510 if (pci_resource_len(pdev, bar) == 0)
2513 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2514 if (!request_region(pci_resource_start(pdev, bar),
2515 pci_resource_len(pdev, bar), res_name))
2518 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2519 if (!__request_mem_region(pci_resource_start(pdev, bar),
2520 pci_resource_len(pdev, bar), res_name,
2525 dr = find_pci_dr(pdev);
2527 dr->region_mask |= 1 << bar;
2532 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2533 &pdev->resource[bar]);
2538 * pci_request_region - Reserve PCI I/O and memory resource
2539 * @pdev: PCI device whose resources are to be reserved
2540 * @bar: BAR to be reserved
2541 * @res_name: Name to be associated with resource
2543 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2544 * being reserved by owner @res_name. Do not access any
2545 * address inside the PCI regions unless this call returns
2548 * Returns 0 on success, or %EBUSY on error. A warning
2549 * message is also printed on failure.
2551 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2553 return __pci_request_region(pdev, bar, res_name, 0);
2557 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2558 * @pdev: PCI device whose resources are to be reserved
2559 * @bar: BAR to be reserved
2560 * @res_name: Name to be associated with resource.
2562 * Mark the PCI region associated with PCI device @pdev BR @bar as
2563 * being reserved by owner @res_name. Do not access any
2564 * address inside the PCI regions unless this call returns
2567 * Returns 0 on success, or %EBUSY on error. A warning
2568 * message is also printed on failure.
2570 * The key difference that _exclusive makes it that userspace is
2571 * explicitly not allowed to map the resource via /dev/mem or
2574 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2576 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2579 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2580 * @pdev: PCI device whose resources were previously reserved
2581 * @bars: Bitmask of BARs to be released
2583 * Release selected PCI I/O and memory resources previously reserved.
2584 * Call this function only after all use of the PCI regions has ceased.
2586 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2590 for (i = 0; i < 6; i++)
2591 if (bars & (1 << i))
2592 pci_release_region(pdev, i);
2595 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2596 const char *res_name, int excl)
2600 for (i = 0; i < 6; i++)
2601 if (bars & (1 << i))
2602 if (__pci_request_region(pdev, i, res_name, excl))
2608 if (bars & (1 << i))
2609 pci_release_region(pdev, i);
2616 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2617 * @pdev: PCI device whose resources are to be reserved
2618 * @bars: Bitmask of BARs to be requested
2619 * @res_name: Name to be associated with resource
2621 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2622 const char *res_name)
2624 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2627 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2628 int bars, const char *res_name)
2630 return __pci_request_selected_regions(pdev, bars, res_name,
2631 IORESOURCE_EXCLUSIVE);
2635 * pci_release_regions - Release reserved PCI I/O and memory resources
2636 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2638 * Releases all PCI I/O and memory resources previously reserved by a
2639 * successful call to pci_request_regions. Call this function only
2640 * after all use of the PCI regions has ceased.
2643 void pci_release_regions(struct pci_dev *pdev)
2645 pci_release_selected_regions(pdev, (1 << 6) - 1);
2649 * pci_request_regions - Reserved PCI I/O and memory resources
2650 * @pdev: PCI device whose resources are to be reserved
2651 * @res_name: Name to be associated with resource.
2653 * Mark all PCI regions associated with PCI device @pdev as
2654 * being reserved by owner @res_name. Do not access any
2655 * address inside the PCI regions unless this call returns
2658 * Returns 0 on success, or %EBUSY on error. A warning
2659 * message is also printed on failure.
2661 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2663 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2667 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2668 * @pdev: PCI device whose resources are to be reserved
2669 * @res_name: Name to be associated with resource.
2671 * Mark all PCI regions associated with PCI device @pdev as
2672 * being reserved by owner @res_name. Do not access any
2673 * address inside the PCI regions unless this call returns
2676 * pci_request_regions_exclusive() will mark the region so that
2677 * /dev/mem and the sysfs MMIO access will not be allowed.
2679 * Returns 0 on success, or %EBUSY on error. A warning
2680 * message is also printed on failure.
2682 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2684 return pci_request_selected_regions_exclusive(pdev,
2685 ((1 << 6) - 1), res_name);
2688 static void __pci_set_master(struct pci_dev *dev, bool enable)
2692 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2694 cmd = old_cmd | PCI_COMMAND_MASTER;
2696 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2697 if (cmd != old_cmd) {
2698 dev_dbg(&dev->dev, "%s bus mastering\n",
2699 enable ? "enabling" : "disabling");
2700 pci_write_config_word(dev, PCI_COMMAND, cmd);
2702 dev->is_busmaster = enable;
2706 * pcibios_setup - process "pci=" kernel boot arguments
2707 * @str: string used to pass in "pci=" kernel boot arguments
2709 * Process kernel boot arguments. This is the default implementation.
2710 * Architecture specific implementations can override this as necessary.
2712 char * __weak __init pcibios_setup(char *str)
2718 * pcibios_set_master - enable PCI bus-mastering for device dev
2719 * @dev: the PCI device to enable
2721 * Enables PCI bus-mastering for the device. This is the default
2722 * implementation. Architecture specific implementations can override
2723 * this if necessary.
2725 void __weak pcibios_set_master(struct pci_dev *dev)
2729 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2730 if (pci_is_pcie(dev))
2733 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2735 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2736 else if (lat > pcibios_max_latency)
2737 lat = pcibios_max_latency;
2740 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2741 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2745 * pci_set_master - enables bus-mastering for device dev
2746 * @dev: the PCI device to enable
2748 * Enables bus-mastering on the device and calls pcibios_set_master()
2749 * to do the needed arch specific settings.
2751 void pci_set_master(struct pci_dev *dev)
2753 __pci_set_master(dev, true);
2754 pcibios_set_master(dev);
2758 * pci_clear_master - disables bus-mastering for device dev
2759 * @dev: the PCI device to disable
2761 void pci_clear_master(struct pci_dev *dev)
2763 __pci_set_master(dev, false);
2767 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2768 * @dev: the PCI device for which MWI is to be enabled
2770 * Helper function for pci_set_mwi.
2771 * Originally copied from drivers/net/acenic.c.
2772 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2774 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2776 int pci_set_cacheline_size(struct pci_dev *dev)
2780 if (!pci_cache_line_size)
2783 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2784 equal to or multiple of the right value. */
2785 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2786 if (cacheline_size >= pci_cache_line_size &&
2787 (cacheline_size % pci_cache_line_size) == 0)
2790 /* Write the correct value. */
2791 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2793 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2794 if (cacheline_size == pci_cache_line_size)
2797 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2798 "supported\n", pci_cache_line_size << 2);
2802 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2804 #ifdef PCI_DISABLE_MWI
2805 int pci_set_mwi(struct pci_dev *dev)
2810 int pci_try_set_mwi(struct pci_dev *dev)
2815 void pci_clear_mwi(struct pci_dev *dev)
2822 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2823 * @dev: the PCI device for which MWI is enabled
2825 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2827 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2830 pci_set_mwi(struct pci_dev *dev)
2835 rc = pci_set_cacheline_size(dev);
2839 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2840 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2841 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2842 cmd |= PCI_COMMAND_INVALIDATE;
2843 pci_write_config_word(dev, PCI_COMMAND, cmd);
2850 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2851 * @dev: the PCI device for which MWI is enabled
2853 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2854 * Callers are not required to check the return value.
2856 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2858 int pci_try_set_mwi(struct pci_dev *dev)
2860 int rc = pci_set_mwi(dev);
2865 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2866 * @dev: the PCI device to disable
2868 * Disables PCI Memory-Write-Invalidate transaction on the device
2871 pci_clear_mwi(struct pci_dev *dev)
2875 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2876 if (cmd & PCI_COMMAND_INVALIDATE) {
2877 cmd &= ~PCI_COMMAND_INVALIDATE;
2878 pci_write_config_word(dev, PCI_COMMAND, cmd);
2881 #endif /* ! PCI_DISABLE_MWI */
2884 * pci_intx - enables/disables PCI INTx for device dev
2885 * @pdev: the PCI device to operate on
2886 * @enable: boolean: whether to enable or disable PCI INTx
2888 * Enables/disables PCI INTx for device dev
2891 pci_intx(struct pci_dev *pdev, int enable)
2893 u16 pci_command, new;
2895 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2898 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2900 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2903 if (new != pci_command) {
2904 struct pci_devres *dr;
2906 pci_write_config_word(pdev, PCI_COMMAND, new);
2908 dr = find_pci_dr(pdev);
2909 if (dr && !dr->restore_intx) {
2910 dr->restore_intx = 1;
2911 dr->orig_intx = !enable;
2917 * pci_intx_mask_supported - probe for INTx masking support
2918 * @dev: the PCI device to operate on
2920 * Check if the device dev support INTx masking via the config space
2923 bool pci_intx_mask_supported(struct pci_dev *dev)
2925 bool mask_supported = false;
2928 if (dev->broken_intx_masking)
2931 pci_cfg_access_lock(dev);
2933 pci_read_config_word(dev, PCI_COMMAND, &orig);
2934 pci_write_config_word(dev, PCI_COMMAND,
2935 orig ^ PCI_COMMAND_INTX_DISABLE);
2936 pci_read_config_word(dev, PCI_COMMAND, &new);
2939 * There's no way to protect against hardware bugs or detect them
2940 * reliably, but as long as we know what the value should be, let's
2941 * go ahead and check it.
2943 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2944 dev_err(&dev->dev, "Command register changed from "
2945 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2946 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2947 mask_supported = true;
2948 pci_write_config_word(dev, PCI_COMMAND, orig);
2951 pci_cfg_access_unlock(dev);
2952 return mask_supported;
2954 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2956 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2958 struct pci_bus *bus = dev->bus;
2959 bool mask_updated = true;
2960 u32 cmd_status_dword;
2961 u16 origcmd, newcmd;
2962 unsigned long flags;
2966 * We do a single dword read to retrieve both command and status.
2967 * Document assumptions that make this possible.
2969 BUILD_BUG_ON(PCI_COMMAND % 4);
2970 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2972 raw_spin_lock_irqsave(&pci_lock, flags);
2974 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2976 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2979 * Check interrupt status register to see whether our device
2980 * triggered the interrupt (when masking) or the next IRQ is
2981 * already pending (when unmasking).
2983 if (mask != irq_pending) {
2984 mask_updated = false;
2988 origcmd = cmd_status_dword;
2989 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2991 newcmd |= PCI_COMMAND_INTX_DISABLE;
2992 if (newcmd != origcmd)
2993 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2996 raw_spin_unlock_irqrestore(&pci_lock, flags);
2998 return mask_updated;
3002 * pci_check_and_mask_intx - mask INTx on pending interrupt
3003 * @dev: the PCI device to operate on
3005 * Check if the device dev has its INTx line asserted, mask it and
3006 * return true in that case. False is returned if not interrupt was
3009 bool pci_check_and_mask_intx(struct pci_dev *dev)
3011 return pci_check_and_set_intx_mask(dev, true);
3013 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3016 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
3017 * @dev: the PCI device to operate on
3019 * Check if the device dev has its INTx line asserted, unmask it if not
3020 * and return true. False is returned and the mask remains active if
3021 * there was still an interrupt pending.
3023 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3025 return pci_check_and_set_intx_mask(dev, false);
3027 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3030 * pci_msi_off - disables any msi or msix capabilities
3031 * @dev: the PCI device to operate on
3033 * If you want to use msi see pci_enable_msi and friends.
3034 * This is a lower level primitive that allows us to disable
3035 * msi operation at the device level.
3037 void pci_msi_off(struct pci_dev *dev)
3042 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3044 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3045 control &= ~PCI_MSI_FLAGS_ENABLE;
3046 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3048 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3050 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3051 control &= ~PCI_MSIX_FLAGS_ENABLE;
3052 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3055 EXPORT_SYMBOL_GPL(pci_msi_off);
3057 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3059 return dma_set_max_seg_size(&dev->dev, size);
3061 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3063 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3065 return dma_set_seg_boundary(&dev->dev, mask);
3067 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3069 static int pcie_flr(struct pci_dev *dev, int probe)
3075 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3076 if (!(cap & PCI_EXP_DEVCAP_FLR))
3082 /* Wait for Transaction Pending bit clean */
3083 for (i = 0; i < 4; i++) {
3085 msleep((1 << (i - 1)) * 100);
3087 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3088 if (!(status & PCI_EXP_DEVSTA_TRPND))
3092 dev_err(&dev->dev, "transaction is not cleared; "
3093 "proceeding with reset anyway\n");
3096 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3103 static int pci_af_flr(struct pci_dev *dev, int probe)
3110 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3114 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3115 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3121 /* Wait for Transaction Pending bit clean */
3122 for (i = 0; i < 4; i++) {
3124 msleep((1 << (i - 1)) * 100);
3126 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3127 if (!(status & PCI_AF_STATUS_TP))
3131 dev_err(&dev->dev, "transaction is not cleared; "
3132 "proceeding with reset anyway\n");
3135 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3142 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3143 * @dev: Device to reset.
3144 * @probe: If set, only check if the device can be reset this way.
3146 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3147 * unset, it will be reinitialized internally when going from PCI_D3hot to
3148 * PCI_D0. If that's the case and the device is not in a low-power state
3149 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3151 * NOTE: This causes the caller to sleep for twice the device power transition
3152 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3153 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3154 * Moreover, only devices in D0 can be reset by this function.
3156 static int pci_pm_reset(struct pci_dev *dev, int probe)
3163 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3164 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3170 if (dev->current_state != PCI_D0)
3173 csr &= ~PCI_PM_CTRL_STATE_MASK;
3175 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3176 pci_dev_d3_sleep(dev);
3178 csr &= ~PCI_PM_CTRL_STATE_MASK;
3180 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3181 pci_dev_d3_sleep(dev);
3186 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3189 struct pci_dev *pdev;
3191 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3194 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3201 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3202 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3203 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3206 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3207 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3213 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3219 rc = pci_dev_specific_reset(dev, probe);
3223 rc = pcie_flr(dev, probe);
3227 rc = pci_af_flr(dev, probe);
3231 rc = pci_pm_reset(dev, probe);
3235 rc = pci_parent_bus_reset(dev, probe);
3240 static int pci_dev_reset(struct pci_dev *dev, int probe)
3245 pci_cfg_access_lock(dev);
3246 /* block PM suspend, driver probe, etc. */
3247 device_lock(&dev->dev);
3250 rc = __pci_dev_reset(dev, probe);
3253 device_unlock(&dev->dev);
3254 pci_cfg_access_unlock(dev);
3259 * __pci_reset_function - reset a PCI device function
3260 * @dev: PCI device to reset
3262 * Some devices allow an individual function to be reset without affecting
3263 * other functions in the same device. The PCI device must be responsive
3264 * to PCI config space in order to use this function.
3266 * The device function is presumed to be unused when this function is called.
3267 * Resetting the device will make the contents of PCI configuration space
3268 * random, so any caller of this must be prepared to reinitialise the
3269 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3272 * Returns 0 if the device function was successfully reset or negative if the
3273 * device doesn't support resetting a single function.
3275 int __pci_reset_function(struct pci_dev *dev)
3277 return pci_dev_reset(dev, 0);
3279 EXPORT_SYMBOL_GPL(__pci_reset_function);
3282 * __pci_reset_function_locked - reset a PCI device function while holding
3283 * the @dev mutex lock.
3284 * @dev: PCI device to reset
3286 * Some devices allow an individual function to be reset without affecting
3287 * other functions in the same device. The PCI device must be responsive
3288 * to PCI config space in order to use this function.
3290 * The device function is presumed to be unused and the caller is holding
3291 * the device mutex lock when this function is called.
3292 * Resetting the device will make the contents of PCI configuration space
3293 * random, so any caller of this must be prepared to reinitialise the
3294 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3297 * Returns 0 if the device function was successfully reset or negative if the
3298 * device doesn't support resetting a single function.
3300 int __pci_reset_function_locked(struct pci_dev *dev)
3302 return __pci_dev_reset(dev, 0);
3304 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3307 * pci_probe_reset_function - check whether the device can be safely reset
3308 * @dev: PCI device to reset
3310 * Some devices allow an individual function to be reset without affecting
3311 * other functions in the same device. The PCI device must be responsive
3312 * to PCI config space in order to use this function.
3314 * Returns 0 if the device function can be reset or negative if the
3315 * device doesn't support resetting a single function.
3317 int pci_probe_reset_function(struct pci_dev *dev)
3319 return pci_dev_reset(dev, 1);
3323 * pci_reset_function - quiesce and reset a PCI device function
3324 * @dev: PCI device to reset
3326 * Some devices allow an individual function to be reset without affecting
3327 * other functions in the same device. The PCI device must be responsive
3328 * to PCI config space in order to use this function.
3330 * This function does not just reset the PCI portion of a device, but
3331 * clears all the state associated with the device. This function differs
3332 * from __pci_reset_function in that it saves and restores device state
3335 * Returns 0 if the device function was successfully reset or negative if the
3336 * device doesn't support resetting a single function.
3338 int pci_reset_function(struct pci_dev *dev)
3342 rc = pci_dev_reset(dev, 1);
3346 pci_save_state(dev);
3349 * both INTx and MSI are disabled after the Interrupt Disable bit
3350 * is set and the Bus Master bit is cleared.
3352 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3354 rc = pci_dev_reset(dev, 0);
3356 pci_restore_state(dev);
3360 EXPORT_SYMBOL_GPL(pci_reset_function);
3363 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3364 * @dev: PCI device to query
3366 * Returns mmrbc: maximum designed memory read count in bytes
3367 * or appropriate error value.
3369 int pcix_get_max_mmrbc(struct pci_dev *dev)
3374 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3378 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3381 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3383 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3386 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3387 * @dev: PCI device to query
3389 * Returns mmrbc: maximum memory read count in bytes
3390 * or appropriate error value.
3392 int pcix_get_mmrbc(struct pci_dev *dev)
3397 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3401 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3404 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3406 EXPORT_SYMBOL(pcix_get_mmrbc);
3409 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3410 * @dev: PCI device to query
3411 * @mmrbc: maximum memory read count in bytes
3412 * valid values are 512, 1024, 2048, 4096
3414 * If possible sets maximum memory read byte count, some bridges have erratas
3415 * that prevent this.
3417 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3423 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3426 v = ffs(mmrbc) - 10;
3428 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3432 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3435 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3438 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3441 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3443 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3446 cmd &= ~PCI_X_CMD_MAX_READ;
3448 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3453 EXPORT_SYMBOL(pcix_set_mmrbc);
3456 * pcie_get_readrq - get PCI Express read request size
3457 * @dev: PCI device to query
3459 * Returns maximum memory read request in bytes
3460 * or appropriate error value.
3462 int pcie_get_readrq(struct pci_dev *dev)
3466 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3468 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3470 EXPORT_SYMBOL(pcie_get_readrq);
3473 * pcie_set_readrq - set PCI Express maximum memory read request
3474 * @dev: PCI device to query
3475 * @rq: maximum memory read count in bytes
3476 * valid values are 128, 256, 512, 1024, 2048, 4096
3478 * If possible sets maximum memory read request in bytes
3480 int pcie_set_readrq(struct pci_dev *dev, int rq)
3484 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3488 * If using the "performance" PCIe config, we clamp the
3489 * read rq size to the max packet size to prevent the
3490 * host bridge generating requests larger than we can
3493 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3494 int mps = pcie_get_mps(dev);
3502 v = (ffs(rq) - 8) << 12;
3504 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3505 PCI_EXP_DEVCTL_READRQ, v);
3507 EXPORT_SYMBOL(pcie_set_readrq);
3510 * pcie_get_mps - get PCI Express maximum payload size
3511 * @dev: PCI device to query
3513 * Returns maximum payload size in bytes
3514 * or appropriate error value.
3516 int pcie_get_mps(struct pci_dev *dev)
3520 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3522 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3526 * pcie_set_mps - set PCI Express maximum payload size
3527 * @dev: PCI device to query
3528 * @mps: maximum payload size in bytes
3529 * valid values are 128, 256, 512, 1024, 2048, 4096
3531 * If possible sets maximum payload size
3533 int pcie_set_mps(struct pci_dev *dev, int mps)
3537 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3541 if (v > dev->pcie_mpss)
3545 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3546 PCI_EXP_DEVCTL_PAYLOAD, v);
3550 * pci_select_bars - Make BAR mask from the type of resource
3551 * @dev: the PCI device for which BAR mask is made
3552 * @flags: resource type mask to be selected
3554 * This helper routine makes bar mask from the type of resource.
3556 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3559 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3560 if (pci_resource_flags(dev, i) & flags)
3566 * pci_resource_bar - get position of the BAR associated with a resource
3567 * @dev: the PCI device
3568 * @resno: the resource number
3569 * @type: the BAR type to be filled in
3571 * Returns BAR position in config space, or 0 if the BAR is invalid.
3573 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3577 if (resno < PCI_ROM_RESOURCE) {
3578 *type = pci_bar_unknown;
3579 return PCI_BASE_ADDRESS_0 + 4 * resno;
3580 } else if (resno == PCI_ROM_RESOURCE) {
3581 *type = pci_bar_mem32;
3582 return dev->rom_base_reg;
3583 } else if (resno < PCI_BRIDGE_RESOURCES) {
3584 /* device specific resource */
3585 reg = pci_iov_resource_bar(dev, resno, type);
3590 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3594 /* Some architectures require additional programming to enable VGA */
3595 static arch_set_vga_state_t arch_set_vga_state;
3597 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3599 arch_set_vga_state = func; /* NULL disables */
3602 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3603 unsigned int command_bits, u32 flags)
3605 if (arch_set_vga_state)
3606 return arch_set_vga_state(dev, decode, command_bits,
3612 * pci_set_vga_state - set VGA decode state on device and parents if requested
3613 * @dev: the PCI device
3614 * @decode: true = enable decoding, false = disable decoding
3615 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3616 * @flags: traverse ancestors and change bridges
3617 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3619 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3620 unsigned int command_bits, u32 flags)
3622 struct pci_bus *bus;
3623 struct pci_dev *bridge;
3627 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3629 /* ARCH specific VGA enables */
3630 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3634 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3635 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3637 cmd |= command_bits;
3639 cmd &= ~command_bits;
3640 pci_write_config_word(dev, PCI_COMMAND, cmd);
3643 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3650 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3653 cmd |= PCI_BRIDGE_CTL_VGA;
3655 cmd &= ~PCI_BRIDGE_CTL_VGA;
3656 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3664 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3665 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3666 static DEFINE_SPINLOCK(resource_alignment_lock);
3669 * pci_specified_resource_alignment - get resource alignment specified by user.
3670 * @dev: the PCI device to get
3672 * RETURNS: Resource alignment if it is specified.
3673 * Zero if it is not specified.
3675 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3677 int seg, bus, slot, func, align_order, count;
3678 resource_size_t align = 0;
3681 spin_lock(&resource_alignment_lock);
3682 p = resource_alignment_param;
3685 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3691 if (sscanf(p, "%x:%x:%x.%x%n",
3692 &seg, &bus, &slot, &func, &count) != 4) {
3694 if (sscanf(p, "%x:%x.%x%n",
3695 &bus, &slot, &func, &count) != 3) {
3696 /* Invalid format */
3697 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3703 if (seg == pci_domain_nr(dev->bus) &&
3704 bus == dev->bus->number &&
3705 slot == PCI_SLOT(dev->devfn) &&
3706 func == PCI_FUNC(dev->devfn)) {
3707 if (align_order == -1) {
3710 align = 1 << align_order;
3715 if (*p != ';' && *p != ',') {
3716 /* End of param or invalid format */
3721 spin_unlock(&resource_alignment_lock);
3726 * pci_is_reassigndev - check if specified PCI is target device to reassign
3727 * @dev: the PCI device to check
3729 * RETURNS: non-zero for PCI device is a target device to reassign,
3732 int pci_is_reassigndev(struct pci_dev *dev)
3734 return (pci_specified_resource_alignment(dev) != 0);
3738 * This function disables memory decoding and releases memory resources
3739 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3740 * It also rounds up size to specified alignment.
3741 * Later on, the kernel will assign page-aligned memory resource back
3744 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3748 resource_size_t align, size;
3751 if (!pci_is_reassigndev(dev))
3754 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3755 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3757 "Can't reassign resources to host bridge.\n");
3762 "Disabling memory decoding and releasing memory resources.\n");
3763 pci_read_config_word(dev, PCI_COMMAND, &command);
3764 command &= ~PCI_COMMAND_MEMORY;
3765 pci_write_config_word(dev, PCI_COMMAND, command);
3767 align = pci_specified_resource_alignment(dev);
3768 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3769 r = &dev->resource[i];
3770 if (!(r->flags & IORESOURCE_MEM))
3772 size = resource_size(r);
3776 "Rounding up size of resource #%d to %#llx.\n",
3777 i, (unsigned long long)size);
3782 /* Need to disable bridge's resource window,
3783 * to enable the kernel to reassign new resource
3786 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3787 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3788 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3789 r = &dev->resource[i];
3790 if (!(r->flags & IORESOURCE_MEM))
3792 r->end = resource_size(r) - 1;
3795 pci_disable_bridge_window(dev);
3799 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3801 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3802 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3803 spin_lock(&resource_alignment_lock);
3804 strncpy(resource_alignment_param, buf, count);
3805 resource_alignment_param[count] = '\0';
3806 spin_unlock(&resource_alignment_lock);
3810 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3813 spin_lock(&resource_alignment_lock);
3814 count = snprintf(buf, size, "%s", resource_alignment_param);
3815 spin_unlock(&resource_alignment_lock);
3819 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3821 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3824 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3825 const char *buf, size_t count)
3827 return pci_set_resource_alignment_param(buf, count);
3830 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3831 pci_resource_alignment_store);
3833 static int __init pci_resource_alignment_sysfs_init(void)
3835 return bus_create_file(&pci_bus_type,
3836 &bus_attr_resource_alignment);
3839 late_initcall(pci_resource_alignment_sysfs_init);
3841 static void __devinit pci_no_domains(void)
3843 #ifdef CONFIG_PCI_DOMAINS
3844 pci_domains_supported = 0;
3849 * pci_ext_cfg_enabled - can we access extended PCI config space?
3850 * @dev: The PCI device of the root bridge.
3852 * Returns 1 if we can access PCI extended config space (offsets
3853 * greater than 0xff). This is the default implementation. Architecture
3854 * implementations can override this.
3856 int __weak pci_ext_cfg_avail(struct pci_dev *dev)
3861 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3864 EXPORT_SYMBOL(pci_fixup_cardbus);
3866 static int __init pci_setup(char *str)
3869 char *k = strchr(str, ',');
3872 if (*str && (str = pcibios_setup(str)) && *str) {
3873 if (!strcmp(str, "nomsi")) {
3875 } else if (!strcmp(str, "noaer")) {
3877 } else if (!strncmp(str, "realloc=", 8)) {
3878 pci_realloc_get_opt(str + 8);
3879 } else if (!strncmp(str, "realloc", 7)) {
3880 pci_realloc_get_opt("on");
3881 } else if (!strcmp(str, "nodomains")) {
3883 } else if (!strncmp(str, "noari", 5)) {
3884 pcie_ari_disabled = true;
3885 } else if (!strncmp(str, "cbiosize=", 9)) {
3886 pci_cardbus_io_size = memparse(str + 9, &str);
3887 } else if (!strncmp(str, "cbmemsize=", 10)) {
3888 pci_cardbus_mem_size = memparse(str + 10, &str);
3889 } else if (!strncmp(str, "resource_alignment=", 19)) {
3890 pci_set_resource_alignment_param(str + 19,
3892 } else if (!strncmp(str, "ecrc=", 5)) {
3893 pcie_ecrc_get_policy(str + 5);
3894 } else if (!strncmp(str, "hpiosize=", 9)) {
3895 pci_hotplug_io_size = memparse(str + 9, &str);
3896 } else if (!strncmp(str, "hpmemsize=", 10)) {
3897 pci_hotplug_mem_size = memparse(str + 10, &str);
3898 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3899 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3900 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3901 pcie_bus_config = PCIE_BUS_SAFE;
3902 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3903 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3904 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3905 pcie_bus_config = PCIE_BUS_PEER2PEER;
3906 } else if (!strncmp(str, "pcie_scan_all", 13)) {
3907 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
3909 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3917 early_param("pci", pci_setup);
3919 EXPORT_SYMBOL(pci_reenable_device);
3920 EXPORT_SYMBOL(pci_enable_device_io);
3921 EXPORT_SYMBOL(pci_enable_device_mem);
3922 EXPORT_SYMBOL(pci_enable_device);
3923 EXPORT_SYMBOL(pcim_enable_device);
3924 EXPORT_SYMBOL(pcim_pin_device);
3925 EXPORT_SYMBOL(pci_disable_device);
3926 EXPORT_SYMBOL(pci_find_capability);
3927 EXPORT_SYMBOL(pci_bus_find_capability);
3928 EXPORT_SYMBOL(pci_release_regions);
3929 EXPORT_SYMBOL(pci_request_regions);
3930 EXPORT_SYMBOL(pci_request_regions_exclusive);
3931 EXPORT_SYMBOL(pci_release_region);
3932 EXPORT_SYMBOL(pci_request_region);
3933 EXPORT_SYMBOL(pci_request_region_exclusive);
3934 EXPORT_SYMBOL(pci_release_selected_regions);
3935 EXPORT_SYMBOL(pci_request_selected_regions);
3936 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3937 EXPORT_SYMBOL(pci_set_master);
3938 EXPORT_SYMBOL(pci_clear_master);
3939 EXPORT_SYMBOL(pci_set_mwi);
3940 EXPORT_SYMBOL(pci_try_set_mwi);
3941 EXPORT_SYMBOL(pci_clear_mwi);
3942 EXPORT_SYMBOL_GPL(pci_intx);
3943 EXPORT_SYMBOL(pci_assign_resource);
3944 EXPORT_SYMBOL(pci_find_parent_resource);
3945 EXPORT_SYMBOL(pci_select_bars);
3947 EXPORT_SYMBOL(pci_set_power_state);
3948 EXPORT_SYMBOL(pci_save_state);
3949 EXPORT_SYMBOL(pci_restore_state);
3950 EXPORT_SYMBOL(pci_pme_capable);
3951 EXPORT_SYMBOL(pci_pme_active);
3952 EXPORT_SYMBOL(pci_wake_from_d3);
3953 EXPORT_SYMBOL(pci_target_state);
3954 EXPORT_SYMBOL(pci_prepare_to_sleep);
3955 EXPORT_SYMBOL(pci_back_from_sleep);
3956 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);