drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #include <command.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <pci.h>
  37
  38 #define PCI_HOSE_OP(rw, size, type)                                     \
  39 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  40                                   pci_dev_t dev,                        \
  41                                   int offset, type value)               \
  42 {                                                                       \
  43         return hose->rw##_##size(hose, dev, offset, value);             \
  44 }
  45
  46 PCI_HOSE_OP(read, byte, u8 *)
  47 PCI_HOSE_OP(read, word, u16 *)
  48 PCI_HOSE_OP(read, dword, u32 *)
  49 PCI_HOSE_OP(write, byte, u8)
  50 PCI_HOSE_OP(write, word, u16)
  51 PCI_HOSE_OP(write, dword, u32)
  52
  53 #define PCI_OP(rw, size, type, error_code)                              \
  54 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  55 {                                                                       \
  56         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  57                                                                         \
  58         if (!hose)                                                      \
  59         {                                                               \
  60                 error_code;                                             \
  61                 return -1;                                              \
  62         }                                                               \
  63                                                                         \
  64         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  65 }
  66
  67 PCI_OP(read, byte, u8 *, *value = 0xff)
  68 PCI_OP(read, word, u16 *, *value = 0xffff)
  69 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  70 PCI_OP(write, byte, u8, )
  71 PCI_OP(write, word, u16, )
  72 PCI_OP(write, dword, u32, )
  73
  74 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  75 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  76                                         pci_dev_t dev,                  \
  77                                         int offset, type val)           \
  78 {                                                                       \
  79         u32 val32;                                                      \
  80                                                                         \
  81         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  82                 *val = -1;                                              \
  83                 return -1;                                              \
  84         }                                                               \
  85                                                                         \
  86         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  87                                                                         \
  88         return 0;                                                       \
  89 }
  90
  91 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  92 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  93                                              pci_dev_t dev,             \
  94                                              int offset, type val)      \
  95 {                                                                       \
  96         u32 val32, mask, ldata, shift;                                  \
  97                                                                         \
  98         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  99                 return -1;                                              \
 100                                                                         \
 101         shift = ((offset & (int)off_mask) * 8);                         \
 102         ldata = (((unsigned long)val) & val_mask) << shift;             \
 103         mask = val_mask << shift;                                       \
 104         val32 = (val32 & ~mask) | ldata;                                \
 105                                                                         \
 106         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 107                 return -1;                                              \
 108                                                                         \
 109         return 0;                                                       \
 110 }
 111
 112 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 113 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 114 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 115 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 116
 117 /* Get a virtual address associated with a BAR region */
 118 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 119 {
 120         pci_addr_t pci_bus_addr;
 121         u32 bar_response;
 122
 123         /* read BAR address */
 124         pci_read_config_dword(pdev, bar, &bar_response);
 125         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 126
 127         /*
 128          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 129          * isn't actualy used on any platform because u-boot assumes a static
 130          * linear mapping.  In the future, this could read the BAR size
 131          * and pass that as the size if needed.
 132          */
 133         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 134 }
 135
 136 /*
 137  *
 138  */
 139
 140 static struct pci_controller* hose_head;
 141
 142 void pci_register_hose(struct pci_controller* hose)
 143 {
 144         struct pci_controller **phose = &hose_head;
 145
 146         while(*phose)
 147                 phose = &(*phose)->next;
 148
 149         hose->next = NULL;
 150
 151         *phose = hose;
 152 }
 153
 154 struct pci_controller *pci_bus_to_hose(int bus)
 155 {
 156         struct pci_controller *hose;
 157
 158         for (hose = hose_head; hose; hose = hose->next) {
 159                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 160                         return hose;
 161         }
 162
 163         printf("pci_bus_to_hose() failed\n");
 164         return NULL;
 165 }
 166
 167 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 168 {
 169         struct pci_controller *hose;
 170
 171         for (hose = hose_head; hose; hose = hose->next) {
 172                 if (hose->cfg_addr == cfg_addr)
 173                         return hose;
 174         }
 175
 176         return NULL;
 177 }
 178
 179 int pci_last_busno(void)
 180 {
 181         struct pci_controller *hose = hose_head;
 182
 183         if (!hose)
 184                 return -1;
 185
 186         while (hose->next)
 187                 hose = hose->next;
 188
 189         return hose->last_busno;
 190 }
 191
 192 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 193 {
 194         struct pci_controller * hose;
 195         u16 vendor, device;
 196         u8 header_type;
 197         pci_dev_t bdf;
 198         int i, bus, found_multi = 0;
 199
 200         for (hose = hose_head; hose; hose = hose->next) {
 201 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 202                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 203 #else
 204                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 205 #endif
 206                         for (bdf = PCI_BDF(bus, 0, 0);
 207 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 208                              bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
 209                                 PCI_MAX_PCI_FUNCTIONS - 1);
 210 #else
 211                              bdf < PCI_BDF(bus + 1, 0, 0);
 212 #endif
 213                              bdf += PCI_BDF(0, 0, 1)) {
 214                                 if (!PCI_FUNC(bdf)) {
 215                                         pci_read_config_byte(bdf,
 216                                                              PCI_HEADER_TYPE,
 217                                                              &header_type);
 218
 219                                         found_multi = header_type & 0x80;
 220                                 } else {
 221                                         if (!found_multi)
 222                                                 continue;
 223                                 }
 224
 225                                 pci_read_config_word(bdf,
 226                                                      PCI_VENDOR_ID,
 227                                                      &vendor);
 228                                 pci_read_config_word(bdf,
 229                                                      PCI_DEVICE_ID,
 230                                                      &device);
 231
 232                                 for (i = 0; ids[i].vendor != 0; i++) {
 233                                         if (vendor == ids[i].vendor &&
 234                                             device == ids[i].device) {
 235                                                 if (index <= 0)
 236                                                         return bdf;
 237
 238                                                 index--;
 239                                         }
 240                                 }
 241                         }
 242         }
 243
 244         return -1;
 245 }
 246
 247 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 248 {
 249         static struct pci_device_id ids[2] = {{}, {0, 0}};
 250
 251         ids[0].vendor = vendor;
 252         ids[0].device = device;
 253
 254         return pci_find_devices(ids, index);
 255 }
 256
 257 /*
 258  *
 259  */
 260
 261 int __pci_hose_phys_to_bus(struct pci_controller *hose,
 262                                 phys_addr_t phys_addr,
 263                                 unsigned long flags,
 264                                 unsigned long skip_mask,
 265                                 pci_addr_t *ba)
 266 {
 267         struct pci_region *res;
 268         pci_addr_t bus_addr;
 269         int i;
 270
 271         for (i = 0; i < hose->region_count; i++) {
 272                 res = &hose->regions[i];
 273
 274                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 275                         continue;
 276
 277                 if (res->flags & skip_mask)
 278                         continue;
 279
 280                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 281
 282                 if (bus_addr >= res->bus_start &&
 283                         bus_addr < res->bus_start + res->size) {
 284                         *ba = bus_addr;
 285                         return 0;
 286                 }
 287         }
 288
 289         return 1;
 290 }
 291
 292 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 293                                     phys_addr_t phys_addr,
 294                                     unsigned long flags)
 295 {
 296         pci_addr_t bus_addr = 0;
 297         int ret;
 298
 299         if (!hose) {
 300                 puts("pci_hose_phys_to_bus: invalid hose\n");
 301                 return bus_addr;
 302         }
 303
 304         /*
 305          * if PCI_REGION_MEM is set we do a two pass search with preference
 306          * on matches that don't have PCI_REGION_SYS_MEMORY set
 307          */
 308         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 309                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 310                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 311                 if (!ret)
 312                         return bus_addr;
 313         }
 314
 315         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 316
 317         if (ret)
 318                 puts("pci_hose_phys_to_bus: invalid physical address\n");
 319
 320         return bus_addr;
 321 }
 322
 323 int __pci_hose_bus_to_phys(struct pci_controller *hose,
 324                                 pci_addr_t bus_addr,
 325                                 unsigned long flags,
 326                                 unsigned long skip_mask,
 327                                 phys_addr_t *pa)
 328 {
 329         struct pci_region *res;
 330         int i;
 331
 332         for (i = 0; i < hose->region_count; i++) {
 333                 res = &hose->regions[i];
 334
 335                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 336                         continue;
 337
 338                 if (res->flags & skip_mask)
 339                         continue;
 340
 341                 if (bus_addr >= res->bus_start &&
 342                         bus_addr < res->bus_start + res->size) {
 343                         *pa = (bus_addr - res->bus_start + res->phys_start);
 344                         return 0;
 345                 }
 346         }
 347
 348         return 1;
 349 }
 350
 351 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 352                                  pci_addr_t bus_addr,
 353                                  unsigned long flags)
 354 {
 355         phys_addr_t phys_addr = 0;
 356         int ret;
 357
 358         if (!hose) {
 359                 puts("pci_hose_bus_to_phys: invalid hose\n");
 360                 return phys_addr;
 361         }
 362
 363         /*
 364          * if PCI_REGION_MEM is set we do a two pass search with preference
 365          * on matches that don't have PCI_REGION_SYS_MEMORY set
 366          */
 367         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 368                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 369                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 370                 if (!ret)
 371                         return phys_addr;
 372         }
 373
 374         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 375
 376         if (ret)
 377                 puts("pci_hose_bus_to_phys: invalid physical address\n");
 378
 379         return phys_addr;
 380 }
 381
 382 /*
 383  *
 384  */
 385
 386 int pci_hose_config_device(struct pci_controller *hose,
 387                            pci_dev_t dev,
 388                            unsigned long io,
 389                            pci_addr_t mem,
 390                            unsigned long command)
 391 {
 392         u32 bar_response;
 393         unsigned int old_command;
 394         pci_addr_t bar_value;
 395         pci_size_t bar_size;
 396         unsigned char pin;
 397         int bar, found_mem64;
 398
 399         debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
 400                 (u64)mem, command);
 401
 402         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
 403
 404         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
 405                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 406                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 407
 408                 if (!bar_response)
 409                         continue;
 410
 411                 found_mem64 = 0;
 412
 413                 /* Check the BAR type and set our address mask */
 414                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 415                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 416                         /* round up region base address to a multiple of size */
 417                         io = ((io - 1) | (bar_size - 1)) + 1;
 418                         bar_value = io;
 419                         /* compute new region base address */
 420                         io = io + bar_size;
 421                 } else {
 422                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 423                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 424                                 u32 bar_response_upper;
 425                                 u64 bar64;
 426                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 427                                         0xffffffff);
 428                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 429                                         &bar_response_upper);
 430
 431                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 432
 433                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 434                                 found_mem64 = 1;
 435                         } else {
 436                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 437                         }
 438
 439                         /* round up region base address to multiple of size */
 440                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 441                         bar_value = mem;
 442                         /* compute new region base address */
 443                         mem = mem + bar_size;
 444                 }
 445
 446                 /* Write it out and update our limit */
 447                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 448
 449                 if (found_mem64) {
 450                         bar += 4;
 451 #ifdef CONFIG_SYS_PCI_64BIT
 452                         pci_hose_write_config_dword(hose, dev, bar,
 453                                 (u32)(bar_value >> 32));
 454 #else
 455                         pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 456 #endif
 457                 }
 458         }
 459
 460         /* Configure Cache Line Size Register */
 461         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 462
 463         /* Configure Latency Timer */
 464         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 465
 466         /* Disable interrupt line, if device says it wants to use interrupts */
 467         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
 468         if (pin != 0) {
 469                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
 470         }
 471
 472         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
 473         pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
 474                                      (old_command & 0xffff0000) | command);
 475
 476         return 0;
 477 }
 478
 479 /*
 480  *
 481  */
 482
 483 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 484                                          unsigned short class,
 485                                          unsigned int vendor,
 486                                          unsigned int device,
 487                                          unsigned int bus,
 488                                          unsigned int dev,
 489                                          unsigned int func)
 490 {
 491         struct pci_config_table *table;
 492
 493         for (table = hose->config_table; table && table->vendor; table++) {
 494                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 495                     (table->device == PCI_ANY_ID || table->device == device) &&
 496                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 497                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 498                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 499                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 500                         return table;
 501                 }
 502         }
 503
 504         return NULL;
 505 }
 506
 507 void pci_cfgfunc_config_device(struct pci_controller *hose,
 508                                pci_dev_t dev,
 509                                struct pci_config_table *entry)
 510 {
 511         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
 512                 entry->priv[2]);
 513 }
 514
 515 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 516                             pci_dev_t dev, struct pci_config_table *entry)
 517 {
 518 }
 519
 520 /*
 521  * HJF: Changed this to return int. I think this is required
 522  * to get the correct result when scanning bridges
 523  */
 524 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 525
 526 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
 527 const char * pci_class_str(u8 class)
 528 {
 529         switch (class) {
 530         case PCI_CLASS_NOT_DEFINED:
 531                 return "Build before PCI Rev2.0";
 532                 break;
 533         case PCI_BASE_CLASS_STORAGE:
 534                 return "Mass storage controller";
 535                 break;
 536         case PCI_BASE_CLASS_NETWORK:
 537                 return "Network controller";
 538                 break;
 539         case PCI_BASE_CLASS_DISPLAY:
 540                 return "Display controller";
 541                 break;
 542         case PCI_BASE_CLASS_MULTIMEDIA:
 543                 return "Multimedia device";
 544                 break;
 545         case PCI_BASE_CLASS_MEMORY:
 546                 return "Memory controller";
 547                 break;
 548         case PCI_BASE_CLASS_BRIDGE:
 549                 return "Bridge device";
 550                 break;
 551         case PCI_BASE_CLASS_COMMUNICATION:
 552                 return "Simple comm. controller";
 553                 break;
 554         case PCI_BASE_CLASS_SYSTEM:
 555                 return "Base system peripheral";
 556                 break;
 557         case PCI_BASE_CLASS_INPUT:
 558                 return "Input device";
 559                 break;
 560         case PCI_BASE_CLASS_DOCKING:
 561                 return "Docking station";
 562                 break;
 563         case PCI_BASE_CLASS_PROCESSOR:
 564                 return "Processor";
 565                 break;
 566         case PCI_BASE_CLASS_SERIAL:
 567                 return "Serial bus controller";
 568                 break;
 569         case PCI_BASE_CLASS_INTELLIGENT:
 570                 return "Intelligent controller";
 571                 break;
 572         case PCI_BASE_CLASS_SATELLITE:
 573                 return "Satellite controller";
 574                 break;
 575         case PCI_BASE_CLASS_CRYPT:
 576                 return "Cryptographic device";
 577                 break;
 578         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
 579                 return "DSP";
 580                 break;
 581         case PCI_CLASS_OTHERS:
 582                 return "Does not fit any class";
 583                 break;
 584         default:
 585         return  "???";
 586                 break;
 587         };
 588 }
 589 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 590
 591 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 592 {
 593         /*
 594          * Check if pci device should be skipped in configuration
 595          */
 596         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 597 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 598                 /*
 599                  * Only skip configuration if "pciconfighost" is not set
 600                  */
 601                 if (getenv("pciconfighost") == NULL)
 602                         return 1;
 603 #else
 604                 return 1;
 605 #endif
 606         }
 607
 608         return 0;
 609 }
 610 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 611         __attribute__((weak, alias("__pci_skip_dev")));
 612
 613 #ifdef CONFIG_PCI_SCAN_SHOW
 614 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 615 {
 616         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 617                 return 0;
 618
 619         return 1;
 620 }
 621 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 622         __attribute__((weak, alias("__pci_print_dev")));
 623 #endif /* CONFIG_PCI_SCAN_SHOW */
 624
 625 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 626 {
 627         unsigned int sub_bus, found_multi = 0;
 628         unsigned short vendor, device, class;
 629         unsigned char header_type;
 630 #ifndef CONFIG_PCI_PNP
 631         struct pci_config_table *cfg;
 632 #endif
 633         pci_dev_t dev;
 634 #ifdef CONFIG_PCI_SCAN_SHOW
 635         static int indent = 0;
 636 #endif
 637
 638         sub_bus = bus;
 639
 640         for (dev =  PCI_BDF(bus,0,0);
 641              dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
 642                                 PCI_MAX_PCI_FUNCTIONS - 1);
 643              dev += PCI_BDF(0, 0, 1)) {
 644
 645                 if (pci_skip_dev(hose, dev))
 646                         continue;
 647
 648                 if (PCI_FUNC(dev) && !found_multi)
 649                         continue;
 650
 651                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 652
 653                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 654
 655                 if (vendor == 0xffff || vendor == 0x0000)
 656                         continue;
 657
 658                 if (!PCI_FUNC(dev))
 659                         found_multi = header_type & 0x80;
 660
 661                 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 662                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 663
 664                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 665                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 666
 667 #ifdef CONFIG_PCI_SCAN_SHOW
 668                 indent++;
 669
 670                 /* Print leading space, including bus indentation */
 671                 printf("%*c", indent + 1, ' ');
 672
 673                 if (pci_print_dev(hose, dev)) {
 674                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
 675                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
 676                                vendor, device, pci_class_str(class >> 8));
 677                 }
 678 #endif
 679
 680 #ifdef CONFIG_PCI_PNP
 681                 sub_bus = max(pciauto_config_device(hose, dev), sub_bus);
 682 #else
 683                 cfg = pci_find_config(hose, class, vendor, device,
 684                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 685                 if (cfg) {
 686                         cfg->config_device(hose, dev, cfg);
 687                         sub_bus = max(sub_bus, hose->current_busno);
 688                 }
 689 #endif
 690
 691 #ifdef CONFIG_PCI_SCAN_SHOW
 692                 indent--;
 693 #endif
 694
 695                 if (hose->fixup_irq)
 696                         hose->fixup_irq(hose, dev);
 697         }
 698
 699         return sub_bus;
 700 }
 701
 702 int pci_hose_scan(struct pci_controller *hose)
 703 {
 704 #if defined(CONFIG_PCI_BOOTDELAY)
 705         static int pcidelay_done;
 706         char *s;
 707         int i;
 708
 709         if (!pcidelay_done) {
 710                 /* wait "pcidelay" ms (if defined)... */
 711                 s = getenv("pcidelay");
 712                 if (s) {
 713                         int val = simple_strtoul(s, NULL, 10);
 714                         for (i = 0; i < val; i++)
 715                                 udelay(1000);
 716                 }
 717                 pcidelay_done = 1;
 718         }
 719 #endif /* CONFIG_PCI_BOOTDELAY */
 720
 721         /*
 722          * Start scan at current_busno.
 723          * PCIe will start scan at first_busno+1.
 724          */
 725         /* For legacy support, ensure current >= first */
 726         if (hose->first_busno > hose->current_busno)
 727                 hose->current_busno = hose->first_busno;
 728 #ifdef CONFIG_PCI_PNP
 729         pciauto_config_init(hose);
 730 #endif
 731         return pci_hose_scan_bus(hose, hose->current_busno);
 732 }
 733
 734 void pci_init(void)
 735 {
 736         hose_head = NULL;
 737
 738         /* now call board specific pci_init()... */
 739         pci_init_board();
 740 }